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Commit 05d54b827fa84b7834fc39c9ff7bb77cce829beb

Authored by Fabio Estevam
Committed by Stefano Babic
1 parent e153333eeb
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mx6: Add support for the mx6solox variant 

mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 8 changed files with 369 additions and 7 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/clock.c
Diff comments   View file @ 05d54b8
... ... @@ -214,7 +214,7 @@
214 214 u32 reg, uart_podf;
215 215 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
216 216 reg = __raw_readl(&imx_ccm->cscdr1);
217   -#ifdef CONFIG_MX6SL
  217 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
218 218 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
219 219 freq = MXC_HCLK;
220 220 #endif
... ... @@ -282,7 +282,7 @@
282 282 return root_freq / (emi_slow_podf + 1);
283 283 }
284 284  
285   -#ifdef CONFIG_MX6SL
  285 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
286 286 static u32 get_mmdc_ch0_clk(void)
287 287 {
288 288 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 05d54b8
... ... @@ -79,9 +79,15 @@
79 79 void init_aips(void)
80 80 {
81 81 struct aipstz_regs *aips1, *aips2;
  82 +#ifdef CONFIG_MX6SX
  83 + struct aipstz_regs *aips3;
  84 +#endif
82 85  
83 86 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
84 87 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  88 +#ifdef CONFIG_MX6SX
  89 + aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
  90 +#endif
85 91  
86 92 /*
87 93 * Set all MPROTx to be non-bufferable, trusted for R/W,
... ... @@ -107,6 +113,26 @@
107 113 writel(0x00000000, &aips2->opacr2);
108 114 writel(0x00000000, &aips2->opacr3);
109 115 writel(0x00000000, &aips2->opacr4);
  116 +
  117 +#ifdef CONFIG_MX6SX
  118 + /*
  119 + * Set all MPROTx to be non-bufferable, trusted for R/W,
  120 + * not forced to user-mode.
  121 + */
  122 + writel(0x77777777, &aips3->mprot0);
  123 + writel(0x77777777, &aips3->mprot1);
  124 +
  125 + /*
  126 + * Set all OPACRx to be non-bufferable, not require
  127 + * supervisor privilege level for access,allow for
  128 + * write access and untrusted master access.
  129 + */
  130 + writel(0x00000000, &aips3->opacr0);
  131 + writel(0x00000000, &aips3->opacr1);
  132 + writel(0x00000000, &aips3->opacr2);
  133 + writel(0x00000000, &aips3->opacr3);
  134 + writel(0x00000000, &aips3->opacr4);
  135 +#endif
110 136 }
111 137  
112 138 static void clear_ldo_ramp(void)
arch/arm/imx-common/cpu.c
Diff comments   View file @ 05d54b8
... ... @@ -112,6 +112,8 @@
112 112 return "6SOLO"; /* Solo version of the mx6 */
113 113 case MXC_CPU_MX6SL:
114 114 return "6SL"; /* Solo-Lite version of the mx6 */
  115 + case MXC_CPU_MX6SX:
  116 + return "6SX"; /* SoloX version of the mx6 */
115 117 case MXC_CPU_MX51:
116 118 return "51";
117 119 case MXC_CPU_MX53:
arch/arm/include/asm/arch-imx/cpu.h
Diff comments   View file @ 05d54b8
... ... @@ -8,7 +8,8 @@
8 8 #define MXC_CPU_MX53 0x53
9 9 #define MXC_CPU_MX6SL 0x60
10 10 #define MXC_CPU_MX6DL 0x61
11   -#define MXC_CPU_MX6SOLO 0x62
  11 +#define MXC_CPU_MX6SX 0x62
12 12 #define MXC_CPU_MX6Q 0x63
13 13 #define MXC_CPU_MX6D 0x64
  14 +#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
arch/arm/include/asm/arch-mx6/crm_regs.h
Diff comments   View file @ 05d54b8
... ... @@ -113,7 +113,11 @@
113 113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
114 114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
115 115 #define MXC_CCM_CCR_COSC_EN (1 << 12)
  116 +#ifdef CONFIG_MX6SX
  117 +#define MXC_CCM_CCR_OSCNT_MASK 0x7F
  118 +#else
116 119 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
  120 +#endif
117 121 #define MXC_CCM_CCR_OSCNT_OFFSET 0
118 122  
119 123 /* Define the bits in register CCDR */
120 124  
... ... @@ -146,8 +150,10 @@
146 150 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
147 151 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
148 152 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
  153 +#ifndef CONFIG_MX6SX
149 154 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
150 155 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
  156 +#endif
151 157 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
152 158 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
153 159 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
154 160  
155 161  
156 162  
157 163  
158 164  
159 165  
160 166  
161 167  
... ... @@ -173,28 +179,40 @@
173 179 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
174 180 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
175 181 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
  182 +#ifndef CONFIG_MX6SX
176 183 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
177 184 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
178 185 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
179 186 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
  187 +#endif
180 188 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
181 189 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
  190 +#ifndef CONFIG_MX6SX
182 191 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
  192 +#endif
183 193 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
184 194 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
185 195 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
186 196 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
187 197 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
  198 +#ifndef CONFIG_MX6SX
188 199 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
189 200 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
  201 +#endif
190 202  
191 203 /* Define the bits in register CSCMR1 */
192 204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
193 205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
  206 +#ifdef CONFIG_MX6SX
  207 +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
  208 +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
  209 +#else
194 210 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
195 211 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
  212 +#endif
196 213 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
197 214 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
  215 +/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
198 216 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
199 217 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
200 218 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
201 219  
202 220  
203 221  
204 222  
205 223  
... ... @@ -207,19 +225,38 @@
207 225 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
208 226 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
209 227 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
  228 +#ifdef CONFIG_MX6SX
  229 +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
  230 +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
  231 +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
  232 +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
  233 +#endif
210 234 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
211 235  
212 236 /* Define the bits in register CSCMR2 */
  237 +#ifdef CONFIG_MX6SX
  238 +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
  239 +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
  240 +#endif
213 241 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
214 242 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
215 243 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
216 244 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
  245 +#ifdef CONFIG_MX6SX
  246 +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
  247 +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
  248 +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
  249 +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
  250 +#else
217 251 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
218 252 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
  253 +#endif
219 254  
220 255 /* Define the bits in register CSCDR1 */
  256 +#ifndef CONFIG_MX6SX
221 257 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
222 258 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
  259 +#endif
223 260 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
224 261 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
225 262 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
226 263  
227 264  
228 265  
229 266  
... ... @@ -228,21 +265,28 @@
228 265 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
229 266 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
230 267 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
  268 +#ifndef CONFIG_MX6SX
231 269 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
232 270 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
233 271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
234 272 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
  273 +#endif
235 274 #ifdef CONFIG_MX6SL
236 275 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
237 276 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
238 277 #else
239 278 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
  279 +#ifdef CONFIG_MX6SX
  280 +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
240 281 #endif
  282 +#endif
241 283 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
242 284  
243 285 /* Define the bits in register CS1CDR */
244 286 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
245 287 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
  288 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
  289 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
246 290 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
247 291 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
248 292 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
... ... @@ -253,6 +297,17 @@
253 297 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
254 298  
255 299 /* Define the bits in register CS2CDR */
  300 +#ifdef CONFIG_MX6SX
  301 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
  302 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
  303 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
  304 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
  305 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
  306 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
  307 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
  308 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
  309 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
  310 +#else
256 311 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
257 312 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
258 313 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
... ... @@ -262,6 +317,7 @@
262 317 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
263 318 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
264 319 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
  320 +#endif
265 321 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
266 322 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
267 323 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
268 324  
... ... @@ -272,9 +328,11 @@
272 328 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
273 329  
274 330 /* Define the bits in register CDCDR */
  331 +#ifndef CONFIG_MX6SX
275 332 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
276 333 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
277 334 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
  335 +#endif
278 336 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
279 337 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
280 338 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
... ... @@ -289,6 +347,20 @@
289 347 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
290 348  
291 349 /* Define the bits in register CHSCCDR */
  350 +#ifdef CONFIG_MX6SX
  351 +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
  352 +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
  353 +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
  354 +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
  355 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
  356 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
  357 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
  358 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
  359 +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
  360 +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
  361 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
  362 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
  363 +#else
292 364 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
293 365 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
294 366 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
... ... @@ -301,6 +373,7 @@
301 373 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
302 374 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
303 375 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
  376 +#endif
304 377  
305 378 #define CHSCCDR_CLK_SEL_LDB_DI0 3
306 379 #define CHSCCDR_PODF_DIVIDE_BY_3 2
307 380  
... ... @@ -309,12 +382,14 @@
309 382 /* Define the bits in register CSCDR2 */
310 383 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
311 384 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
  385 +/* All IPU2_DI1 are LCDIF1 on MX6SX */
312 386 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
313 387 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
314 388 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
315 389 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
316 390 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
317 391 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
  392 +/* All IPU2_DI0 are LCDIF2 on MX6SX */
318 393 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
319 394 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
320 395 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
321 396  
... ... @@ -335,7 +410,9 @@
335 410 /* Define the bits in register CDHIPR */
336 411 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
337 412 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
  413 +#ifndef CONFIG_MX6SX
338 414 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
  415 +#endif
339 416 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
340 417 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
341 418 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
342 419  
343 420  
344 421  
... ... @@ -344,13 +421,17 @@
344 421 /* Define the bits in register CLPCR */
345 422 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
346 423 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
  424 +#ifndef CONFIG_MX6SX
347 425 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
348 426 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
349 427 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
  428 +#endif
350 429 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
351 430 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
  431 +#ifndef CONFIG_MX6SX
352 432 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
353 433 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
  434 +#endif
354 435 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
355 436 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
356 437 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
357 438  
358 439  
359 440  
... ... @@ -359,15 +440,19 @@
359 440 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
360 441 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
361 442 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
  443 +#ifndef CONFIG_MX6SX
362 444 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
363 445 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
364 446 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
  447 +#endif
365 448 #define MXC_CCM_CLPCR_LPM_MASK 0x3
366 449 #define MXC_CCM_CLPCR_LPM_OFFSET 0
367 450  
368 451 /* Define the bits in register CISR */
369 452 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
  453 +#ifndef CONFIG_MX6SX
370 454 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
  455 +#endif
371 456 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
372 457 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
373 458 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
374 459  
... ... @@ -378,7 +463,9 @@
378 463  
379 464 /* Define the bits in register CIMR */
380 465 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
  466 +#ifndef CONFIG_MX6SX
381 467 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
  468 +#endif
382 469 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
383 470 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
384 471 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
... ... @@ -393,6 +480,7 @@
393 480 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
394 481 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
395 482 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
  483 +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
396 484 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
397 485 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
398 486 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
... ... @@ -400,6 +488,7 @@
400 488 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
401 489  
402 490 /* Define the bits in registers CGPR */
  491 +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
403 492 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
404 493 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
405 494 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
406 495  
... ... @@ -435,8 +524,13 @@
435 524 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
436 525 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
437 526 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
  527 +#ifdef CONFIG_MX6SX
  528 +#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
  529 +#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
  530 +#else
438 531 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
439 532 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
  533 +#endif
440 534  
441 535 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
442 536 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
443 537  
444 538  
445 539  
446 540  
447 541  
448 542  
449 543  
450 544  
... ... @@ -448,27 +542,48 @@
448 542 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
449 543 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
450 544 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
  545 +#ifndef CONFIG_MX6SX
451 546 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
452 547 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
  548 +#endif
453 549 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
454 550 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
455 551 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
456 552 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
457 553 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
458 554 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
  555 +#ifdef CONFIG_MX6SX
  556 +#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
  557 +#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
  558 +#endif
459 559 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
460 560 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
461 561 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
462 562 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
  563 +#ifndef CONFIG_MX6SX
463 564 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
464 565 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
  566 +#endif
465 567 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
466 568 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
  569 +#ifdef CONFIG_MX6SX
  570 +#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
  571 +#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
  572 +#define MXC_CCM_CCGR1_CANFD_OFFSET 30
  573 +#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
  574 +#endif
467 575  
  576 +#ifndef CONFIG_MX6SX
468 577 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
469 578 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
  579 +#else
  580 +#define MXC_CCM_CCGR2_CSI_OFFSET 2
  581 +#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
  582 +#endif
  583 +#ifndef CONFIG_MX6SX
470 584 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
471 585 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
  586 +#endif
472 587 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
473 588 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
474 589 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
475 590  
476 591  
477 592  
... ... @@ -487,17 +602,33 @@
487 602 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
488 603 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
489 604 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
  605 +#ifdef CONFIG_MX6SX
  606 +#define MXC_CCM_CCGR2_LCD_OFFSET 28
  607 +#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
  608 +#define MXC_CCM_CCGR2_PXP_OFFSET 30
  609 +#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
  610 +#else
490 611 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
491 612 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
492 613 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
493 614 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
  615 +#endif
494 616  
  617 +#ifdef CONFIG_MX6SX
  618 +#define MXC_CCM_CCGR3_M4_OFFSET 2
  619 +#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
  620 +#define MXC_CCM_CCGR3_ENET_OFFSET 4
  621 +#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
  622 +#define MXC_CCM_CCGR3_QSPI_OFFSET 14
  623 +#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
  624 +#else
495 625 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
496 626 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
497 627 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
498 628 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
499 629 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
500 630 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
  631 +#endif
501 632 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
502 633 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
503 634 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
504 635  
505 636  
506 637  
507 638  
508 639  
509 640  
510 641  
... ... @@ -506,29 +637,43 @@
506 637 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
507 638 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
508 639 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
  640 +#ifdef CONFIG_MX6SX
  641 +#define MXC_CCM_CCGR3_QSPI1_OFFSET 14
  642 +#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
  643 +#else
509 644 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
510 645 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
511 646 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
512 647 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
  648 +#endif
513 649 #define MXC_CCM_CCGR3_MLB_OFFSET 18
514 650 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
515 651 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
516 652 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
  653 +#ifndef CONFIG_MX6SX
517 654 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
518 655 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
  656 +#endif
519 657 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
520 658 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
521 659 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
522 660 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
523 661 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
524 662 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
  663 +#ifndef CONFIG_MX6SX
525 664 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
526 665 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
  666 +#endif
527 667  
528 668 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
529 669 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
  670 +#ifdef CONFIG_MX6SX
  671 +#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
  672 +#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
  673 +#else
530 674 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
531 675 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
  676 +#endif
532 677 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
533 678 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
534 679 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
535 680  
... ... @@ -552,8 +697,10 @@
552 697  
553 698 #define MXC_CCM_CCGR5_ROM_OFFSET 0
554 699 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
  700 +#ifndef CONFIG_MX6SX
555 701 #define MXC_CCM_CCGR5_SATA_OFFSET 4
556 702 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
  703 +#endif
557 704 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
558 705 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
559 706 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
... ... @@ -570,6 +717,12 @@
570 717 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
571 718 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
572 719 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
  720 +#ifdef CONFIG_MX6SX
  721 +#define MXC_CCM_CCGR5_SAI1_OFFSET 20
  722 +#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
  723 +#define MXC_CCM_CCGR5_SAI2_OFFSET 30
  724 +#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
  725 +#endif
573 726  
574 727 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
575 728 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
576 729  
... ... @@ -583,8 +736,25 @@
583 736 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
584 737 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
585 738 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
  739 +#ifdef CONFIG_MX6SX
  740 +#define MXC_CCM_CCGR6_PWM8_OFFSET 16
  741 +#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
  742 +#define MXC_CCM_CCGR6_VADC_OFFSET 20
  743 +#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
  744 +#define MXC_CCM_CCGR6_GIS_OFFSET 22
  745 +#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
  746 +#define MXC_CCM_CCGR6_I2C4_OFFSET 24
  747 +#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
  748 +#define MXC_CCM_CCGR6_PWM5_OFFSET 26
  749 +#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
  750 +#define MXC_CCM_CCGR6_PWM6_OFFSET 28
  751 +#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
  752 +#define MXC_CCM_CCGR6_PWM7_OFFSET 30
  753 +#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
  754 +#else
586 755 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
587 756 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
  757 +#endif
588 758  
589 759 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
590 760 #define BP_ANADIG_PLL_SYS_RSVD0 20
arch/arm/include/asm/arch-mx6/imx-regs.h
Diff comments   View file @ 05d54b8
... ... @@ -19,6 +19,19 @@
19 19 #define GPU_2D_ARB_END_ADDR 0x02203FFF
20 20 #define OPENVG_ARB_BASE_ADDR 0x02204000
21 21 #define OPENVG_ARB_END_ADDR 0x02207FFF
  22 +#elif CONFIG_MX6SX
  23 +#define CAAM_ARB_BASE_ADDR 0x00100000
  24 +#define CAAM_ARB_END_ADDR 0x00107FFF
  25 +#define GPU_ARB_BASE_ADDR 0x01800000
  26 +#define GPU_ARB_END_ADDR 0x01803FFF
  27 +#define APBH_DMA_ARB_BASE_ADDR 0x01804000
  28 +#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
  29 +#define M4_BOOTROM_BASE_ADDR 0x007F8000
  30 +
  31 +#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
  32 +#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  33 +#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  34 +
22 35 #else
23 36 #define CAAM_ARB_BASE_ADDR 0x00100000
24 37 #define CAAM_ARB_END_ADDR 0x00103FFF
25 38  
26 39  
... ... @@ -39,14 +52,27 @@
39 52 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
40 53  
41 54 /* GPV - PL301 configuration ports */
42   -#ifdef CONFIG_MX6SL
  55 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
43 56 #define GPV2_BASE_ADDR 0x00D00000
44 57 #else
45 58 #define GPV2_BASE_ADDR 0x00200000
46 59 #endif
47 60  
  61 +#ifdef CONFIG_MX6SX
  62 +#define GPV3_BASE_ADDR 0x00E00000
  63 +#define GPV4_BASE_ADDR 0x00F00000
  64 +#define GPV5_BASE_ADDR 0x01000000
  65 +#define GPV6_BASE_ADDR 0x01100000
  66 +#define PCIE_ARB_BASE_ADDR 0x08000000
  67 +#define PCIE_ARB_END_ADDR 0x08FFFFFF
  68 +
  69 +#else
48 70 #define GPV3_BASE_ADDR 0x00300000
49 71 #define GPV4_BASE_ADDR 0x00800000
  72 +#define PCIE_ARB_BASE_ADDR 0x01000000
  73 +#define PCIE_ARB_END_ADDR 0x01FFFFFF
  74 +#endif
  75 +
50 76 #define IRAM_BASE_ADDR 0x00900000
51 77 #define SCU_BASE_ADDR 0x00A00000
52 78 #define IC_INTERFACES_BASE_ADDR 0x00A00100
53 79  
... ... @@ -56,13 +82,21 @@
56 82 #define L2_PL310_BASE 0x00A02000
57 83 #define GPV0_BASE_ADDR 0x00B00000
58 84 #define GPV1_BASE_ADDR 0x00C00000
59   -#define PCIE_ARB_BASE_ADDR 0x01000000
60   -#define PCIE_ARB_END_ADDR 0x01FFFFFF
61 85  
62 86 #define AIPS1_ARB_BASE_ADDR 0x02000000
63 87 #define AIPS1_ARB_END_ADDR 0x020FFFFF
64 88 #define AIPS2_ARB_BASE_ADDR 0x02100000
65 89 #define AIPS2_ARB_END_ADDR 0x021FFFFF
  90 +#ifdef CONFIG_MX6SX
  91 +#define AIPS3_BASE_ADDR 0x02200000
  92 +#define AIPS3_END_ADDR 0x022FFFFF
  93 +#define WEIM_ARB_BASE_ADDR 0x50000000
  94 +#define WEIM_ARB_END_ADDR 0x57FFFFFF
  95 +#define QSPI1_ARB_BASE_ADDR 0x60000000
  96 +#define QSPI1_ARB_END_ADDR 0x6FFFFFFF
  97 +#define QSPI2_ARB_BASE_ADDR 0x70000000
  98 +#define QSPI2_ARB_END_ADDR 0x7FFFFFFF
  99 +#else
66 100 #define SATA_ARB_BASE_ADDR 0x02200000
67 101 #define SATA_ARB_END_ADDR 0x02203FFF
68 102 #define OPENVG_ARB_BASE_ADDR 0x02204000
69 103  
... ... @@ -75,8 +109,9 @@
75 109 #define IPU2_ARB_END_ADDR 0x02BFFFFF
76 110 #define WEIM_ARB_BASE_ADDR 0x08000000
77 111 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
  112 +#endif
78 113  
79   -#ifdef CONFIG_MX6SL
  114 +#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
80 115 #define MMDC0_ARB_BASE_ADDR 0x80000000
81 116 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
82 117 #define MMDC1_ARB_BASE_ADDR 0xC0000000
83 118  
... ... @@ -88,8 +123,10 @@
88 123 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
89 124 #endif
90 125  
  126 +#ifndef CONFIG_MX6SX
91 127 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
92 128 #define IPU_SOC_OFFSET 0x00200000
  129 +#endif
93 130  
94 131 /* Defines for Blocks connected via AIPS (SkyBlue) */
95 132 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
96 133  
... ... @@ -112,7 +149,9 @@
112 149 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
113 150 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
114 151 #else
  152 +#ifndef CONFIG_MX6SX
115 153 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
  154 +#endif
116 155 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
117 156 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
118 157 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
119 158  
... ... @@ -121,8 +160,10 @@
121 160 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
122 161 #endif
123 162  
  163 +#ifndef CONFIG_MX6SX
124 164 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
125 165 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
  166 +#endif
126 167 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
127 168  
128 169 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
... ... @@ -157,6 +198,13 @@
157 198 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
158 199 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
159 200 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  201 +#elif CONFIG_MX6SX
  202 +#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
  203 +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
  204 +#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
  205 +#define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
  206 +#define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
  207 +#define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
160 208 #else
161 209 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
162 210 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
... ... @@ -193,6 +241,8 @@
193 241 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
194 242 #ifdef CONFIG_MX6SL
195 243 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
  244 +#elif CONFIG_MX6SX
  245 +#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
196 246 #else
197 247 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
198 248 #endif
199 249  
200 250  
201 251  
202 252  
203 253  
... ... @@ -202,13 +252,28 @@
202 252 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
203 253 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
204 254 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
  255 +#ifdef CONFIG_MX6SX
  256 +#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  257 +#else
205 258 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
  259 +#endif
206 260 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
  261 +#ifdef CONFIG_MX6SX
  262 +#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  263 +#else
207 264 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
  265 +#endif
208 266 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
  267 +#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
  268 +#ifdef CONFIG_MX6SX
  269 +#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
  270 +#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
  271 +#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  272 +#else
209 273 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
210 274 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
211 275 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
  276 +#endif
212 277 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
213 278 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
214 279 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
215 280  
216 281  
... ... @@ -216,10 +281,42 @@
216 281 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
217 282 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
218 283  
  284 +#ifdef CONFIG_MX6SX
  285 +#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
  286 +#define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
  287 +#define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
  288 +#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
  289 +#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
  290 +#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
  291 +#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
  292 +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
  293 +#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
  294 +#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
  295 +#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
  296 +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
  297 +#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
  298 +#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
  299 +#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
  300 +#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
  301 +#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
  302 +#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
  303 +#define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
  304 +#define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
  305 +#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
  306 +#define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
  307 +#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
  308 +#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
  309 +#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
  310 +#endif
  311 +
219 312 #define CHIP_REV_1_0 0x10
220 313 #define CHIP_REV_1_2 0x12
221 314 #define CHIP_REV_1_5 0x15
  315 +#ifndef CONFIG_MX6SX
222 316 #define IRAM_SIZE 0x00040000
  317 +#else
  318 +#define IRAM_SIZE 0x00020000
  319 +#endif
223 320 #define FEC_QUIRK_ENET_MAC
224 321  
225 322 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
226 323  
... ... @@ -473,7 +570,23 @@
473 570 u32 rsvd7[4];
474 571 };
475 572  
  573 +#ifdef CONFIG_MX6SX
476 574 struct fuse_bank4_regs {
  575 + u32 sjc_resp_low;
  576 + u32 rsvd0[3];
  577 + u32 sjc_resp_high;
  578 + u32 rsvd1[3];
  579 + u32 mac_addr_low;
  580 + u32 rsvd2[3];
  581 + u32 mac_addr_high;
  582 + u32 rsvd3[3];
  583 + u32 mac_addr2;
  584 + u32 rsvd4[7];
  585 + u32 gp1;
  586 + u32 rsvd5[7];
  587 +};
  588 +#else
  589 +struct fuse_bank4_regs {
477 590 u32 sjc_resp_low;
478 591 u32 rsvd0[3];
479 592 u32 sjc_resp_high;
... ... @@ -487,6 +600,7 @@
487 600 u32 gp2;
488 601 u32 rsvd5[3];
489 602 };
  603 +#endif
490 604  
491 605 struct aipstz_regs {
492 606 u32 mprot0;
arch/arm/include/asm/arch-mx6/mx6-ddr.h
Diff comments   View file @ 05d54b8
... ... @@ -13,7 +13,11 @@
13 13 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
14 14 #include "mx6dl-ddr.h"
15 15 #else
  16 +#ifdef CONFIG_MX6SX
  17 +#include "mx6sx-ddr.h"
  18 +#else
16 19 #error "Please select cpu"
  20 +#endif /* CONFIG_MX6SX */
17 21 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
18 22 #endif /* CONFIG_MX6Q */
19 23 #else
arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
Diff comments   View file @ 05d54b8
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __ASM_ARCH_MX6SX_DDR_H__
  8 +#define __ASM_ARCH_MX6SX_DDR_H__
  9 +
  10 +#ifndef CONFIG_MX6SX
  11 +#error "wrong CPU"
  12 +#endif
  13 +
  14 +#define MX6_IOM_DRAM_DQM0 0x020e02ec
  15 +#define MX6_IOM_DRAM_DQM1 0x020e02f0
  16 +#define MX6_IOM_DRAM_DQM2 0x020e02f4
  17 +#define MX6_IOM_DRAM_DQM3 0x020e02f8
  18 +
  19 +#define MX6_IOM_DRAM_RAS 0x020e02fc
  20 +#define MX6_IOM_DRAM_CAS 0x020e0300
  21 +#define MX6_IOM_DRAM_SDODT0 0x020e0310
  22 +#define MX6_IOM_DRAM_SDODT1 0x020e0314
  23 +#define MX6_IOM_DRAM_SDBA2 0x020e0320
  24 +#define MX6_IOM_DRAM_SDCKE0 0x020e0324
  25 +#define MX6_IOM_DRAM_SDCKE1 0x020e0328
  26 +#define MX6_IOM_DRAM_SDCLK_0 0x020e032c
  27 +#define MX6_IOM_DRAM_RESET 0x020e0340
  28 +
  29 +#define MX6_IOM_DRAM_SDQS0 0x020e0330
  30 +#define MX6_IOM_DRAM_SDQS1 0x020e0334
  31 +#define MX6_IOM_DRAM_SDQS2 0x020e0338
  32 +#define MX6_IOM_DRAM_SDQS3 0x020e033c
  33 +
  34 +#define MX6_IOM_GRP_ADDDS 0x020e05f4
  35 +#define MX6_IOM_DDRMODE_CTL 0x020e05f8
  36 +#define MX6_IOM_GRP_DDRPKE 0x020e05fc
  37 +#define MX6_IOM_GRP_DDRMODE 0x020e0608
  38 +#define MX6_IOM_GRP_B0DS 0x020e060c
  39 +#define MX6_IOM_GRP_B1DS 0x020e0610
  40 +#define MX6_IOM_GRP_CTLDS 0x020e0614
  41 +#define MX6_IOM_GRP_DDR_TYPE 0x020e0618
  42 +#define MX6_IOM_GRP_B2DS 0x020e061c
  43 +#define MX6_IOM_GRP_B3DS 0x020e0620
  44 +
  45 +#endif /*__ASM_ARCH_MX6SX_DDR_H__ */