Eric Lee / smarc-uboot

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Commit 05f474c4d0469bebc0bb05df60a39dc7fdf28e62

Authored by Wolfgang Denk
1 parent ad74cae9ff
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Update CHANGELOG 

Signed-off-by: Wolfgang Denk <wd@denx.de>

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  1 +commit ad74cae9ff8790727bc81ee91c6bca7d50dca446
  2 +Author: David Brownell <dbrownell@users.sourceforge.net>
  3 +Date: Thu Apr 16 23:15:15 2009 -0700
  4 +
  5 + dm9000 EEPROM reading bugfix
  6 +
  7 + Make the U-Boot dm9000 driver read addresses from EEPROM just
  8 + like Linux does ... read six bytes, instead of reading twelve
  9 + bytes and then discarding every other one.
  10 +
  11 + Using the right Ethernet address is a big win.
  12 +
  13 + Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
  14 + Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15 + Acked-by: Ben Warren <biggerbadderben@gmail.com>
  16 +
  17 +commit d4c02e6f5d49880123e7f584b88f857ffd874381
  18 +Author: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  19 +Date: Wed Feb 25 14:27:24 2009 +0900
  20 +
  21 + rtl8169: fix cache coherency problem
  22 +
  23 + Fix the problem that cannot access actual data when CPU data cache enabled.
  24 +
  25 + Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  26 + Tested-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  27 + Acked-by: Ben Warren <biggerbadderben@gmail.com>
  28 +
  29 +commit 34b76a14f676bc6501c27a96564e4dfb4793f033
  30 +Author: Wolfgang Denk <wd@denx.de>
  31 +Date: Sun Apr 26 20:39:26 2009 +0200
  32 +
  33 + lib_arm/board.c: remove misleading "test-only" comment.
  34 +
  35 + For a long time, the print_cpuinfo() declaration in lib_arm/board.c
  36 + had been marked as "test-only", which is plain wrong considering
  37 + current usage. Delete this misleading comment.
  38 +
  39 + Signed-off-by: Wolfgang Denk <wd@denx.de>
  40 +
  41 +commit 14b9308d511b53042ef478936e367a67282df66a
  42 +Author: Heiko Schocher <hs@denx.de>
  43 +Date: Fri Apr 24 06:50:45 2009 +0200
  44 +
  45 + 83xx: searching "muram-data" by compatible property
  46 +
  47 + if using CONFIG_BOOTCOUNT_LIMIT feature on a MPC8360 CPU
  48 + in the muram-data node, the reg entry needs to be updated.
  49 + This is done in fdt_fixup_muram(), but we should use
  50 + the compatible "fsl,qe-muram-data" for searching the
  51 + node instead of searching the muram-data node with
  52 + an absolute path.
  53 +
  54 + Signed-off-by: Heiko Schocher <hs@denx.de>
  55 + Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
  56 +
  57 +commit 8e15088794807944b221c11609d36789efc7f767
  58 +Author: Anatolij Gustschin <agust@denx.de>
  59 +Date: Thu Apr 23 21:29:34 2009 +0200
  60 +
  61 + mpc83xx: MPC8360ERDK: fix environment offset configuration bug
  62 +
  63 + The size of U-Boot binary for MPC8360ERDK increased
  64 + (> 2 flash sectors now), so 'saveenv' will partially
  65 + overwrite U-Boot in flash and will brick the board.
  66 + This patch moves environment offset to fourth flash
  67 + sector and also fixes CONFIG_SYS_MONITOR_LEN.
  68 +
  69 + Signed-off-by: Anatolij Gustschin <agust@denx.de>
  70 + Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
  71 +
  72 +commit 3c172c4fdbbb5858fae38478d6399be4a16be3fc
  73 +Author: Michael Zaidman <michael.zaidman@gmail.com>
  74 +Date: Sat Apr 4 01:43:00 2009 +0300
  75 +
  76 + NetLoop initialization bug
  77 +
  78 + The patch fixes the bug of partial initialization of global network
  79 + parameters.
  80 +
  81 + Upon u-boot's start up the first ping command causes a failure of the
  82 + consequent TFTP command. It happens in the recently added mechanism of
  83 + the NetLoop initialization where initialization of global network
  84 + parameters is separated in the NetInitLoop routine which is called per
  85 + env_id change. Thus, ping request will initialize the network parameters
  86 + necessary for ping operation only, afterwards the env_changed_id will be
  87 + set to the env_id that will prevent all following initialization requests
  88 + from other protocols.
  89 + The problem is that the initialized by ping subset of network parameters
  90 + is not sufficient for other protocols and particularly for TFTP which
  91 + requires the NetServerIp also.
  92 +
  93 + Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
  94 + Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
  95 +
  96 +commit b11f664f52c2855990107c18f242223377183575
  97 +Author: Timur Tabi <timur@freescale.com>
  98 +Date: Thu Apr 9 10:27:05 2009 -0500
  99 +
  100 + net: fix ULI 526x macro usage in netdev.h
  101 +
  102 + Change netdev.h to use CONFIG_ULI526X instead of CONFIG_ULI526. CONFIG_ULI526X
  103 + is used everywhere else, so that's the correct macro name. Without this fix,
  104 + Ethernet will not work on the Freescale MPC8610 HPCD.
  105 +
  106 + Signed-off-by: Timur Tabi <timur@freescale.com>
  107 + Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
  108 +
  109 +commit 7ee38c044ca5041d3378d6507580ea4ec344af96
  110 +Author: David Brownell <dbrownell@users.sourceforge.net>
  111 +Date: Sun Apr 12 15:38:06 2009 -0700
  112 +
  113 + fix DaVinci NS16550_REG_SIZE regression
  114 +
  115 + Update the DaVinci DM6446 boards to use the new convention
  116 + for CONFIG_SYS_NS16550_REG_SIZE ... the size hasn't changed
  117 + from the original 4 bytes, but these chips are little-endian.
  118 +
  119 + (Resolves a regression added recently by the include/ns16550.h
  120 + patch to "Unify structure declaration for registers". The code
  121 + previously worked just fine because the registers were accessed
  122 + as host-endian words, not as bytes.)
  123 +
  124 + Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
  125 +
  126 +commit dfc99e143fca44a492918ac6cf3f76ee9c2473a9
  127 +Author: Mike Frysinger <vapier@gentoo.org>
  128 +Date: Sun Apr 12 22:29:20 2009 -0400
  129 +
  130 + cmd_nand: drop duplicate NULL ptr check
  131 +
  132 + The first if statement checks for NULL ptrs, so there is no need to check
  133 + it again in later else cases (such as .oob).
  134 +
  135 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  136 + CC: Scott Wood <scottwood@freescale.com>
  137 +
  138 +commit 7732cef2eeb4e339cfcd8553fab773af73a20805
  139 +Author: David Brownell <dbrownell@users.sourceforge.net>
  140 +Date: Mon Apr 13 08:03:38 2009 -0700
  141 +
  142 + CMD_UBI != MTD_PARTITIONS
  143 +
  144 + Fix dependency goofage: it should certainly be possible to have the
  145 + partition support without bringing in UBI commands.
  146 +
  147 + Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
  148 + Acked-by: Stefan Roese <sr@denx.de>
  149 +
  150 +commit 6ebff365eb63093ca35b687316002535c6a18820
  151 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  152 +Date: Thu Apr 16 21:30:48 2009 +0200
  153 +
  154 + at91sam9/at91cap: fix CONFIG_SYS_HZ to 1000
  155 +
  156 + The timer has been rewrote with a precision at ~0,18%
  157 +
  158 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  159 + Tested-by: Sergey Lapin <slapin@ossfans.org>
  160 + Tested-by: Eric BENARD <ebenard@free.fr>
  161 +
  162 +commit f0a2c7b4b64eacd06bb272856bcc056be8719f5a
  163 +Author: Ilko Iliev <iliev@ronetix.at>
  164 +Date: Thu Apr 16 21:30:48 2009 +0200
  165 +
  166 + at91: add support for the PM9263 board of Ronetix GmbH
  167 +
  168 + The PM9263 board is based on the AT91SAM9263-EK board.
  169 +
  170 + Here is the page on Ronetix website:
  171 + http://www.ronetix.at/starter_kit_9263.html
  172 +
  173 + Signed-off-by: Ilko Iliev <iliev@ronetix.at>
  174 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  175 +
  176 +commit dc39ae9513c32dfeb9e018dc0d22c6484514fefb
  177 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  178 +Date: Thu Apr 16 21:30:44 2009 +0200
  179 +
  180 + at91sam9/at91cap: improve clock framework
  181 +
  182 + calculate dynamically the clock rate and pllb setting for usb
  183 +
  184 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  185 +
  186 +commit dd7c302099ef5590069bdbf292aaa8230cd59de7
  187 +Author: Stefan Roese <sr@denx.de>
  188 +Date: Wed Apr 15 14:08:48 2009 +0200
  189 +
  190 + ppc4xx: Disable POST memory test on NAND-booting Kilauea
  191 +
  192 + Don't run the memory POST on the NAND-booting version. It will
  193 + overwrite part of the U-Boot image which is already loaded from NAND
  194 + to SDRAM. We were just lucky that it booted at all with this SDRAM
  195 + test enabled.
  196 +
  197 + Signed-off-by: Stefan Roese <sr@denx.de>
  198 +
  199 +commit 9a929170be89b27bce677504da27e88600c06c49
  200 +Author: Stefan Roese <sr@denx.de>
  201 +Date: Wed Apr 15 14:06:26 2009 +0200
  202 +
  203 + ppc4xx: Disable POST memory test on NAND-booting Sequoia
  204 +
  205 + Don't run the memory POST on the NAND-booting version. It will
  206 + overwrite part of the U-Boot image which is already loaded from NAND
  207 + to SDRAM. We were just lucky that it booted at all with this SDRAM
  208 + test enabled.
  209 +
  210 + Signed-off-by: Stefan Roese <sr@denx.de>
  211 +
  212 +commit 17c1b0e89b8be7d90f605eb19af9218c6275bfb3
  213 +Author: Stefan Roese <sr@denx.de>
  214 +Date: Wed Apr 15 11:32:53 2009 +0200
  215 +
  216 + ppc4xx: Remove unused code for Sequoia NAND booting version
  217 +
  218 + The current define of get_bus_freq() in the CONFIG_NAND_SPL #ifdef is not
  219 + used at all. This patch changes it's define to the currently used value of
  220 + 133333333 and removes the unnecessary code.
  221 +
  222 + Signed-off-by: Stefan Roese <sr@denx.de>
  223 +
  224 +commit cf9409885cbe01405bad76790e99f8adf3351f4d
  225 +Author: Stefan Roese <sr@denx.de>
  226 +Date: Wed Apr 15 10:50:48 2009 +0200
  227 +
  228 + ppc4xx: Add "booting from NAND" to 4xx NAND-booting targets
  229 +
  230 + This additional text in the bootup log helps to see if the board is
  231 + configured for NAND-booting. Especially helpful for boards that can
  232 + boot from NOR and NAND (e.g. most of the AMCC eval boards).
  233 +
  234 + Signed-off-by: Stefan Roese <sr@denx.de>
  235 +
  236 +commit 5132106a27b8fb302677852b26ffd319b40d17e2
  237 +Author: Stefan Roese <sr@denx.de>
  238 +Date: Wed Apr 8 10:36:22 2009 +0200
  239 +
  240 + ppc4xx: Fixup chip-selects in dtb for NAND-booting Sequoia
  241 +
  242 + Currently the NOR & NAND support in Linux only works for the "standard"
  243 + Sequoia, the version booting for NOR flash. The NAND-booting version
  244 + has the chip-selects swapped. Here the chip-select mappings:
  245 +
  246 + "Standard" NOR-booting version:
  247 + CS0 NOR
  248 + CS3 NAND
  249 +
  250 + NAND-booting version:
  251 + CS0 NAND
  252 + CS3 NOR
  253 +
  254 + With this path the dtb gets fixed-up, so that the correct chip-select
  255 + numbers are patched in the dtb enabling correct NOR & NAND support
  256 + in Linux on the NAND-booting Sequoia version.
  257 +
  258 + Signed-off-by: Stefan Roese <sr@denx.de>
  259 +
  260 +commit aad4eca4ba8d597747199d8af723426681557dda
  261 +Author: Mike Frysinger <vapier@gentoo.org>
  262 +Date: Sat Apr 4 09:10:27 2009 -0400
  263 +
  264 + Blackfin: audit UART for all known anomalies
  265 +
  266 + There is no code change here, just new comments, but this keeps me from
  267 + having to do another audit from scratch in the future.
  268 +
  269 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  270 +
  271 +commit 8ef929afa43c77c9573caa57c6e17a97a33775c0
  272 +Author: Mike Frysinger <vapier@gentoo.org>
  273 +Date: Sat Apr 4 08:40:13 2009 -0400
  274 +
  275 + Blackfin: add check for anomaly 05000362
  276 +
  277 + DESCRIPTION:
  278 + The column address width settings for banks 2 and 3 are misconnected in
  279 + the SDRAM controller. Accesses to bank 2 will result in an error if the
  280 + Column Address Width for bank 3 (EB3CAW ) is not set to be the same as
  281 + that of bank 2.
  282 +
  283 + WORKAROUND:
  284 + If using bank 2, make sure that banks 2 and 3 have the same column address
  285 + width settings in the EBIU_SDBCTL register. This must be the case
  286 + regardless of whether or not bank 3 is enabled.
  287 +
  288 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  289 +
  290 +commit c2e07449f546fb375289cdac1a608fdc20357873
  291 +Author: Mike Frysinger <vapier@gentoo.org>
  292 +Date: Sat Apr 4 08:29:55 2009 -0400
  293 +
  294 + Blackfin: add comment about anomaly 05000430 avoidance
  295 +
  296 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  297 +
  298 +commit 48ab1509254a4c175e4f65c478a978928ffe09ec
  299 +Author: Mike Frysinger <vapier@gentoo.org>
  300 +Date: Sat Apr 4 08:10:22 2009 -0400
  301 +
  302 + Blackfin: add workaround for anomaly 05000242
  303 +
  304 + DESCRIPTION:
  305 + If the DF bit is set prior to a hardware reset, the PLL will continue to
  306 + divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
  307 + cleared in the PLL_CTL register.
  308 +
  309 + WORKAROUND:
  310 + Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
  311 + 2 after reset.
  312 +
  313 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  314 +
  315 +commit ce1fe4ba6bb9df7c57351436fa17d1af8bbe7916
  316 +Author: Mike Frysinger <vapier@gentoo.org>
  317 +Date: Sat Apr 4 08:09:24 2009 -0400
  318 +
  319 + Blackfin: add workaround for anomaly 05000171
  320 +
  321 + DESCRIPTION:
  322 + The Boot ROM is executed at power up/reset and changes the value of the
  323 + SICA_IWR registers from their default reset value of 0xFFFF, but does not
  324 + restore them.
  325 +
  326 + WORKAROUND:
  327 + User code should not rely on the default value of these registers. Set
  328 + the desired values explicitly.
  329 +
  330 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  331 +
  332 +commit 51ee6e057f7a920e2a125cd9f985d10f625e355f
  333 +Author: Mike Frysinger <vapier@gentoo.org>
  334 +Date: Sat Apr 4 08:22:36 2009 -0400
  335 +
  336 + Blackfin: update anomaly sheets
  337 +
  338 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  339 +
  340 +commit a343ba87ea0320ca0a4ecfa2c42cd9d4f18883df
  341 +Author: Graf Yang <graf.yang@analog.com>
  342 +Date: Sat Apr 4 07:45:57 2009 -0400
  343 +
  344 + Blackfin: nand: flush peripheral before polling it
  345 +
  346 + We need to make sure the data written to the nand flash controller makes
  347 + it there before we start polling its status register. Otherwise, we may
  348 + get stale data and return before the controller is actually ready.
  349 +
  350 + Signed-off-by: Graf Yang <graf.yang@analog.com>
  351 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  352 + Acked-by: Scott Wood <scottwood@freescale.com>
  353 +
  354 +commit 3ccbfb25f48af78e7092ac75f3115e924e76c748
  355 +Author: Remy Bohmer <linux@bohmer.net>
  356 +Date: Sun Apr 5 11:43:28 2009 +0200
  357 +
  358 + Support for PXA27X UDC.
  359 +
  360 + This Patch adds Support for PXA27X UDC.
  361 + (Rebased to drivers/usb reorganisation)
  362 +
  363 + Signed-off-by: Vivek Kutal <vivek.kutal@azingo.com>
  364 + Signed-off-by: Remy Bohmer <linux@bohmer.net>
  365 +
  366 +commit 2731b9a86685190d26b1883f27afda5ac8e1a313
  367 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  368 +Date: Fri Apr 3 12:46:58 2009 +0200
  369 +
  370 + drivers/usb: regorganisation
  371 +
  372 + move to linux usb driver organisation
  373 +
  374 + as following
  375 +
  376 + drivers/usb/gadget
  377 + drivers/usb/host
  378 + drivers/usb/musb
  379 +
  380 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  381 + Signed-off-by: Remy Bohmer <linux@bohmer.net>
  382 +
  383 +commit d04371a116d102e587ba7aa4c329b441cdbea3f4
  384 +Author: Todor I Mollov <tmollov@ucsd.edu>
  385 +Date: Sat Apr 4 06:53:06 2009 -0400
  386 +
  387 + Blackfin: spi: make cs deassert function deterministic
  388 +
  389 + Blackfin SPI driver was not driving the SPI chip-select high before
  390 + putting the chip-select signals into tri-state mode. This is probably
  391 + something that slipped by unnoticed in most designs. If the signals are
  392 + put directly into a tri-state mode, then the board is relying on the
  393 + pull-up resistors to pull up the chip-select before the next transaction.
  394 + Most of the time this is fine, except when you have two transactions that
  395 + follow each other very closely, such as the flash erase and read status
  396 + register commands. In this case I was seeing a 500ns separation between
  397 + the transactions. In my setup, with a 10kOhm pull-up, it would meet
  398 + timing spec about half the time and resulted in intermittent errors. (A
  399 + stronger pull up would fix this, but our design is targeted for low power
  400 + consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
  401 + I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
  402 + chip-selects high before putting them into tri-state. For me, this
  403 + resulted in a rise time of 5ns instead of the previous rise time of about
  404 + 1us, and fully satisfied the timing spec of the chip.
  405 +
  406 + Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
  407 + Signed-off-by: Mike Frysinger <vapier@gentoo.org>
  408 +
  409 +commit c6fadb9c73a6a3e0c7f20696e978304a593a8d2d
  410 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  411 +Date: Sat Dec 13 21:08:05 2008 +0100
  412 +
  413 + integratorap: fix PCI support
  414 +
  415 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  416 +
  417 +commit 1c397508c836dfcb01fb2471c71de0727051f117
  418 +Author: Dirk Behme <dirk.behme@googlemail.com>
  419 +Date: Mon Mar 30 21:15:23 2009 +0200
  420 +
  421 + OMAP3: Update Overo pin mux for new expansion board
  422 +
  423 + A new Overo expansion board uses GPIO 14, 21, 22 and 23 for LED's and
  424 + switches. This patch changes the pinmux configuration for those pins.
  425 + They were previously set up for unused MMC3_DAT4-7.
  426 +
  427 + Signed-off-by: Steve Sakoman <steve@sakoman.com>
  428 + Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
  429 +
  430 +commit ab298231518675b3784aea88ee9b978438f99e63
  431 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  432 +Date: Sun Apr 5 13:08:03 2009 +0200
  433 +
  434 + arm: unify reset command
  435 +
  436 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  437 +
  438 +commit b3acb6cd4059dfb29a5e99095d802717f53ff784
  439 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  440 +Date: Sun Apr 5 13:06:31 2009 +0200
  441 +
  442 + arm: clean cache management
  443 +
  444 + unify arm cache management except for non standard cache as ARM7TDMI
  445 +
  446 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  447 +
  448 +commit 677e62f43235de9a1701204d7bcea0fb3d233fa1
  449 +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  450 +Date: Sun Apr 5 13:02:43 2009 +0200
  451 +
  452 + arm: update co-processor 15 access
  453 +
  454 + import system.h from linux
  455 +
  456 + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  457 +
  458 +commit 23e4af49e066a53cd3e3659b68ef90572d88de84
  459 +Author: Guennadi Liakhovetski <lg@denx.de>
  460 +Date: Sun Apr 5 00:42:02 2009 +0200
  461 +
  462 + ARM: add the imx31_phycore_eet target to MAINTAINERS
  463 +
  464 + imx31_phycore_eet is a variant of the imx31_phycore board with a few
  465 + extensions, which justifies a separate entry in the MAINTAINERS list,
  466 + whereas normally all entries sharing a single configuration file and a
  467 + board/ directory have only one entry in MAINTAINERS.
  468 +
  469 + Reported-by: Wolfgang Denk <wd@denx.de>
  470 + Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
  471 +
  472 +commit 69c5bf29908b3a7f8e23bd9891b7ecc5b21f23e5
  473 +Author: Guennadi Liakhovetski <lg@denx.de>
  474 +Date: Sun Apr 5 00:37:07 2009 +0200
  475 +
  476 + ARM: fix out-of-tree build of imx31_phycore_eet
  477 +
  478 + Fix out-of-tree build of the imx31_phycore_eet target.
  479 +
  480 + Reported-by: Wolfgang Denk <wd@denx.de>
  481 + Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
  482 +
  483 +commit 3c853f31d6a8e4407f73a2ca2c63d383a245f237
  484 +Author: Jon Smirl <jonsmirl@gmail.com>
  485 +Date: Sat Apr 4 17:44:51 2009 -0400
  486 +
  487 + mpc5200: reduce delays in i2c
  488 +
  489 + The previous code waited 1000us before checking i2c
  490 + status. Measurement shows i2c is usually ready in
  491 + under 50us. Change the polling interval to 15us,
  492 + loop 6,667 times to keep the polling timeout constant
  493 + at 100ms.
  494 +
  495 +commit 36003268968949110ef145d9f2eaf8439c96d25b
  496 +Author: Sanjeev Premi <premi@ti.com>
  497 +Date: Fri Apr 3 14:00:07 2009 +0530
  498 +
  499 + OMAP: Fix compile issue
  500 +
  501 + Fixes this compile error:
  502 + board.c: In function 'do_switch_ecc':
  503 + board.c:339: error: 'cmd_tbl_t' has no member named 'help'
  504 + make[1]: *** [board.o] Error 1
  505 + make[1]: Leaving directory `/db/psp_git/users/a0756819/u-boot/cpu/arm_cortexa8/omap3'
  506 + make: *** [cpu/arm_cortexa8/omap3/libomap3.a] Error 2
  507 +
  508 + This is due to the fact that current command uses long
  509 + help for the usage print even if the CONFIG_SYS_LONGHELP
  510 + is not enabled. (Thanks Jean-Christophe for explanation).
  511 +
  512 + Signed-off-by: Sanjeev Premi <premi@ti.com>
  513 +
  514 +commit 342c1a5d9ab74febf3226a86216dc5aa05295d46
  515 +Author: Minkyu Kang <mk7.kang@samsung.com>
  516 +Date: Fri Apr 3 09:56:16 2009 +0900
  517 +
  518 + s3c64xx: fix the wrong gpio offset
  519 +
  520 + This patch fix the wrong gpio offset
  521 +
  522 + Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
  523 +
  524 +commit ab0689c316c9b2ee33f4de1c50263b64e539f12a
  525 +Author: Kyungmin Park <kmpark@infradead.org>
  526 +Date: Wed Nov 26 10:18:13 2008 +0900
  527 +
  528 + Move machine specific code to board at s3c64xx (v2)
  529 +
  530 + Move machine specific code to smdk6400.
  531 + Some board use OneNAND instead of NAND.
  532 +
  533 + Some register MP0_CS_CFG[5:0] are controled by both h/w and s/w.
  534 + So it's better to use macro instead of hard-coded value.
  535 +
  536 + Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
  537 +
  538 +commit 767f3acd9f6e1dcb8ada926c333945382eddc7e8
  539 +Author: Tom Rix <Tom.Rix@windriver.com>
  540 +Date: Wed Apr 1 22:02:19 2009 -0500
  541 +
  542 + ZOOM1 Remove legacy NAND defines
  543 +
  544 + Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
  545 +
  546 +commit 5891151707ee5902fe62d554c247f42865815757
  547 +Author: Tom Rix <Tom.Rix@windriver.com>
  548 +Date: Wed Apr 1 22:02:20 2009 -0500
  549 +
  550 + OMAP3 Fix multiline formatting in board init files.
  551 +
  552 + Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
  553 +
  554 +commit c0a14aedc3440d6591b8c86d45861a0a8b46e11d
  555 +Author: Wolfgang Denk <wd@denx.de>
  556 +Date: Sun Apr 5 00:27:57 2009 +0200
  557 +
  558 + Update CHANGELOG, coding style cleanup.
  559 +
1 560 commit f63728c804ab7413a67d70f6774cd30c3f7b40fb
2 561 Author: Wolfgang Denk <wd@denx.de>
3 562 Date: Sun Apr 5 00:18:44 2009 +0200