ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE

The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>

ARM: bcm283x: Define CONFIG_SYS_CACHELINE_SIZE
The cacheline is always 32 bytes for arm1176 CPUs, so define it at board config level for cache handling code. The ARM Cortex-A7 has a dcache line size of 64 bytes. Signed-off-by: Alexander Stein <alexanders83@web.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Alexander Stein · Tom Rini
1 parent 2085ae74de
Showing 2 changed files with 3 additions and 0 deletions Side-by-side Diff
include/configs/rpi.h
include/configs/rpi_2.h
@@ -7,6 +7,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
  
+#define CONFIG_SYS_CACHELINE_SIZE		32
+
 #include "rpi-common.h"
  
 #endif
@@ -9,6 +9,7 @@
  
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BCM2836
+#define CONFIG_SYS_CACHELINE_SIZE		64
  
 #include "rpi-common.h"
...	...	@@ -7,6 +7,8 @@
7	7	#ifndef __CONFIG_H
8	8	#define __CONFIG_H
9	9
	10	+#define CONFIG_SYS_CACHELINE_SIZE 32
	11	+
10	12	#include "rpi-common.h"
11	13
12	14	#endif
...	...	@@ -9,6 +9,7 @@
9	9
10	10	#define CONFIG_SKIP_LOWLEVEL_INIT
11	11	#define CONFIG_BCM2836
	12	+#define CONFIG_SYS_CACHELINE_SIZE 64
12	13
13	14	#include "rpi-common.h"
14	15