DMC: Exynos5: Enable update mode for DREX controller

As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

DMC: Exynos5: Enable update mode for DREX controller
As per Exynos5800 UM ver 0.00 section 17.13.2.1 CONCONTROL register bit 3 [update_mode], Exynos5800 does not support the PHY initiated update. And it is recommanded to set this field to 1'b1 during initialization. This patch sets this bit. Applying MC-initiated mode makes DDL tracking ON, that helps in compensate MIF voltage variation. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Alim Akhtar · Minkyu Kang
1 parent 79043d84da
Showing 2 changed files with 20 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
arch/arm/include/asm/arch-exynos/dmc.h
@@ -832,6 +832,25 @@
 	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
 	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
  
+	/*
+	 * As per Exynos5800 UM ver 0.00 section 17.13.2.1
+	 * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
+	 * support the PHY initiated update. And it is recommended to set
+	 * this field to 1'b1 during initialization
+	 *
+	 * When we apply PHY-initiated mode, DLL lock value is determined
+	 * once at DMC init time and not updated later when we change the MIF
+	 * voltage based on ASV group in kernel. Applying MC-initiated mode
+	 * makes sure that DLL tracing is ON so that silicon is able to
+	 * compensate the voltage variation.
+	 */
+	val = readl(&drex0->concontrol);
+	val |= CONCONTROL_UPDATE_MODE;
+	writel(val , &drex0->concontrol);
+	val = readl(&drex1->concontrol);
+	val |= CONCONTROL_UPDATE_MODE;
+	writel(val , &drex1->concontrol);
+
 	return 0;
 }
 #endif
@@ -450,6 +450,7 @@
 #define CONCONTROL_RD_FETCH_SHIFT	12
 #define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
 #define CONCONTROL_AREF_EN_SHIFT	5
+#define CONCONTROL_UPDATE_MODE		(1 << 3)
  
 /* PRECHCONFIG register field */
 #define PRECHCONFIG_TP_CNT_SHIFT	24
...	...	@@ -832,6 +832,25 @@
832	832	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
833	833	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
834	834
	835	+ /*
	836	+ * As per Exynos5800 UM ver 0.00 section 17.13.2.1
	837	+ * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
	838	+ * support the PHY initiated update. And it is recommended to set
	839	+ * this field to 1'b1 during initialization
	840	+ *
	841	+ * When we apply PHY-initiated mode, DLL lock value is determined
	842	+ * once at DMC init time and not updated later when we change the MIF
	843	+ * voltage based on ASV group in kernel. Applying MC-initiated mode
	844	+ * makes sure that DLL tracing is ON so that silicon is able to
	845	+ * compensate the voltage variation.
	846	+ */
	847	+ val = readl(&drex0->concontrol);
	848	+ val \|= CONCONTROL_UPDATE_MODE;
	849	+ writel(val , &drex0->concontrol);
	850	+ val = readl(&drex1->concontrol);
	851	+ val \|= CONCONTROL_UPDATE_MODE;
	852	+ writel(val , &drex1->concontrol);
	853	+
835	854	return 0;
836	855	}
837	856	#endif
...	...	@@ -450,6 +450,7 @@
450	450	#define CONCONTROL_RD_FETCH_SHIFT 12
451	451	#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
452	452	#define CONCONTROL_AREF_EN_SHIFT 5
	453	+#define CONCONTROL_UPDATE_MODE (1 << 3)
453	454
454	455	/* PRECHCONFIG register field */
455	456	#define PRECHCONFIG_TP_CNT_SHIFT 24