Commit 0652f201a950e0f14d8f7def65323934a4bdaad4

Authored by faqiang.zhu
Committed by Ji Luo
1 parent c57f6effca

MA-15062 change MACRO name of mcu TCM base address

imx-regs-imx8mm.h is used both for imx8mm and imx8mn, while mcu in
imx8mn is Cortex-M7, it's different from Cortex-M4 in imx8mm, change
the MACRO name of mcu TCM base address from M4_BOOTROM_BASE_ADDR to
MCU_BOOTROM_BASE_ADDR.
since this MACRO will be used in common code for i.MX chips, the same
MACRO name in other files are also modified.

Change-Id: I433dd78d11c485d0f4cb82bab299f61cb29dce45
Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
(cherry picked from commit e2eb616fdbc4ce6475b084ab11b77cd5dcaa6fd2)

Showing 4 changed files with 4 additions and 4 deletions Side-by-side Diff

arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h
... ... @@ -14,7 +14,7 @@
14 14  
15 15 #define ROM_VERSION_A0 0x800
16 16 #define ROM_VERSION_B0 0x800
17   -#define M4_BOOTROM_BASE_ADDR 0x007E0000
  17 +#define MCU_BOOTROM_BASE_ADDR 0x007E0000
18 18  
19 19 #define AIPS1_BASE_ADDR 0x301F0000
20 20 #define GPIO1_BASE_ADDR 0x30200000
arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h
... ... @@ -11,7 +11,7 @@
11 11 #define ROM_VERSION_A0 0x800
12 12 #define ROM_VERSION_B0 0x83C
13 13  
14   -#define M4_BOOTROM_BASE_ADDR 0x007E0000
  14 +#define MCU_BOOTROM_BASE_ADDR 0x007E0000
15 15  
16 16 #define SAI1_BASE_ADDR 0x30010000
17 17 #define SAI6_BASE_ADDR 0x30030000
arch/arm/include/asm/arch-mx6/imx-regs.h
... ... @@ -23,7 +23,7 @@
23 23 #define GPU_ARB_END_ADDR 0x01803FFF
24 24 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
25 25 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
26   -#define M4_BOOTROM_BASE_ADDR 0x007F8000
  26 +#define MCU_BOOTROM_BASE_ADDR 0x007F8000
27 27  
28 28 #elif !defined(CONFIG_MX6SLL)
29 29 #define CAAM_ARB_BASE_ADDR 0x00100000
arch/arm/include/asm/arch-mx7/imx-regs.h
... ... @@ -18,7 +18,7 @@
18 18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21   -#define M4_BOOTROM_BASE_ADDR 0x00180000
  21 +#define MCU_BOOTROM_BASE_ADDR 0x00180000
22 22  
23 23 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
24 24 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)