Commit 06b174124e3668be9a01c943b5e0c04c9e9fd1c4
Committed by
Stefan Roese
1 parent
9a420986cc
Exists in
master
and in
54 other branches
ppc4xx: Setup HICB on Io64
The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
Showing 2 changed files with 20 additions and 1 deletions Side-by-side Diff
board/gdsys/405ex/io64.c
... | ... | @@ -249,6 +249,7 @@ |
249 | 249 | char str_serdes[] = "Start SERDES blocks"; |
250 | 250 | char str_channels[] = "Start FPGA channels"; |
251 | 251 | char str_locks[] = "Verify SERDES locks"; |
252 | + char str_hicb[] = "Verify HICB status"; | |
252 | 253 | char str_status[] = "Verify PHY status -"; |
253 | 254 | char slash[] = "\\|/-\\|/-"; |
254 | 255 | |
... | ... | @@ -311,6 +312,21 @@ |
311 | 312 | } |
312 | 313 | } |
313 | 314 | blank_string(strlen(str_locks)); |
315 | + | |
316 | + /* verify hicb_status */ | |
317 | + puts(str_hicb); | |
318 | + for (fpga = 0; fpga < 2; ++fpga) { | |
319 | + u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int; | |
320 | + for (k = 0; k < 32; ++k) { | |
321 | + u16 status = in_le16(ch0_hicb_status_int + 4*k); | |
322 | + if (status) | |
323 | + printf("fpga %d hicb %d: hicb status %04x\n", | |
324 | + fpga, k, status); | |
325 | + /* reset events */ | |
326 | + out_le16(ch0_hicb_status_int + 4*k, status); | |
327 | + } | |
328 | + } | |
329 | + blank_string(strlen(str_hicb)); | |
314 | 330 | |
315 | 331 | /* verify phy status */ |
316 | 332 | puts(str_status); |
include/gdsys_fpga.h
... | ... | @@ -82,7 +82,10 @@ |
82 | 82 | u16 reserved_1[502]; /* 0x0014 */ |
83 | 83 | u16 ch0_status_int; /* 0x0400 */ |
84 | 84 | u16 ch0_config_int; /* 0x0402 */ |
85 | - u16 reserved_2[7677]; /* 0x0404 */ | |
85 | + u16 reserved_2[126]; /* 0x0404 */ | |
86 | + u16 ch0_hicb_status_int;/* 0x0500 */ | |
87 | + u16 ch0_hicb_config_int;/* 0x0502 */ | |
88 | + u16 reserved_3[7549]; /* 0x0504 */ | |
86 | 89 | u16 reflection_high; /* 0x3ffe */ |
87 | 90 | } ihs_fpga_t; |
88 | 91 | #endif |