usb: ci_udc: lift ilist size calculations to global scope

This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: Stephen Warren <swarren@nvidia.com>

usb: ci_udc: lift ilist size calculations to global scope
This will allow functions other than ci_udc_probe() to make use of the constants in a future change. This in turn requires converting the const int variables to #defines, since the initialization of one global const int can't depend on the value of another const int; the compiler thinks it's non-constant if that dependency exists. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren · Marek Vasut
1 parent 8d7c39d3e8
Showing 1 changed file with 14 additions and 14 deletions Side-by-side Diff
drivers/usb/gadget/ci_udc.c
@@ -34,6 +34,17 @@
 #error This driver can not work on systems with caches longer than 128b
 #endif
  
+/*
+ * Each qTD item must be 32-byte aligned, each qTD touple must be
+ * cacheline aligned. There are two qTD items for each endpoint and
+ * only one of them is used for the endpoint at time, so we can group
+ * them together.
+ */
+#define ILIST_ALIGN		roundup(ARCH_DMA_MINALIGN, 32)
+#define ILIST_ENT_RAW_SZ	(2 * sizeof(struct ept_queue_item))
+#define ILIST_ENT_SZ		roundup(ILIST_ENT_RAW_SZ, ARCH_DMA_MINALIGN)
+#define ILIST_SZ		(NUM_ENDPOINTS * ILIST_ENT_SZ)
+
 #ifndef DEBUG
 #define DBG(x...) do {} while (0)
 #else
  
  
@@ -786,29 +797,18 @@
 	const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
 	const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
  
-	const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
-	const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
-	const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
-	const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
-
 	/* The QH list must be aligned to 4096 bytes. */
 	controller.epts = memalign(eplist_align, eplist_sz);
 	if (!controller.epts)
 		return -ENOMEM;
 	memset(controller.epts, 0, eplist_sz);
  
-	/*
-	 * Each qTD item must be 32-byte aligned, each qTD touple must be
-	 * cacheline aligned. There are two qTD items for each endpoint and
-	 * only one of them is used for the endpoint at time, so we can group
-	 * them together.
-	 */
-	controller.items_mem = memalign(ilist_align, ilist_sz);
+	controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
 	if (!controller.items_mem) {
 		free(controller.epts);
 		return -ENOMEM;
 	}
-	memset(controller.items_mem, 0, ilist_sz);
+	memset(controller.items_mem, 0, ILIST_SZ);
  
 	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
 		/*
@@ -828,7 +828,7 @@
 		head->next = TERMINATE;
 		head->info = 0;
  
-		imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
+		imem = controller.items_mem + ((i >> 1) * ILIST_ENT_SZ);
 		if (i & 1)
 			imem += sizeof(struct ept_queue_item);
...	...	@@ -34,6 +34,17 @@
34	34	#error This driver can not work on systems with caches longer than 128b
35	35	#endif
36	36
	37	+/*
	38	+ * Each qTD item must be 32-byte aligned, each qTD touple must be
	39	+ * cacheline aligned. There are two qTD items for each endpoint and
	40	+ * only one of them is used for the endpoint at time, so we can group
	41	+ * them together.
	42	+ */
	43	+#define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32)
	44	+#define ILIST_ENT_RAW_SZ (2 * sizeof(struct ept_queue_item))
	45	+#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ARCH_DMA_MINALIGN)
	46	+#define ILIST_SZ (NUM_ENDPOINTS * ILIST_ENT_SZ)
	47	+
37	48	#ifndef DEBUG
38	49	#define DBG(x...) do {} while (0)
39	50	#else
40	51
41	52
...	...	@@ -786,29 +797,18 @@
786	797	const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
787	798	const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
788	799
789		- const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
790		- const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
791		- const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
792		- const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
793		-
794	800	/* The QH list must be aligned to 4096 bytes. */
795	801	controller.epts = memalign(eplist_align, eplist_sz);
796	802	if (!controller.epts)
797	803	return -ENOMEM;
798	804	memset(controller.epts, 0, eplist_sz);
799	805
800		- /*
801		- * Each qTD item must be 32-byte aligned, each qTD touple must be
802		- * cacheline aligned. There are two qTD items for each endpoint and
803		- * only one of them is used for the endpoint at time, so we can group
804		- * them together.
805		- */
806		- controller.items_mem = memalign(ilist_align, ilist_sz);
	806	+ controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
807	807	if (!controller.items_mem) {
808	808	free(controller.epts);
809	809	return -ENOMEM;
810	810	}
811		- memset(controller.items_mem, 0, ilist_sz);
	811	+ memset(controller.items_mem, 0, ILIST_SZ);
812	812
813	813	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
814	814	/*
...	...	@@ -828,7 +828,7 @@
828	828	head->next = TERMINATE;
829	829	head->info = 0;
830	830
831		- imem = controller.items_mem + ((i >> 1) * ilist_ent_sz);
	831	+ imem = controller.items_mem + ((i >> 1) * ILIST_ENT_SZ);
832	832	if (i & 1)
833	833	imem += sizeof(struct ept_queue_item);
834	834