Commit 06b3acf1848b48f127952f609115a994fefbd520
Committed by
York Sun
York Sun
1 parent
e2544e7a54
Exists in
v2017.01-smarct4x
and in
37 other branches
powerpc/t2080: updating rcw for silicon v1.1
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0, and also update core frequency to 1.8GHz for v1.1. We reserve the support for T2080 v1.0 and enable v1.1 by default. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Showing 2 changed files with 26 additions and 10 deletions Side-by-side Diff
board/freescale/t208xqds/t2080_rcw.cfg
| 1 | 1 | #PBL preamble and RCW header |
| 2 | 2 | aa55aa55 010e0100 |
| 3 | -#SerDes Protocol: 0x66_0x16 | |
| 4 | -#Core/DDR: 1533Mhz/2133MT/s | |
| 5 | -12100017 15000000 00000000 00000000 | |
| 6 | -66150002 00008400 e8104000 c1000000 | |
| 3 | + | |
| 4 | +#For T2080 v1.0 | |
| 5 | +#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s | |
| 6 | +#12100017 15000000 00000000 00000000 | |
| 7 | +#66150002 00008400 e8104000 c1000000 | |
| 8 | +#00000000 00000000 00000000 000307fc | |
| 9 | +#00000000 00000000 00000000 00000004 | |
| 10 | + | |
| 11 | +#For T2080 v1.1 | |
| 12 | +#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s | |
| 13 | +0c070012 0e000000 00000000 00000000 | |
| 14 | +66150002 00000000 e8104000 c1000000 | |
| 7 | 15 | 00000000 00000000 00000000 000307fc |
| 8 | 16 | 00000000 00000000 00000000 00000004 |
board/freescale/t208xrdb/t2080_rcw.cfg
| 1 | -#PBL preamble and RCW header for T2080RDB | |
| 1 | +#PBL preamble and RCW header | |
| 2 | 2 | aa55aa55 010e0100 |
| 3 | -#SerDes Protocol: 0x66_0x16 | |
| 4 | -#Core/DDR: 1533Mhz/1600MT/s | |
| 5 | -120c0017 15000000 00000000 00000000 | |
| 6 | -66150002 00008400 ec104000 c1000000 | |
| 7 | -00000000 00000000 00000000 000307fc | |
| 3 | + | |
| 4 | +#For T2080 v1.0 | |
| 5 | +#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s | |
| 6 | +#120c0017 15000000 00000000 00000000 | |
| 7 | +#66150002 00008400 ec104000 c1000000 | |
| 8 | +#00000000 00000000 00000000 000307fc | |
| 9 | +#00000000 00000000 00000000 00000004 | |
| 10 | + | |
| 11 | +#For T2080 v1.1 | |
| 12 | +#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s | |
| 13 | +1206001b 15000000 00000000 00000000 | |
| 14 | +66150002 00000000 e8104000 c1000000 | |
| 15 | +00800000 00000000 00000000 000307fc | |
| 8 | 16 | 00000000 00000000 00000000 00000004 |