Commit 06d43c808d61580d977526deca328e33382b40c8
Committed by
Tom Rini
1 parent
2b373cb83c
Exists in
v2017.01-smarct4x
and in
25 other branches
arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Showing 2 changed files with 6 additions and 1 deletions Side-by-side Diff
arch/arm/include/asm/system.h
... | ... | @@ -331,7 +331,7 @@ |
331 | 331 | |
332 | 332 | /* options available for data cache on each page */ |
333 | 333 | enum dcache_option { |
334 | - DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0), | |
334 | + DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, | |
335 | 335 | DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), |
336 | 336 | DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), |
337 | 337 | DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), |
arch/arm/lib/cache-cp15.c
... | ... | @@ -71,8 +71,13 @@ |
71 | 71 | |
72 | 72 | end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; |
73 | 73 | start = start >> MMU_SECTION_SHIFT; |
74 | +#ifdef CONFIG_ARMV7_LPAE | |
75 | + debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size, | |
76 | + option); | |
77 | +#else | |
74 | 78 | debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size, |
75 | 79 | option); |
80 | +#endif | |
76 | 81 | for (upto = start; upto < end; upto++) |
77 | 82 | set_section_dcache(upto, option); |
78 | 83 |