Eric Lee / smarc-uboot

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Commit 06e07f65c7bf5449f2417d8ff08de88bf8c4b8a7

Authored by Minghuan Lian
Committed by Tom Rini
1 parent 9561723c76
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers/net/e1000.c: fix compile warning under 64bit mode 

Fix this:
warning: cast from pointer to integer of different size

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>

Showing 1 changed file with 17 additions and 14 deletions Side-by-side Diff

... ... @@ -4927,22 +4927,23 @@
4927 4927 fill_rx(struct e1000_hw *hw)
4928 4928 {
4929 4929 struct e1000_rx_desc *rd;
4930   - uint32_t flush_start, flush_end;
  4930 + unsigned long flush_start, flush_end;
4931 4931  
4932 4932 rx_last = rx_tail;
4933 4933 rd = rx_base + rx_tail;
4934 4934 rx_tail = (rx_tail + 1) % 8;
4935 4935 memset(rd, 0, 16);
4936   - rd->buffer_addr = cpu_to_le64((u32)packet);
  4936 + rd->buffer_addr = cpu_to_le64((unsigned long)packet);
4937 4937  
4938 4938 /*
4939 4939 * Make sure there are no stale data in WB over this area, which
4940 4940 * might get written into the memory while the e1000 also writes
4941 4941 * into the same memory area.
4942 4942 */
4943   - invalidate_dcache_range((u32)packet, (u32)packet + 4096);
  4943 + invalidate_dcache_range((unsigned long)packet,
  4944 + (unsigned long)packet + 4096);
4944 4945 /* Dump the DMA descriptor into RAM. */
4945   - flush_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4946 + flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
4946 4947 flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
4947 4948 flush_dcache_range(flush_start, flush_end);
4948 4949  
... ... @@ -4963,7 +4964,7 @@
4963 4964 unsigned long tipg, tarc;
4964 4965 uint32_t ipgr1, ipgr2;
4965 4966  
4966   - E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
  4967 + E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base);
4967 4968 E1000_WRITE_REG(hw, TDBAH, 0);
4968 4969  
4969 4970 E1000_WRITE_REG(hw, TDLEN, 128);
... ... @@ -5107,7 +5108,7 @@
5107 5108 E1000_WRITE_FLUSH(hw);
5108 5109 }
5109 5110 /* Setup the Base and Length of the Rx Descriptor Ring */
5110   - E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
  5111 + E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base);
5111 5112 E1000_WRITE_REG(hw, RDBAH, 0);
5112 5113  
5113 5114 E1000_WRITE_REG(hw, RDLEN, 128);
5114 5115  
... ... @@ -5138,14 +5139,14 @@
5138 5139 {
5139 5140 struct e1000_hw *hw = nic->priv;
5140 5141 struct e1000_rx_desc *rd;
5141   - uint32_t inval_start, inval_end;
  5142 + unsigned long inval_start, inval_end;
5142 5143 uint32_t len;
5143 5144  
5144 5145 /* return true if there's an ethernet packet ready to read */
5145 5146 rd = rx_base + rx_last;
5146 5147  
5147 5148 /* Re-load the descriptor from RAM. */
5148   - inval_start = ((u32)rd) & ~(ARCH_DMA_MINALIGN - 1);
  5149 + inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
5149 5150 inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
5150 5151 invalidate_dcache_range(inval_start, inval_end);
5151 5152  
... ... @@ -5154,8 +5155,9 @@
5154 5155 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
5155 5156 /* Packet received, make sure the data are re-loaded from RAM. */
5156 5157 len = le32_to_cpu(rd->length);
5157   - invalidate_dcache_range((u32)packet,
5158   - (u32)packet + roundup(len, ARCH_DMA_MINALIGN));
  5158 + invalidate_dcache_range((unsigned long)packet,
  5159 + (unsigned long)packet +
  5160 + roundup(len, ARCH_DMA_MINALIGN));
5159 5161 NetReceive((uchar *)packet, len);
5160 5162 fill_rx(hw);
5161 5163 return 1;
... ... @@ -5170,7 +5172,7 @@
5170 5172 struct e1000_hw *hw = nic->priv;
5171 5173 struct e1000_tx_desc *txp;
5172 5174 int i = 0;
5173   - uint32_t flush_start, flush_end;
  5175 + unsigned long flush_start, flush_end;
5174 5176  
5175 5177 txp = tx_base + tx_tail;
5176 5178 tx_tail = (tx_tail + 1) % 8;
5177 5179  
... ... @@ -5180,10 +5182,11 @@
5180 5182 txp->upper.data = 0;
5181 5183  
5182 5184 /* Dump the packet into RAM so e1000 can pick them. */
5183   - flush_dcache_range((u32)nv_packet,
5184   - (u32)nv_packet + roundup(length, ARCH_DMA_MINALIGN));
  5185 + flush_dcache_range((unsigned long)nv_packet,
  5186 + (unsigned long)nv_packet +
  5187 + roundup(length, ARCH_DMA_MINALIGN));
5185 5188 /* Dump the descriptor into RAM as well. */
5186   - flush_start = ((u32)txp) & ~(ARCH_DMA_MINALIGN - 1);
  5189 + flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
5187 5190 flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
5188 5191 flush_dcache_range(flush_start, flush_end);
5189 5192