Eric Lee / smarc-uboot

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Commit 06fb06f66c57912b53bda9fd1772d5d069433cbd

Authored by Sumit Garg
Committed by York Sun
1 parent a7a81756b8
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

SECURE_BOOT: Unify memory map for Layerscape based platforms 

Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 2 changed files with 28 additions and 38 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 06fb06f
... ... @@ -196,12 +196,12 @@
196 196 config SYS_LS_PPA_ESBC_ADDR
197 197 hex "hdr address of PPA firmware loading from"
198 198 depends on FSL_LS_PPA && CHAIN_OF_TRUST
199   - default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
200   - default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
201   - default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
202   - default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
203   - default 0x700000 if SYS_LS_PPA_FW_IN_MMC
204   - default 0x700000 if SYS_LS_PPA_FW_IN_NAND
  199 + default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
  200 + default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
  201 + default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
  202 + default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
  203 + default 0x680000 if SYS_LS_PPA_FW_IN_MMC
  204 + default 0x680000 if SYS_LS_PPA_FW_IN_NAND
205 205 help
206 206 If the PPA header firmware locate at XIP flash, such as NOR or
207 207 QSPI flash, this address is a directly memory-mapped.
arch/arm/include/asm/fsl_secure_boot.h
Diff comments   View file @ 06fb06f
1 1 /*
2 2 * Copyright 2015 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
5 6 */
6 7  
7 8  
8 9  
9 10  
10 11  
11 12  
12 13  
13 14  
14 15  
15 16  
16 17  
... ... @@ -71,55 +72,44 @@
71 72 * DDR memory map
72 73 */
73 74 #ifdef CONFIG_FSL_LSCH3
74   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x580d00000
75   -#define CONFIG_BS_ADDR_DEVICE 0x580e00000
76   -#define CONFIG_BS_HDR_ADDR_RAM 0xa0d00000
77   -#define CONFIG_BS_ADDR_RAM 0xa0e00000
78   -#define CONFIG_BS_HDR_SIZE 0x00002000
  75 +#define CONFIG_BS_ADDR_DEVICE 0x580600000
  76 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
79 77 #define CONFIG_BS_SIZE 0x00001000
  78 +#define CONFIG_BS_HDR_SIZE 0x00004000
  79 +#define CONFIG_BS_ADDR_RAM 0xa0600000
  80 +#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
80 81 #else
81 82 #ifdef CONFIG_SD_BOOT
82 83 /* For SD boot address and size are assigned in terms of sector
83 84 * offset and no. of sectors respectively.
84 85 */
85   -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
86   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000920
87   -#else
88   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000900
89   -#endif
90   -#define CONFIG_BS_ADDR_DEVICE 0x00000940
91   -#define CONFIG_BS_HDR_SIZE 0x00000010
  86 +#define CONFIG_BS_ADDR_DEVICE 0x00003000
  87 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
92 88 #define CONFIG_BS_SIZE 0x00000008
  89 +#define CONFIG_BS_HDR_SIZE 0x00000010
93 90 #elif defined(CONFIG_NAND_BOOT)
94   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
95   -#define CONFIG_BS_ADDR_DEVICE 0x00802000
96   -#define CONFIG_BS_HDR_SIZE 0x00002000
97   -#define CONFIG_BS_SIZE 0x00001000
98   -#elif defined(CONFIG_QSPI_BOOT)
99   -#ifdef CONFIG_ARCH_LS1046A
100   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x40780000
101   -#define CONFIG_BS_ADDR_DEVICE 0x40800000
102   -#elif defined(CONFIG_ARCH_LS1012A)
103   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x400c0000
104   -#define CONFIG_BS_ADDR_DEVICE 0x40060000
105   -#else
106   -#error "Platform not supported"
107   -#endif
  91 +#define CONFIG_BS_ADDR_DEVICE 0x00600000
  92 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
  93 +#define CONFIG_BS_SIZE 0x00001000
108 94 #define CONFIG_BS_HDR_SIZE 0x00002000
  95 +#elif defined(CONFIG_QSPI_BOOT)
  96 +#define CONFIG_BS_ADDR_DEVICE 0x40600000
  97 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
109 98 #define CONFIG_BS_SIZE 0x00001000
110   -#else /* Default NOR Boot */
111   -#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000
112   -#define CONFIG_BS_ADDR_DEVICE 0x60060000
113 99 #define CONFIG_BS_HDR_SIZE 0x00002000
  100 +#else /* Default NOR Boot */
  101 +#define CONFIG_BS_ADDR_DEVICE 0x60600000
  102 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
114 103 #define CONFIG_BS_SIZE 0x00001000
  104 +#define CONFIG_BS_HDR_SIZE 0x00002000
115 105 #endif
116   -#define CONFIG_BS_HDR_ADDR_RAM 0x81000000
117   -#define CONFIG_BS_ADDR_RAM 0x81020000
  106 +#define CONFIG_BS_ADDR_RAM 0x81000000
  107 +#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
118 108 #endif
119 109  
120 110 #ifdef CONFIG_BOOTSCRIPT_COPY_RAM
121   -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
122 111 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
  112 +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
123 113 #else
124 114 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
125 115 /* BOOTSCRIPT_ADDR is not required */