m68k: add amcore board support

Add Sysam Amcore m68k-based board support. Signed-off-by: Angelo Dureghello <angelo@sysam.it>

m68k: add amcore board support
Add Sysam Amcore m68k-based board support. Signed-off-by: Angelo Dureghello <angelo@sysam.it>
angelo@sysam.it · Tom Rini
1 parent a2bc4321e4
Showing 9 changed files with 376 additions and 0 deletions Side-by-side Diff
arch/m68k/Kconfig
board/sysam/amcore/Kconfig
board/sysam/amcore/MAINTAINERS
board/sysam/amcore/Makefile
board/sysam/amcore/amcore.c
board/sysam/amcore/config.mk
board/sysam/amcore/u-boot.lds
configs/amcore_defconfig
include/configs/amcore.h
@@ -67,6 +67,9 @@
 config TARGET_M5485EVB
 	bool "Support M5485EVB"
  
+config TARGET_AMCORE
+	bool "Support AMCORE"
+
 endchoice
  
 source "board/BuS/eb_cpu5282/Kconfig"
@@ -89,6 +92,7 @@
 source "board/freescale/m54455evb/Kconfig"
 source "board/freescale/m547xevb/Kconfig"
 source "board/freescale/m548xevb/Kconfig"
+source "board/sysam/amcore/Kconfig"
  
 endmenu
+if TARGET_AMCORE
+
+config SYS_CPU
+        string
+        default "mcf530x"
+
+config SYS_BOARD
+        string
+        default "amcore"
+
+config SYS_VENDOR
+        string
+        default "sysam"
+
+config SYS_CONFIG_NAME
+        string
+        default "amcore"
+
+endif
+AMCORE BOARD
+M:	Angelo Dureghello <angelo@sysam.it>
+S:	Maintained
+F:	board/sysam/amcore/
+F:	include/configs/amcore.h
+F:      configs/amcore_defconfig
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	= amcore.o
+/*
+ * Board functions for Sysam AMCORE (MCF5307 based) board
+ *
+ * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ *
+ * This file copies memory testdram() from sandburst/common/sb_common.c
+ */
+
+#include <common.h>
+#include <asm/immap.h>
+#include <asm/io.h>
+
+void init_lcd(void)
+{
+	/* setup for possible K0108 lcd connected on the parallel port */
+	sim_t *sim = (sim_t *)(MMAP_SIM);
+
+	out_be16(&sim->par, 0x300);
+
+	gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+
+	out_be16(&gpio->paddr, 0xfcff);
+	out_be16(&gpio->padat, 0x0c00);
+}
+
+int checkboard(void)
+{
+	puts("Board: ");
+	puts("AMCORE v.001(alpha)\n");
+
+	init_lcd();
+
+	return 0;
+}
+
+/*
+ * in initdram we are here executing from flash
+ * case 1:
+ * is with no ACR/flash cache enabled
+ * nop = 40ns (scope measured)
+ */
+void fudelay(int usec)
+{
+	while (usec--)
+		asm volatile ("nop");
+}
+
+phys_size_t initdram(int board_type)
+{
+	u32 dramsize, RC;
+
+	sdramctrl_t *dc = (sdramctrl_t *)(MMAP_DRAMC);
+
+	/*
+	 * SDRAM  MT48LC4M32B2 details
+	 * Memory block 0: 16 MB of SDRAM at address $00000000
+	 * Port size: 32-bit port
+	 *
+	 * Memory block 0 wired as follows:
+	 * CPU   : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
+	 * SDRAM :  A0  A1  A2  A3  A4  A5  A6 A7  A8  A9 A10 A11 BA0 BA1
+	 *
+	 * Ensure that there is a delay of at least 100 microseconds from
+	 * processor reset to the following code so that the SDRAM is ready
+	 * for commands.
+	 */
+	fudelay(100);
+
+	/*
+	 * DCR
+	 * set proper  RC as per specification
+	 */
+	RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
+	RC = (RC * 15) >> 4;
+
+	/* 0x8000 is the faster option */
+	out_be16(&dc->dcr, 0x8200 | RC);
+
+	/*
+	 * DACR0, page mode continuous, CMD on A20 0x0300
+	 */
+	out_be32(&dc->dacr0, 0x00003304);
+
+	dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
+	out_be32(&dc->dmr0,  dramsize|1);
+
+	/* issue a PRECHARGE ALL */
+	out_be32(&dc->dacr0, 0x0000330c);
+	out_be32((u32 *)0x00000004, 0xbeaddeed);
+	/* issue AUTOREFRESH */
+	out_be32(&dc->dacr0, 0x0000b304);
+	/* let refresh occour */
+	fudelay(1);
+
+	out_be32(&dc->dacr0, 0x0000b344);
+	out_be32((u32 *)0x00000c00, 0xbeaddeed);
+
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
+}
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+CONFIG_SYS_TEXT_BASE = 0xffc00000
+/*
+ * Linker script for Sysam AMCORE board
+ *
+ * (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+OUTPUT_ARCH(m68k)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/m68k/cpu/mcf530x/start.o		(.text)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o	(.text)
+
+    *(.text)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    KEEP(*(.got))
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.sdata)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   _sbss = .;
+   *(.sbss*)
+   *(.bss*)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
+CONFIG_M68K=y
+CONFIG_TARGET_AMCORE=y
+/*
+ * Sysam AMCORE board configuration
+ *
+ * (C) Copyright 2015  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __AMCORE_CONFIG_H
+#define __AMCORE_CONFIG_H
+
+#define CONFIG_AMCORE
+#define CONFIG_HOSTNAME			AMCORE
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_MCF530x
+#define CONFIG_M5307
+
+#define CONFIG_MCFTMR
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		0
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_BOOTCOMMAND		"bootm ffc20000"
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AES
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_XIMG
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_TIMER
+#define CONFIG_CMD_DIAG
+
+#define CONFIG_SYS_PROMPT		"amcore $ "
+/* undef to save memory	*/
+#undef	CONFIG_SYS_LONGHELP
+
+#if defined(CONFIG_CMD_KGDB)
+/* Console I/O buff. size */
+#define CONFIG_SYS_CBSIZE		1024
+#else
+#define CONFIG_SYS_CBSIZE		256
+#endif
+/* Print buffer size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args	*/
+#define CONFIG_SYS_MAXARGS		16
+/* Boot argument buffer size	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	1 /* no console @ startup	*/
+#define CONFIG_AUTO_COMPLETE		1 /* add autocompletion support	*/
+#define CONFIG_LOOPW			1 /* enable loopw command	*/
+#define CONFIG_MX_CYCLIC		1 /* enable mdc/mwc commands	*/
+
+#define CONFIG_SYS_LOAD_ADDR		0x20000	/* default load address */
+
+#define CONFIG_SYS_MEMTEST_START	0x0
+#define CONFIG_SYS_MEMTEST_END		0x1000000
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_SYS_CLK			45000000
+#define CONFIG_SYS_CPU_CLK		(CONFIG_SYS_CLK * 2)
+/* Register Base Addrs */
+#define CONFIG_SYS_MBAR			0x10000000
+/* Definitions for initial stack pointer and data area (in DPRAM) */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
+/* size of internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_SIZE		0x1000000
+#define CONFIG_SYS_FLASH_BASE		0xffc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+/* amcore design has flash data bytes wired swapped */
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
+/* reserve 128-4KB */
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#define CONFIG_SYS_MONITOR_LEN          ((128 - 4) * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_ENV_SECT_SIZE		0x1000
+
+/* memory map space for linux boot data */
+#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
+
+/*
+ * Cache Configuration
+ *
+ * Special 8K version 3 core cache.
+ * This is a single unified instruction/data cache.
+ * sdram - single region - no masks
+ */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CF_ACR_CM_WT | CF_ACR_SM_ALL | \
+					 CF_ACR_EN)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_DCM_P | CF_CACR_ESB | \
+					 CF_CACR_EC)
+
+/* CS0 - AMD Flash, address 0xffc00000 */
+#define	CONFIG_SYS_CS0_BASE		(CONFIG_SYS_FLASH_BASE>>16)
+/* 4MB, AA=0,V=1  C/I BIT for errata */
+#define	CONFIG_SYS_CS0_MASK		0x003f0001
+/* WS=10, AA=1, PS=16bit (10) */
+#define	CONFIG_SYS_CS0_CTRL		0x1980
+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
+#define CONFIG_SYS_CS1_BASE		0x3000
+#define CONFIG_SYS_CS1_MASK		0x00070001
+#define CONFIG_SYS_CS1_CTRL		0x0100
+
+#endif  /* __AMCORE_CONFIG_H */
...	...	@@ -67,6 +67,9 @@
67	67	config TARGET_M5485EVB
68	68	bool "Support M5485EVB"
69	69
	70	+config TARGET_AMCORE
	71	+ bool "Support AMCORE"
	72	+
70	73	endchoice
71	74
72	75	source "board/BuS/eb_cpu5282/Kconfig"
...	...	@@ -89,6 +92,7 @@
89	92	source "board/freescale/m54455evb/Kconfig"
90	93	source "board/freescale/m547xevb/Kconfig"
91	94	source "board/freescale/m548xevb/Kconfig"
	95	+source "board/sysam/amcore/Kconfig"
92	96
93	97	endmenu
	1	+if TARGET_AMCORE
	2	+
	3	+config SYS_CPU
	4	+ string
	5	+ default "mcf530x"
	6	+
	7	+config SYS_BOARD
	8	+ string
	9	+ default "amcore"
	10	+
	11	+config SYS_VENDOR
	12	+ string
	13	+ default "sysam"
	14	+
	15	+config SYS_CONFIG_NAME
	16	+ string
	17	+ default "amcore"
	18	+
	19	+endif
	1	+AMCORE BOARD
	2	+M: Angelo Dureghello <angelo@sysam.it>
	3	+S: Maintained
	4	+F: board/sysam/amcore/
	5	+F: include/configs/amcore.h
	6	+F: configs/amcore_defconfig
	1	+#
	2	+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y = amcore.o
	1	+/*
	2	+ * Board functions for Sysam AMCORE (MCF5307 based) board
	3	+ *
	4	+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ *
	8	+ * This file copies memory testdram() from sandburst/common/sb_common.c
	9	+ */
	10	+
	11	+#include <common.h>
	12	+#include <asm/immap.h>
	13	+#include <asm/io.h>
	14	+
	15	+void init_lcd(void)
	16	+{
	17	+ /* setup for possible K0108 lcd connected on the parallel port */
	18	+ sim_t sim = (sim_t )(MMAP_SIM);
	19	+
	20	+ out_be16(&sim->par, 0x300);
	21	+
	22	+ gpio_t gpio = (gpio_t )(MMAP_GPIO);
	23	+
	24	+ out_be16(&gpio->paddr, 0xfcff);
	25	+ out_be16(&gpio->padat, 0x0c00);
	26	+}
	27	+
	28	+int checkboard(void)
	29	+{
	30	+ puts("Board: ");
	31	+ puts("AMCORE v.001(alpha)\n");
	32	+
	33	+ init_lcd();
	34	+
	35	+ return 0;
	36	+}
	37	+
	38	+/*
	39	+ * in initdram we are here executing from flash
	40	+ * case 1:
	41	+ * is with no ACR/flash cache enabled
	42	+ * nop = 40ns (scope measured)
	43	+ */
	44	+void fudelay(int usec)
	45	+{
	46	+ while (usec--)
	47	+ asm volatile ("nop");
	48	+}
	49	+
	50	+phys_size_t initdram(int board_type)
	51	+{
	52	+ u32 dramsize, RC;
	53	+
	54	+ sdramctrl_t dc = (sdramctrl_t )(MMAP_DRAMC);
	55	+
	56	+ /*
	57	+ * SDRAM MT48LC4M32B2 details
	58	+ * Memory block 0: 16 MB of SDRAM at address $00000000
	59	+ * Port size: 32-bit port
	60	+ *
	61	+ * Memory block 0 wired as follows:
	62	+ * CPU : A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23
	63	+ * SDRAM : A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
	64	+ *
	65	+ * Ensure that there is a delay of at least 100 microseconds from
	66	+ * processor reset to the following code so that the SDRAM is ready
	67	+ * for commands.
	68	+ */
	69	+ fudelay(100);
	70	+
	71	+ /*
	72	+ * DCR
	73	+ * set proper RC as per specification
	74	+ */
	75	+ RC = (CONFIG_SYS_CPU_CLK / 1000000) >> 1;
	76	+ RC = (RC * 15) >> 4;
	77	+
	78	+ /* 0x8000 is the faster option */
	79	+ out_be16(&dc->dcr, 0x8200 \| RC);
	80	+
	81	+ /*
	82	+ * DACR0, page mode continuous, CMD on A20 0x0300
	83	+ */
	84	+ out_be32(&dc->dacr0, 0x00003304);
	85	+
	86	+ dramsize = ((CONFIG_SYS_SDRAM_SIZE)-1) & 0xfffc0000;
	87	+ out_be32(&dc->dmr0, dramsize\|1);
	88	+
	89	+ /* issue a PRECHARGE ALL */
	90	+ out_be32(&dc->dacr0, 0x0000330c);
	91	+ out_be32((u32 *)0x00000004, 0xbeaddeed);
	92	+ /* issue AUTOREFRESH */
	93	+ out_be32(&dc->dacr0, 0x0000b304);
	94	+ /* let refresh occour */
	95	+ fudelay(1);
	96	+
	97	+ out_be32(&dc->dacr0, 0x0000b344);
	98	+ out_be32((u32 *)0x00000c00, 0xbeaddeed);
	99	+
	100	+ return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
	101	+}
	1	+#
	2	+# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+CONFIG_SYS_TEXT_BASE = 0xffc00000
	1	+/*
	2	+ * Linker script for Sysam AMCORE board
	3	+ *
	4	+ * (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+OUTPUT_ARCH(m68k)
	10	+
	11	+SECTIONS
	12	+{
	13	+ /* Read-only sections, merged into text segment: */
	14	+ .text :
	15	+ {
	16	+ arch/m68k/cpu/mcf530x/start.o (.text)
	17	+
	18	+ . = DEFINED(env_offset) ? env_offset : .;
	19	+ common/env_embedded.o (.text)
	20	+
	21	+ *(.text)
	22	+ }
	23	+ _etext = .;
	24	+ PROVIDE (etext = .);
	25	+ .rodata :
	26	+ {
	27	+ (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))
	28	+ }
	29	+
	30	+ /* Read-write section, merged into data segment: */
	31	+ . = (. + 0x00FF) & 0xFFFFFF00;
	32	+ _erotext = .;
	33	+ PROVIDE (erotext = .);
	34	+
	35	+ .reloc :
	36	+ {
	37	+ __got_start = .;
	38	+ KEEP(*(.got))
	39	+ __got_end = .;
	40	+ _GOT2_TABLE_ = .;
	41	+ KEEP(*(.got2))
	42	+ _FIXUP_TABLE_ = .;
	43	+ KEEP(*(.fixup))
	44	+ }
	45	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
	46	+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
	47	+
	48	+ .data :
	49	+ {
	50	+ *(.data)
	51	+ *(.sdata)
	52	+ }
	53	+ _edata = .;
	54	+ PROVIDE (edata = .);
	55	+
	56	+ . = .;
	57	+
	58	+ . = ALIGN(4);
	59	+ .u_boot_list : {
	60	+ KEEP((SORT(.u_boot_list)));
	61	+ }
	62	+
	63	+ . = .;
	64	+ __start___ex_table = .;
	65	+ __ex_table : { *(__ex_table) }
	66	+ __stop___ex_table = .;
	67	+
	68	+ . = ALIGN(256);
	69	+ __init_begin = .;
	70	+ .text.init : { *(.text.init) }
	71	+ .data.init : { *(.data.init) }
	72	+ . = ALIGN(256);
	73	+ __init_end = .;
	74	+
	75	+ __bss_start = .;
	76	+ .bss (NOLOAD) :
	77	+ {
	78	+ _sbss = .;
	79	+ (.sbss)
	80	+ (.bss)
	81	+ *(COMMON)
	82	+ . = ALIGN(4);
	83	+ _ebss = .;
	84	+ }
	85	+ __bss_end = . ;
	86	+ PROVIDE (end = .);
	87	+}
	1	+/*
	2	+ * Sysam AMCORE board configuration
	3	+ *
	4	+ * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef __AMCORE_CONFIG_H
	10	+#define __AMCORE_CONFIG_H
	11	+
	12	+#define CONFIG_AMCORE
	13	+#define CONFIG_HOSTNAME AMCORE
	14	+
	15	+#define CONFIG_SYS_GENERIC_BOARD
	16	+
	17	+#define CONFIG_MCF530x
	18	+#define CONFIG_M5307
	19	+
	20	+#define CONFIG_MCFTMR
	21	+#define CONFIG_MCFUART
	22	+#define CONFIG_SYS_UART_PORT 0
	23	+#define CONFIG_BAUDRATE 115200
	24	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	25	+
	26	+#define CONFIG_BOOTDELAY 1
	27	+#define CONFIG_BOOTCOMMAND "bootm ffc20000"
	28	+
	29	+#include <config_cmd_default.h>
	30	+#undef CONFIG_CMD_AES
	31	+#undef CONFIG_CMD_BOOTD
	32	+#undef CONFIG_CMD_NET
	33	+#undef CONFIG_CMD_NFS
	34	+#undef CONFIG_CMD_FPGA
	35	+#undef CONFIG_CMD_XIMG
	36	+#define CONFIG_CMD_CACHE
	37	+#define CONFIG_CMD_TIMER
	38	+#define CONFIG_CMD_DIAG
	39	+
	40	+#define CONFIG_SYS_PROMPT "amcore $ "
	41	+/* undef to save memory */
	42	+#undef CONFIG_SYS_LONGHELP
	43	+
	44	+#if defined(CONFIG_CMD_KGDB)
	45	+/* Console I/O buff. size */
	46	+#define CONFIG_SYS_CBSIZE 1024
	47	+#else
	48	+#define CONFIG_SYS_CBSIZE 256
	49	+#endif
	50	+/* Print buffer size */
	51	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	52	+ sizeof(CONFIG_SYS_PROMPT)+16)
	53	+/* max number of command args */
	54	+#define CONFIG_SYS_MAXARGS 16
	55	+/* Boot argument buffer size */
	56	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	57	+
	58	+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */
	59	+#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
	60	+#define CONFIG_LOOPW 1 /* enable loopw command */
	61	+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
	62	+
	63	+#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */
	64	+
	65	+#define CONFIG_SYS_MEMTEST_START 0x0
	66	+#define CONFIG_SYS_MEMTEST_END 0x1000000
	67	+
	68	+#define CONFIG_SYS_HZ 1000
	69	+
	70	+#define CONFIG_SYS_CLK 45000000
	71	+#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2)
	72	+/* Register Base Addrs */
	73	+#define CONFIG_SYS_MBAR 0x10000000
	74	+/* Definitions for initial stack pointer and data area (in DPRAM) */
	75	+#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
	76	+/* size of internal SRAM */
	77	+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
	78	+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	79	+ GENERATED_GBL_DATA_SIZE)
	80	+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	81	+
	82	+#define CONFIG_SYS_SDRAM_BASE 0x00000000
	83	+#define CONFIG_SYS_SDRAM_SIZE 0x1000000
	84	+#define CONFIG_SYS_FLASH_BASE 0xffc00000
	85	+#define CONFIG_SYS_MAX_FLASH_BANKS 1
	86	+#define CONFIG_SYS_MAX_FLASH_SECT 1024
	87	+#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
	88	+
	89	+#define CONFIG_SYS_FLASH_CFI
	90	+#define CONFIG_FLASH_CFI_DRIVER
	91	+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	92	+/* amcore design has flash data bytes wired swapped */
	93	+#define CONFIG_SYS_WRITE_SWAPPED_DATA
	94	+/* reserve 128-4KB */
	95	+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	96	+#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
	97	+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
	98	+#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
	99	+
	100	+#define CONFIG_ENV_IS_IN_FLASH 1
	101	+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
	102	+ CONFIG_SYS_MONITOR_LEN)
	103	+#define CONFIG_ENV_SIZE 0x1000
	104	+#define CONFIG_ENV_SECT_SIZE 0x1000
	105	+
	106	+/* memory map space for linux boot data */
	107	+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
	108	+
	109	+/*
	110	+ * Cache Configuration
	111	+ *
	112	+ * Special 8K version 3 core cache.
	113	+ * This is a single unified instruction/data cache.
	114	+ * sdram - single region - no masks
	115	+ */
	116	+#define CONFIG_SYS_CACHELINE_SIZE 16
	117	+
	118	+#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	119	+ CONFIG_SYS_INIT_RAM_SIZE - 8)
	120	+#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	121	+ CONFIG_SYS_INIT_RAM_SIZE - 4)
	122	+#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	123	+#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT \| CF_ACR_SM_ALL \| \
	124	+ CF_ACR_EN)
	125	+#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P \| CF_CACR_ESB \| \
	126	+ CF_CACR_EC)
	127	+
	128	+/* CS0 - AMD Flash, address 0xffc00000 */
	129	+#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16)
	130	+/* 4MB, AA=0,V=1 C/I BIT for errata */
	131	+#define CONFIG_SYS_CS0_MASK 0x003f0001
	132	+/* WS=10, AA=1, PS=16bit (10) */
	133	+#define CONFIG_SYS_CS0_CTRL 0x1980
	134	+/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */
	135	+#define CONFIG_SYS_CS1_BASE 0x3000
	136	+#define CONFIG_SYS_CS1_MASK 0x00070001
	137	+#define CONFIG_SYS_CS1_CTRL 0x0100
	138	+
	139	+#endif /* __AMCORE_CONFIG_H */