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Commit 071d897c96460c414786ef1d40f3e56f8d9fb8cb

Authored by stroese 2003-05-23 19:35:47 +0800

1 parent 3871842529

Exists in master and in 54 other branches

PMC405 board added.

Showing 6 changed files with 1518 additions and 0 deletions Side-by-side Diff

board/esd/pmc405/Makefile
board/esd/pmc405/config.mk
board/esd/pmc405/pmc405.c
board/esd/pmc405/strataflash.c
board/esd/pmc405/u-boot.lds
include/configs/PMC405.h

board/esd/pmc405/Makefile

Diff comments View file @ 071d897

	1	+#
	2	+# (C) Copyright 2000, 2001
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = lib$(BOARD).a
	27	+
	28	+OBJS = $(BOARD).o strataflash.o
	29	+
	30	+$(LIB): $(OBJS) $(SOBJS)
	31	+ $(AR) crv $@ $^
	32	+
	33	+clean:
	34	+ rm -f $(SOBJS) $(OBJS)
	35	+
	36	+distclean: clean
	37	+ rm -f $(LIB) core *.bak .depend
	38	+
	39	+#########################################################################
	40	+
	41	+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
	42	+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
	43	+
	44	+sinclude .depend
	45	+
	46	+#########################################################################

board/esd/pmc405/config.mk

Diff comments View file @ 071d897

	1	+#
	2	+# (C) Copyright 2000, 2001
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+#
	25	+# esd PMC405 boards
	26	+#
	27	+
	28	+TEXT_BASE = 0xFFFC0000

board/esd/pmc405/pmc405.c

Diff comments View file @ 071d897

	1	+/*
	2	+ * (C) Copyright 2001-2003
	3	+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/processor.h>
	26	+#include <command.h>
	27	+#include <cmd_boot.h>
	28	+#include <malloc.h>
	29	+
	30	+/* ------------------------------------------------------------------------- */
	31	+
	32	+
	33	+/* Prototypes */
	34	+int gunzip(void , int, unsigned char , int *);
	35	+
	36	+
	37	+int board_pre_init (void)
	38	+{
	39	+ /*
	40	+ * IRQ 0-15 405GP internally generated; active high; level sensitive
	41	+ * IRQ 16 405GP internally generated; active low; level sensitive
	42	+ * IRQ 17-24 RESERVED
	43	+ * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
	44	+ * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
	45	+ * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
	46	+ * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
	47	+ * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
	48	+ * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
	49	+ * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
	50	+ */
	51	+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	52	+ mtdcr(uicer, 0x00000000); /* disable all ints */
	53	+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
	54	+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
	55	+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
	56	+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
	57	+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
	58	+
	59	+ /*
	60	+ * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
	61	+ */
	62	+ mtebc (epcr, 0xa8400000);
	63	+
	64	+ return 0;
	65	+}
	66	+
	67	+
	68	+/* ------------------------------------------------------------------------- */
	69	+
	70	+int misc_init_f (void)
	71	+{
	72	+ return 0; /* dummy implementation */
	73	+}
	74	+
	75	+
	76	+int misc_init_r (void)
	77	+{
	78	+#if 0 /* test-only */
	79	+ DECLARE_GLOBAL_DATA_PTR;
	80	+ volatile unsigned short *fpga_mode =
	81	+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
	82	+ volatile unsigned char *duart0_mcr =
	83	+ (unsigned char *)((ulong)DUART0_BA + 4);
	84	+ volatile unsigned char *duart1_mcr =
	85	+ (unsigned char *)((ulong)DUART1_BA + 4);
	86	+ bd_t *bd = gd->bd;
	87	+ char * tmp; /* Temporary char pointer */
	88	+ unsigned char *dst;
	89	+ ulong len = sizeof(fpgadata);
	90	+ int status;
	91	+ int index;
	92	+ int i;
	93	+ unsigned long cntrl0Reg;
	94	+
	95	+ /*
	96	+ * Setup GPIO pins (CS6+CS7 as GPIO)
	97	+ */
	98	+ cntrl0Reg = mfdcr(cntrl0);
	99	+ mtdcr(cntrl0, cntrl0Reg \| 0x00300000);
	100	+
	101	+ dst = malloc(CFG_FPGA_MAX_SIZE);
	102	+ if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar )fpgadata, (int )&len) != 0) {
	103	+ printf ("GUNZIP ERROR - must RESET board to recover\n");
	104	+ do_reset (NULL, 0, 0, NULL);
	105	+ }
	106	+
	107	+ status = fpga_boot(dst, len);
	108	+ if (status != 0) {
	109	+ printf("\nFPGA: Booting failed ");
	110	+ switch (status) {
	111	+ case ERROR_FPGA_PRG_INIT_LOW:
	112	+ printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	113	+ break;
	114	+ case ERROR_FPGA_PRG_INIT_HIGH:
	115	+ printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	116	+ break;
	117	+ case ERROR_FPGA_PRG_DONE:
	118	+ printf("(Timeout: DONE not high after programming FPGA)\n ");
	119	+ break;
	120	+ }
	121	+
	122	+ /* display infos on fpgaimage */
	123	+ index = 15;
	124	+ for (i=0; i<4; i++) {
	125	+ len = dst[index];
	126	+ printf("FPGA: %s\n", &(dst[index+1]));
	127	+ index += len+3;
	128	+ }
	129	+ putc ('\n');
	130	+ /* delayed reboot */
	131	+ for (i=20; i>0; i--) {
	132	+ printf("Rebooting in %2d seconds \r",i);
	133	+ for (index=0;index<1000;index++)
	134	+ udelay(1000);
	135	+ }
	136	+ putc ('\n');
	137	+ do_reset(NULL, 0, 0, NULL);
	138	+ }
	139	+
	140	+ /* restore gpio/cs settings */
	141	+ mtdcr(cntrl0, cntrl0Reg);
	142	+
	143	+ puts("FPGA: ");
	144	+
	145	+ /* display infos on fpgaimage */
	146	+ index = 15;
	147	+ for (i=0; i<4; i++) {
	148	+ len = dst[index];
	149	+ printf("%s ", &(dst[index+1]));
	150	+ index += len+3;
	151	+ }
	152	+ putc ('\n');
	153	+
	154	+ free(dst);
	155	+
	156	+ /*
	157	+ * Reset FPGA via FPGA_DATA pin
	158	+ */
	159	+ SET_FPGA(FPGA_PRG \| FPGA_CLK);
	160	+ udelay(1000); /* wait 1ms */
	161	+ SET_FPGA(FPGA_PRG \| FPGA_CLK \| FPGA_DATA);
	162	+ udelay(1000); /* wait 1ms */
	163	+
	164	+ /*
	165	+ * Enable power on PS/2 interface
	166	+ */
	167	+ *fpga_mode \|= CFG_FPGA_CTRL_PS2_RESET;
	168	+
	169	+ /*
	170	+ * Enable interrupts in exar duart mcr[3]
	171	+ */
	172	+ *duart0_mcr = 0x08;
	173	+ *duart1_mcr = 0x08;
	174	+#endif
	175	+
	176	+ return (0);
	177	+}
	178	+
	179	+
	180	+/*
	181	+ * Check Board Identity:
	182	+ */
	183	+
	184	+int checkboard (void)
	185	+{
	186	+ unsigned char str[64];
	187	+ int i = getenv_r ("serial#", str, sizeof(str));
	188	+
	189	+ puts ("Board: ");
	190	+
	191	+ if (i == -1) {
	192	+ puts ("### No HW ID - assuming ABG405");
	193	+ } else {
	194	+ puts(str);
	195	+ }
	196	+
	197	+ putc ('\n');
	198	+
	199	+ return 0;
	200	+}
	201	+
	202	+/* ------------------------------------------------------------------------- */
	203	+
	204	+long int initdram (int board_type)
	205	+{
	206	+ unsigned long val;
	207	+
	208	+ mtdcr(memcfga, mem_mb0cf);
	209	+ val = mfdcr(memcfgd);
	210	+
	211	+#if 0
	212	+ printf("\nmb0cf=%x\n", val); /* test-only */
	213	+ printf("strap=%x\n", mfdcr(strap)); /* test-only */
	214	+#endif
	215	+
	216	+ return (410241024 << ((val & 0x000e0000) >> 17));
	217	+}
	218	+
	219	+/* ------------------------------------------------------------------------- */
	220	+
	221	+int testdram (void)
	222	+{
	223	+ /* TODO: XXX XXX XXX */
	224	+ printf ("test: 16 MB - ok\n");
	225	+
	226	+ return (0);
	227	+}
	228	+
	229	+/* ------------------------------------------------------------------------- */

board/esd/pmc405/strataflash.c

Diff comments View file @ 071d897

	1	+/*
	2	+ * (C) Copyright 2002
	3	+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <asm/processor.h>
	26	+
	27	+#undef DEBUG_FLASH
	28	+/*
	29	+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
	30	+ * The width of the port and the width of the chips are determined at initialization.
	31	+ * These widths are used to calculate the address for access CFI data structures.
	32	+ * It has been tested on an Intel Strataflash implementation.
	33	+ *
	34	+ * References
	35	+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
	36	+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
	37	+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
	38	+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
	39	+ *
	40	+ * TODO
	41	+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
	42	+ * Add support for other command sets Use the PRI and ALT to determine command set
	43	+ * Verify erase and program timeouts.
	44	+ */
	45	+
	46	+#define FLASH_CMD_CFI 0x98
	47	+#define FLASH_CMD_READ_ID 0x90
	48	+#define FLASH_CMD_RESET 0xff
	49	+#define FLASH_CMD_BLOCK_ERASE 0x20
	50	+#define FLASH_CMD_ERASE_CONFIRM 0xD0
	51	+#define FLASH_CMD_WRITE 0x40
	52	+#define FLASH_CMD_PROTECT 0x60
	53	+#define FLASH_CMD_PROTECT_SET 0x01
	54	+#define FLASH_CMD_PROTECT_CLEAR 0xD0
	55	+#define FLASH_CMD_CLEAR_STATUS 0x50
	56	+#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
	57	+#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
	58	+
	59	+#define FLASH_STATUS_DONE 0x80
	60	+#define FLASH_STATUS_ESS 0x40
	61	+#define FLASH_STATUS_ECLBS 0x20
	62	+#define FLASH_STATUS_PSLBS 0x10
	63	+#define FLASH_STATUS_VPENS 0x08
	64	+#define FLASH_STATUS_PSS 0x04
	65	+#define FLASH_STATUS_DPS 0x02
	66	+#define FLASH_STATUS_R 0x01
	67	+#define FLASH_STATUS_PROTECT 0x01
	68	+
	69	+#define FLASH_OFFSET_CFI 0x55
	70	+#define FLASH_OFFSET_CFI_RESP 0x10
	71	+#define FLASH_OFFSET_WTOUT 0x1F
	72	+#define FLASH_OFFSET_WBTOUT 0x20
	73	+#define FLASH_OFFSET_ETOUT 0x21
	74	+#define FLASH_OFFSET_CETOUT 0x22
	75	+#define FLASH_OFFSET_WMAX_TOUT 0x23
	76	+#define FLASH_OFFSET_WBMAX_TOUT 0x24
	77	+#define FLASH_OFFSET_EMAX_TOUT 0x25
	78	+#define FLASH_OFFSET_CEMAX_TOUT 0x26
	79	+#define FLASH_OFFSET_SIZE 0x27
	80	+#define FLASH_OFFSET_INTERFACE 0x28
	81	+#define FLASH_OFFSET_BUFFER_SIZE 0x2A
	82	+#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
	83	+#define FLASH_OFFSET_ERASE_REGIONS 0x2D
	84	+#define FLASH_OFFSET_PROTECT 0x02
	85	+#define FLASH_OFFSET_USER_PROTECTION 0x85
	86	+#define FLASH_OFFSET_INTEL_PROTECTION 0x81
	87	+
	88	+
	89	+#define FLASH_MAN_CFI 0x01000000
	90	+
	91	+
	92	+
	93	+
	94	+typedef union {
	95	+ unsigned char c;
	96	+ unsigned short w;
	97	+ unsigned long l;
	98	+} cfiword_t;
	99	+
	100	+typedef union {
	101	+ unsigned char * cp;
	102	+ unsigned short *wp;
	103	+ unsigned long *lp;
	104	+} cfiptr_t;
	105	+
	106	+#define NUM_ERASE_REGIONS 4
	107	+
	108	+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	109	+
	110	+
	111	+/*-----------------------------------------------------------------------
	112	+ * Functions
	113	+ */
	114	+
	115	+
	116	+
	117	+static void flash_add_byte(flash_info_t info, cfiword_t cword, uchar c);
	118	+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
	119	+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
	120	+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
	121	+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
	122	+static int flash_detect_cfi(flash_info_t * info);
	123	+static ulong flash_get_size (ulong base, int banknum);
	124	+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
	125	+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
	126	+#ifdef CFG_FLASH_USE_BUFFER_WRITE
	127	+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
	128	+#endif
	129	+/*-----------------------------------------------------------------------
	130	+ * create an address based on the offset and the port width
	131	+ */
	132	+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
	133	+{
	134	+ return ((uchar )(info->start[sect] + (offset info->portwidth)));
	135	+}
	136	+/*-----------------------------------------------------------------------
	137	+ * read a character at a port width address
	138	+ */
	139	+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
	140	+{
	141	+ uchar *cp;
	142	+ cp = flash_make_addr(info, 0, offset);
	143	+ return (cp[info->portwidth - 1]);
	144	+}
	145	+
	146	+/*-----------------------------------------------------------------------
	147	+ * read a short word by swapping for ppc format.
	148	+ */
	149	+ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
	150	+{
	151	+ uchar * addr;
	152	+
	153	+ addr = flash_make_addr(info, sect, offset);
	154	+ return ((addr[(2*info->portwidth) - 1] << 8) \| addr[info->portwidth - 1]);
	155	+
	156	+}
	157	+
	158	+/*-----------------------------------------------------------------------
	159	+ * read a long word by picking the least significant byte of each maiximum
	160	+ * port size word. Swap for ppc format.
	161	+ */
	162	+ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
	163	+{
	164	+ uchar * addr;
	165	+
	166	+ addr = flash_make_addr(info, sect, offset);
	167	+ return ( (addr[(2*info->portwidth) - 1] << 24 ) \| (addr[(info->portwidth) -1] << 16) \|
	168	+ (addr[(4info->portwidth) - 1] << 8) \| addr[(3info->portwidth) - 1]);
	169	+
	170	+}
	171	+
	172	+/*-----------------------------------------------------------------------
	173	+ */
	174	+unsigned long flash_init (void)
	175	+{
	176	+ unsigned long size;
	177	+ int i;
	178	+ unsigned long address;
	179	+
	180	+
	181	+ /* The flash is positioned back to back, with the demultiplexing of the chip
	182	+ * based on the A24 address line.
	183	+ *
	184	+ */
	185	+
	186	+ address = CFG_FLASH_BASE;
	187	+ size = 0;
	188	+
	189	+ /* Init: no FLASHes known */
	190	+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
	191	+ flash_info[i].flash_id = FLASH_UNKNOWN;
	192	+ size += flash_info[i].size = flash_get_size(address, i);
	193	+ address += CFG_FLASH_INCREMENT;
	194	+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
	195	+ printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
	196	+ flash_info[0].size, flash_info[i].size<<20);
	197	+ }
	198	+ }
	199	+
	200	+#if 0 /* test-only */
	201	+ /* Monitor protection ON by default */
	202	+#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
	203	+ for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
	204	+ (void)flash_real_protect(&flash_info[0], i, 1);
	205	+#endif
	206	+#else
	207	+ /* monitor protection ON by default */
	208	+ flash_protect (FLAG_PROTECT_SET,
	209	+ - CFG_MONITOR_LEN,
	210	+ - 1, &flash_info[1]);
	211	+#endif
	212	+
	213	+ return (size);
	214	+}
	215	+
	216	+/*-----------------------------------------------------------------------
	217	+ */
	218	+int flash_erase (flash_info_t *info, int s_first, int s_last)
	219	+{
	220	+ int rcode = 0;
	221	+ int prot;
	222	+ int sect;
	223	+
	224	+ if( info->flash_id != FLASH_MAN_CFI) {
	225	+ printf ("Can't erase unknown flash type - aborted\n");
	226	+ return 1;
	227	+ }
	228	+ if ((s_first < 0) \|\| (s_first > s_last)) {
	229	+ printf ("- no sectors to erase\n");
	230	+ return 1;
	231	+ }
	232	+
	233	+ prot = 0;
	234	+ for (sect=s_first; sect<=s_last; ++sect) {
	235	+ if (info->protect[sect]) {
	236	+ prot++;
	237	+ }
	238	+ }
	239	+ if (prot) {
	240	+ printf ("- Warning: %d protected sectors will not be erased!\n",
	241	+ prot);
	242	+ } else {
	243	+ printf ("\n");
	244	+ }
	245	+
	246	+
	247	+ for (sect = s_first; sect<=s_last; sect++) {
	248	+ if (info->protect[sect] == 0) { /* not protected */
	249	+ flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
	250	+ flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
	251	+ flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
	252	+
	253	+ if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
	254	+ rcode = 1;
	255	+ } else
	256	+ printf(".");
	257	+ }
	258	+ }
	259	+ printf (" done\n");
	260	+ return rcode;
	261	+}
	262	+
	263	+/*-----------------------------------------------------------------------
	264	+ */
	265	+void flash_print_info (flash_info_t *info)
	266	+{
	267	+ int i;
	268	+
	269	+ if (info->flash_id != FLASH_MAN_CFI) {
	270	+ printf ("missing or unknown FLASH type\n");
	271	+ return;
	272	+ }
	273	+
	274	+ printf("CFI conformant FLASH (%d x %d)",
	275	+ (info->portwidth << 3 ), (info->chipwidth << 3 ));
	276	+ printf (" Size: %ld MB in %d Sectors\n",
	277	+ info->size >> 20, info->sector_count);
	278	+ printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
	279	+ info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
	280	+
	281	+ printf (" Sector Start Addresses:");
	282	+ for (i=0; i<info->sector_count; ++i) {
	283	+#ifdef CFG_FLASH_EMPTY_INFO
	284	+ int k;
	285	+ int size;
	286	+ int erased;
	287	+ volatile unsigned long *flash;
	288	+
	289	+ /*
	290	+ * Check if whole sector is erased
	291	+ */
	292	+ if (i != (info->sector_count-1))
	293	+ size = info->start[i+1] - info->start[i];
	294	+ else
	295	+ size = info->start[0] + info->size - info->start[i];
	296	+ erased = 1;
	297	+ flash = (volatile unsigned long *)info->start[i];
	298	+ size = size >> 2; /* divide by 4 for longword access */
	299	+ for (k=0; k<size; k++)
	300	+ {
	301	+ if (*flash++ != 0xffffffff)
	302	+ {
	303	+ erased = 0;
	304	+ break;
	305	+ }
	306	+ }
	307	+
	308	+ if ((i % 5) == 0)
	309	+ printf ("\n ");
	310	+ /* print empty and read-only info */
	311	+ printf (" %08lX%s%s",
	312	+ info->start[i],
	313	+ erased ? " E" : " ",
	314	+ info->protect[i] ? "RO " : " ");
	315	+#else
	316	+ if ((i % 5) == 0)
	317	+ printf ("\n ");
	318	+ printf (" %08lX%s",
	319	+ info->start[i],
	320	+ info->protect[i] ? " (RO)" : " ");
	321	+#endif
	322	+ }
	323	+ printf ("\n");
	324	+ return;
	325	+}
	326	+
	327	+/*-----------------------------------------------------------------------
	328	+ * Copy memory to flash, returns:
	329	+ * 0 - OK
	330	+ * 1 - write timeout
	331	+ * 2 - Flash not erased
	332	+ */
	333	+int write_buff (flash_info_t info, uchar src, ulong addr, ulong cnt)
	334	+{
	335	+ ulong wp;
	336	+ ulong cp;
	337	+ int aln;
	338	+ cfiword_t cword;
	339	+ int i, rc;
	340	+
	341	+ /* get lower aligned address */
	342	+ wp = (addr & ~(info->portwidth - 1));
	343	+
	344	+ /* handle unaligned start */
	345	+ if((aln = addr - wp) != 0) {
	346	+ cword.l = 0;
	347	+ cp = wp;
	348	+ for(i=0;i<aln; ++i, ++cp)
	349	+ flash_add_byte(info, &cword, ((uchar )cp));
	350	+
	351	+ for(; (i< info->portwidth) && (cnt > 0) ; i++) {
	352	+ flash_add_byte(info, &cword, *src++);
	353	+ cnt--;
	354	+ cp++;
	355	+ }
	356	+ for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
	357	+ flash_add_byte(info, &cword, ((uchar )cp));
	358	+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
	359	+ return rc;
	360	+ wp = cp;
	361	+ }
	362	+
	363	+#ifdef CFG_FLASH_USE_BUFFER_WRITE
	364	+ while(cnt >= info->portwidth) {
	365	+ i = info->buffer_size > cnt? cnt: info->buffer_size;
	366	+ if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
	367	+ return rc;
	368	+ wp += i;
	369	+ src += i;
	370	+ cnt -=i;
	371	+ }
	372	+#else
	373	+ /* handle the aligned part */
	374	+ while(cnt >= info->portwidth) {
	375	+ cword.l = 0;
	376	+ for(i = 0; i < info->portwidth; i++) {
	377	+ flash_add_byte(info, &cword, *src++);
	378	+ }
	379	+ if((rc = flash_write_cfiword(info, wp, cword)) != 0)
	380	+ return rc;
	381	+ wp += info->portwidth;
	382	+ cnt -= info->portwidth;
	383	+ }
	384	+#endif /* CFG_FLASH_USE_BUFFER_WRITE */
	385	+ if (cnt == 0) {
	386	+ return (0);
	387	+ }
	388	+
	389	+ /*
	390	+ * handle unaligned tail bytes
	391	+ */
	392	+ cword.l = 0;
	393	+ for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
	394	+ flash_add_byte(info, &cword, *src++);
	395	+ --cnt;
	396	+ }
	397	+ for (; i<info->portwidth; ++i, ++cp) {
	398	+ flash_add_byte(info, & cword, ((uchar )cp));
	399	+ }
	400	+
	401	+ return flash_write_cfiword(info, wp, cword);
	402	+}
	403	+
	404	+/*-----------------------------------------------------------------------
	405	+ */
	406	+int flash_real_protect(flash_info_t *info, long sector, int prot)
	407	+{
	408	+ int retcode = 0;
	409	+
	410	+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	411	+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
	412	+ if(prot)
	413	+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
	414	+ else
	415	+ flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
	416	+
	417	+ if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
	418	+ prot?"protect":"unprotect")) == 0) {
	419	+
	420	+ info->protect[sector] = prot;
	421	+ /* Intel's unprotect unprotects all locking */
	422	+ if(prot == 0) {
	423	+ int i;
	424	+ for(i = 0 ; i<info->sector_count; i++) {
	425	+ if(info->protect[i])
	426	+ flash_real_protect(info, i, 1);
	427	+ }
	428	+ }
	429	+ }
	430	+
	431	+ return retcode;
	432	+}
	433	+/*-----------------------------------------------------------------------
	434	+ * wait for XSR.7 to be set. Time out with an error if it does not.
	435	+ * This routine does not set the flash to read-array mode.
	436	+ */
	437	+static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
	438	+{
	439	+ ulong start;
	440	+
	441	+ /* Wait for command completion */
	442	+ start = get_timer (0);
	443	+ while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
	444	+ if (get_timer(start) > info->erase_blk_tout) {
	445	+ printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
	446	+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
	447	+ return ERR_TIMOUT;
	448	+ }
	449	+ }
	450	+ return ERR_OK;
	451	+}
	452	+/*-----------------------------------------------------------------------
	453	+ * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
	454	+ * This routine sets the flash to read-array mode.
	455	+ */
	456	+static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
	457	+{
	458	+ int retcode;
	459	+ retcode = flash_status_check(info, sector, tout, prompt);
	460	+ if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
	461	+ retcode = ERR_INVAL;
	462	+ printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
	463	+ if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS \| FLASH_STATUS_PSLBS)){
	464	+ printf("Command Sequence Error.\n");
	465	+ } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
	466	+ printf("Block Erase Error.\n");
	467	+ retcode = ERR_NOT_ERASED;
	468	+ } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
	469	+ printf("Locking Error\n");
	470	+ }
	471	+ if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
	472	+ printf("Block locked.\n");
	473	+ retcode = ERR_PROTECTED;
	474	+ }
	475	+ if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
	476	+ printf("Vpp Low Error.\n");
	477	+ }
	478	+ flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
	479	+ return retcode;
	480	+}
	481	+/*-----------------------------------------------------------------------
	482	+ */
	483	+static void flash_add_byte(flash_info_t info, cfiword_t cword, uchar c)
	484	+{
	485	+ switch(info->portwidth) {
	486	+ case FLASH_CFI_8BIT:
	487	+ cword->c = c;
	488	+ break;
	489	+ case FLASH_CFI_16BIT:
	490	+ cword->w = (cword->w << 8) \| c;
	491	+ break;
	492	+ case FLASH_CFI_32BIT:
	493	+ cword->l = (cword->l << 8) \| c;
	494	+ }
	495	+}
	496	+
	497	+
	498	+/*-----------------------------------------------------------------------
	499	+ * make a proper sized command based on the port and chip widths
	500	+ */
	501	+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
	502	+{
	503	+ int i;
	504	+ uchar cp = (uchar )cmdbuf;
	505	+ for(i=0; i< info->portwidth; i++)
	506	+ *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
	507	+}
	508	+
	509	+/*
	510	+ * Write a proper sized command to the correct address
	511	+ */
	512	+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
	513	+{
	514	+
	515	+ volatile cfiptr_t addr;
	516	+ cfiword_t cword;
	517	+ addr.cp = flash_make_addr(info, sect, offset);
	518	+ flash_make_cmd(info, cmd, &cword);
	519	+ switch(info->portwidth) {
	520	+ case FLASH_CFI_8BIT:
	521	+ *addr.cp = cword.c;
	522	+ break;
	523	+ case FLASH_CFI_16BIT:
	524	+ *addr.wp = cword.w;
	525	+ break;
	526	+ case FLASH_CFI_32BIT:
	527	+ *addr.lp = cword.l;
	528	+ break;
	529	+ }
	530	+}
	531	+
	532	+/*-----------------------------------------------------------------------
	533	+ */
	534	+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
	535	+{
	536	+ cfiptr_t cptr;
	537	+ cfiword_t cword;
	538	+ int retval;
	539	+ cptr.cp = flash_make_addr(info, sect, offset);
	540	+ flash_make_cmd(info, cmd, &cword);
	541	+ switch(info->portwidth) {
	542	+ case FLASH_CFI_8BIT:
	543	+ retval = (cptr.cp[0] == cword.c);
	544	+ break;
	545	+ case FLASH_CFI_16BIT:
	546	+ retval = (cptr.wp[0] == cword.w);
	547	+ break;
	548	+ case FLASH_CFI_32BIT:
	549	+ retval = (cptr.lp[0] == cword.l);
	550	+ break;
	551	+ default:
	552	+ retval = 0;
	553	+ break;
	554	+ }
	555	+ return retval;
	556	+}
	557	+/*-----------------------------------------------------------------------
	558	+ */
	559	+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
	560	+{
	561	+ cfiptr_t cptr;
	562	+ cfiword_t cword;
	563	+ int retval;
	564	+ cptr.cp = flash_make_addr(info, sect, offset);
	565	+ flash_make_cmd(info, cmd, &cword);
	566	+ switch(info->portwidth) {
	567	+ case FLASH_CFI_8BIT:
	568	+ retval = ((cptr.cp[0] & cword.c) == cword.c);
	569	+ break;
	570	+ case FLASH_CFI_16BIT:
	571	+ retval = ((cptr.wp[0] & cword.w) == cword.w);
	572	+ break;
	573	+ case FLASH_CFI_32BIT:
	574	+ retval = ((cptr.lp[0] & cword.l) == cword.l);
	575	+ break;
	576	+ default:
	577	+ retval = 0;
	578	+ break;
	579	+ }
	580	+ return retval;
	581	+}
	582	+
	583	+/*-----------------------------------------------------------------------
	584	+ * detect if flash is compatible with the Common Flash Interface (CFI)
	585	+ * http://www.jedec.org/download/search/jesd68.pdf
	586	+ *
	587	+*/
	588	+static int flash_detect_cfi(flash_info_t * info)
	589	+{
	590	+
	591	+ for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
	592	+ info->portwidth <<= 1) {
	593	+ for(info->chipwidth =FLASH_CFI_BY8;
	594	+ info->chipwidth <= info->portwidth;
	595	+ info->chipwidth <<= 1) {
	596	+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
	597	+ flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
	598	+ if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
	599	+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
	600	+ flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
	601	+ return 1;
	602	+ }
	603	+ }
	604	+ return 0;
	605	+}
	606	+/*
	607	+ * The following code cannot be run from FLASH!
	608	+ *
	609	+ */
	610	+static ulong flash_get_size (ulong base, int banknum)
	611	+{
	612	+ flash_info_t * info = &flash_info[banknum];
	613	+ int i, j;
	614	+ int sect_cnt;
	615	+ unsigned long sector;
	616	+ unsigned long tmp;
	617	+ int size_ratio;
	618	+ uchar num_erase_regions;
	619	+ int erase_region_size;
	620	+ int erase_region_count;
	621	+
	622	+ info->start[0] = base;
	623	+
	624	+ if(flash_detect_cfi(info)){
	625	+#ifdef DEBUG_FLASH
	626	+ printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
	627	+#endif
	628	+ size_ratio = info->portwidth / info->chipwidth;
	629	+ num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
	630	+#ifdef DEBUG_FLASH
	631	+ printf("found %d erase regions\n", num_erase_regions);
	632	+#endif
	633	+ sect_cnt = 0;
	634	+ sector = base;
	635	+ for(i = 0 ; i < num_erase_regions; i++) {
	636	+ if(i > NUM_ERASE_REGIONS) {
	637	+ printf("%d erase regions found, only %d used\n",
	638	+ num_erase_regions, NUM_ERASE_REGIONS);
	639	+ break;
	640	+ }
	641	+ tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
	642	+ erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
	643	+ tmp >>= 16;
	644	+ erase_region_count = (tmp & 0xffff) +1;
	645	+ for(j = 0; j< erase_region_count; j++) {
	646	+ info->start[sect_cnt] = sector;
	647	+ sector += (erase_region_size * size_ratio);
	648	+ info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
	649	+ sect_cnt++;
	650	+ }
	651	+ }
	652	+
	653	+ info->sector_count = sect_cnt;
	654	+ /* multiply the size by the number of chips */
	655	+ info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
	656	+ info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
	657	+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
	658	+ info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
	659	+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
	660	+ info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
	661	+ tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
	662	+ info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
	663	+ info->flash_id = FLASH_MAN_CFI;
	664	+ }
	665	+
	666	+ flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
	667	+ return(info->size);
	668	+}
	669	+
	670	+
	671	+/*-----------------------------------------------------------------------
	672	+ */
	673	+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
	674	+{
	675	+
	676	+ cfiptr_t ctladdr;
	677	+ cfiptr_t cptr;
	678	+ int flag;
	679	+
	680	+ ctladdr.cp = flash_make_addr(info, 0, 0);
	681	+ cptr.cp = (uchar *)dest;
	682	+
	683	+
	684	+ /* Check if Flash is (sufficiently) erased */
	685	+ switch(info->portwidth) {
	686	+ case FLASH_CFI_8BIT:
	687	+ flag = ((cptr.cp[0] & cword.c) == cword.c);
	688	+ break;
	689	+ case FLASH_CFI_16BIT:
	690	+ flag = ((cptr.wp[0] & cword.w) == cword.w);
	691	+ break;
	692	+ case FLASH_CFI_32BIT:
	693	+ flag = ((cptr.lp[0] & cword.l) == cword.l);
	694	+ break;
	695	+ default:
	696	+ return 2;
	697	+ }
	698	+ if(!flag)
	699	+ return 2;
	700	+
	701	+ /* Disable interrupts which might cause a timeout here */
	702	+ flag = disable_interrupts();
	703	+
	704	+ flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
	705	+ flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
	706	+
	707	+ switch(info->portwidth) {
	708	+ case FLASH_CFI_8BIT:
	709	+ cptr.cp[0] = cword.c;
	710	+ break;
	711	+ case FLASH_CFI_16BIT:
	712	+ cptr.wp[0] = cword.w;
	713	+ break;
	714	+ case FLASH_CFI_32BIT:
	715	+ cptr.lp[0] = cword.l;
	716	+ break;
	717	+ }
	718	+
	719	+ /* re-enable interrupts if necessary */
	720	+ if(flag)
	721	+ enable_interrupts();
	722	+
	723	+ return flash_full_status_check(info, 0, info->write_tout, "write");
	724	+}
	725	+
	726	+#ifdef CFG_FLASH_USE_BUFFER_WRITE
	727	+
	728	+/* loop through the sectors from the highest address
	729	+ * when the passed address is greater or equal to the sector address
	730	+ * we have a match
	731	+ */
	732	+static int find_sector(flash_info_t *info, ulong addr)
	733	+{
	734	+ int sector;
	735	+ for(sector = info->sector_count - 1; sector >= 0; sector--) {
	736	+ if(addr >= info->start[sector])
	737	+ break;
	738	+ }
	739	+ return sector;
	740	+}
	741	+
	742	+static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
	743	+{
	744	+
	745	+ int sector;
	746	+ int cnt;
	747	+ int retcode;
	748	+ volatile cfiptr_t src;
	749	+ volatile cfiptr_t dst;
	750	+
	751	+ src.cp = cp;
	752	+ dst.cp = (uchar *)dest;
	753	+ sector = find_sector(info, dest);
	754	+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	755	+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
	756	+ if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
	757	+ "write to buffer")) == ERR_OK) {
	758	+ switch(info->portwidth) {
	759	+ case FLASH_CFI_8BIT:
	760	+ cnt = len;
	761	+ break;
	762	+ case FLASH_CFI_16BIT:
	763	+ cnt = len >> 1;
	764	+ break;
	765	+ case FLASH_CFI_32BIT:
	766	+ cnt = len >> 2;
	767	+ break;
	768	+ default:
	769	+ return ERR_INVAL;
	770	+ break;
	771	+ }
	772	+ flash_write_cmd(info, sector, 0, (uchar)cnt-1);
	773	+ while(cnt-- > 0) {
	774	+ switch(info->portwidth) {
	775	+ case FLASH_CFI_8BIT:
	776	+ dst.cp++ = src.cp++;
	777	+ break;
	778	+ case FLASH_CFI_16BIT:
	779	+ dst.wp++ = src.wp++;
	780	+ break;
	781	+ case FLASH_CFI_32BIT:
	782	+ dst.lp++ = src.lp++;
	783	+ break;
	784	+ default:
	785	+ return ERR_INVAL;
	786	+ break;
	787	+ }
	788	+ }
	789	+ flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
	790	+ retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
	791	+ "buffer write");
	792	+ }
	793	+ flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
	794	+ return retcode;
	795	+}
	796	+#endif /* CFG_USE_FLASH_BUFFER_WRITE */

board/esd/pmc405/u-boot.lds

Diff comments View file @ 071d897

	1	+/*
	2	+ * (C) Copyright 2000, 2001
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(powerpc)
	25	+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
	26	+/* Do we need any of these for elf?
	27	+ __DYNAMIC = 0; */
	28	+SECTIONS
	29	+{
	30	+ .resetvec 0xFFFFFFFC :
	31	+ {
	32	+ *(.resetvec)
	33	+ } = 0xffff
	34	+
	35	+ /* Read-only sections, merged into text segment: */
	36	+ . = + SIZEOF_HEADERS;
	37	+ .interp : { *(.interp) }
	38	+ .hash : { *(.hash) }
	39	+ .dynsym : { *(.dynsym) }
	40	+ .dynstr : { *(.dynstr) }
	41	+ .rel.text : { *(.rel.text) }
	42	+ .rela.text : { *(.rela.text) }
	43	+ .rel.data : { *(.rel.data) }
	44	+ .rela.data : { *(.rela.data) }
	45	+ .rel.rodata : { *(.rel.rodata) }
	46	+ .rela.rodata : { *(.rela.rodata) }
	47	+ .rel.got : { *(.rel.got) }
	48	+ .rela.got : { *(.rela.got) }
	49	+ .rel.ctors : { *(.rel.ctors) }
	50	+ .rela.ctors : { *(.rela.ctors) }
	51	+ .rel.dtors : { *(.rel.dtors) }
	52	+ .rela.dtors : { *(.rela.dtors) }
	53	+ .rel.bss : { *(.rel.bss) }
	54	+ .rela.bss : { *(.rela.bss) }
	55	+ .rel.plt : { *(.rel.plt) }
	56	+ .rela.plt : { *(.rela.plt) }
	57	+ .init : { *(.init) }
	58	+ .plt : { *(.plt) }
	59	+ .text :
	60	+ {
	61	+ /* WARNING - the following is hand-optimized to fit within */
	62	+ /* the sector layout of our flash chips! XXX FIXME XXX */
	63	+
	64	+ cpu/ppc4xx/start.o (.text)
	65	+ cpu/ppc4xx/traps.o (.text)
	66	+ cpu/ppc4xx/interrupts.o (.text)
	67	+ cpu/ppc4xx/serial.o (.text)
	68	+ cpu/ppc4xx/cpu_init.o (.text)
	69	+ cpu/ppc4xx/speed.o (.text)
	70	+ cpu/ppc4xx/405gp_enet.o (.text)
	71	+ common/dlmalloc.o (.text)
	72	+ lib_generic/crc32.o (.text)
	73	+ lib_ppc/extable.o (.text)
	74	+ lib_generic/zlib.o (.text)
	75	+
	76	+/* . = env_offset;*/
	77	+/* common/environment.o(.text)*/
	78	+
	79	+ *(.text)
	80	+ *(.fixup)
	81	+ *(.got1)
	82	+ }
	83	+ _etext = .;
	84	+ PROVIDE (etext = .);
	85	+ .rodata :
	86	+ {
	87	+ *(.rodata)
	88	+ *(.rodata1)
	89	+ }
	90	+ .fini : { *(.fini) } =0
	91	+ .ctors : { *(.ctors) }
	92	+ .dtors : { *(.dtors) }
	93	+
	94	+ /* Read-write section, merged into data segment: */
	95	+ . = (. + 0x00FF) & 0xFFFFFF00;
	96	+ _erotext = .;
	97	+ PROVIDE (erotext = .);
	98	+ .reloc :
	99	+ {
	100	+ *(.got)
	101	+ _GOT2_TABLE_ = .;
	102	+ *(.got2)
	103	+ _FIXUP_TABLE_ = .;
	104	+ *(.fixup)
	105	+ }
	106	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
	107	+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
	108	+
	109	+ .data :
	110	+ {
	111	+ *(.data)
	112	+ *(.data1)
	113	+ *(.sdata)
	114	+ *(.sdata2)
	115	+ *(.dynamic)
	116	+ CONSTRUCTORS
	117	+ }
	118	+ _edata = .;
	119	+ PROVIDE (edata = .);
	120	+
	121	+ __start___ex_table = .;
	122	+ __ex_table : { *(__ex_table) }
	123	+ __stop___ex_table = .;
	124	+
	125	+ . = ALIGN(256);
	126	+ __init_begin = .;
	127	+ .text.init : { *(.text.init) }
	128	+ .data.init : { *(.data.init) }
	129	+ . = ALIGN(256);
	130	+ __init_end = .;
	131	+
	132	+ __bss_start = .;
	133	+ .bss :
	134	+ {
	135	+ (.sbss) (.scommon)
	136	+ *(.dynbss)
	137	+ *(.bss)
	138	+ *(COMMON)
	139	+ }
	140	+ _end = . ;
	141	+ PROVIDE (end = .);
	142	+}

include/configs/PMC405.h

Diff comments View file @ 071d897

	1	+/*
	2	+ * (C) Copyright 2001-2003
	3	+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+/*
	25	+ * board/config.h - configuration options, board specific
	26	+ */
	27	+
	28	+#ifndef __CONFIG_H
	29	+#define __CONFIG_H
	30	+
	31	+/*
	32	+ * High Level Configuration Options
	33	+ * (easy to change)
	34	+ */
	35	+
	36	+#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	37	+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	38	+#define CONFIG_PMC405 1 /* ...on a PMC405 board */
	39	+
	40	+#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
	41	+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	42	+
	43	+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	44	+
	45	+#define CONFIG_BAUDRATE 9600
	46	+#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	47	+
	48	+#undef CONFIG_BOOTARGS
	49	+#define CONFIG_RAMBOOTCOMMAND \
	50	+ "setenv bootargs root=/dev/ram rw nfsroot=$(serverip):$(rootpath) " \
	51	+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	52	+ "bootm ffc00000 ffca0000"
	53	+#define CONFIG_NFSBOOTCOMMAND \
	54	+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	55	+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
	56	+ "bootm ffc00000"
	57	+#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	58	+
	59	+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	60	+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	61	+
	62	+#define CONFIG_MII 1 /* MII PHY management */
	63	+#define CONFIG_PHY_ADDR 0 /* PHY address */
	64	+
	65	+#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \| \
	66	+ CFG_CMD_PCI \| \
	67	+ CFG_CMD_IRQ \| \
	68	+ CFG_CMD_ELF \| \
	69	+ CFG_CMD_DATE \| \
	70	+ CFG_CMD_JFFS2 \| \
	71	+ CFG_CMD_MII \| \
	72	+ CFG_CMD_I2C \| \
	73	+ CFG_CMD_EEPROM )
	74	+
	75	+#define CONFIG_MAC_PARTITION
	76	+#define CONFIG_DOS_PARTITION
	77	+
	78	+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	79	+#include <cmd_confdefs.h>
	80	+
	81	+#undef CONFIG_WATCHDOG /* watchdog disabled */
	82	+
	83	+#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
	84	+#define CFG_RTC_REG_BASE_ADDR 0xF0000300 /* RTC Base Address */
	85	+
	86	+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	87	+
	88	+/*
	89	+ * Miscellaneous configurable options
	90	+ */
	91	+#define CFG_LONGHELP /* undef to save memory */
	92	+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	93	+
	94	+#undef CFG_HUSH_PARSER /* use "hush" command parser */
	95	+#ifdef CFG_HUSH_PARSER
	96	+#define CFG_PROMPT_HUSH_PS2 "> "
	97	+#endif
	98	+
	99	+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	100	+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	101	+#else
	102	+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	103	+#endif
	104	+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	105	+#define CFG_MAXARGS 16 /* max number of command args */
	106	+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	107	+
	108	+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
	109	+
	110	+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
	111	+
	112	+#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	113	+#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	114	+
	115	+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	116	+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	117	+#define CFG_BASE_BAUD 691200
	118	+
	119	+/* The following table includes the supported baudrates */
	120	+#define CFG_BAUDRATE_TABLE \
	121	+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	122	+ 57600, 115200, 230400, 460800, 921600 }
	123	+
	124	+#define CFG_LOAD_ADDR 0x100000 /* default load address */
	125	+#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	126	+
	127	+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	128	+
	129	+#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	130	+
	131	+/*-----------------------------------------------------------------------
	132	+ * PCI stuff
	133	+ *-----------------------------------------------------------------------
	134	+ */
	135	+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	136	+#define PCI_HOST_FORCE 1 /* configure as pci host */
	137	+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	138	+
	139	+#define CONFIG_PCI /* include pci support */
	140	+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	141	+#define CONFIG_PCI_PNP /* do pci plug-and-play */
	142	+ /* resource configuration */
	143	+
	144	+#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	145	+
	146	+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	147	+#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
	148	+#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	149	+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	150	+#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	151	+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	152	+#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	153	+#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	154	+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
	155	+
	156	+/*-----------------------------------------------------------------------
	157	+ * Start addresses for the final memory configuration
	158	+ * (Set up by the startup code)
	159	+ * Please note that CFG_SDRAM_BASE _must_ start at 0
	160	+ */
	161	+#define CFG_SDRAM_BASE 0x00000000
	162	+#define CFG_MONITOR_BASE 0xFFFC0000
	163	+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	164	+#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	165	+
	166	+/*
	167	+ * For booting Linux, the board info and command line data
	168	+ * have to be in the first 8 MB of memory, since this is
	169	+ * the maximum mapped by the Linux kernel during initialization.
	170	+ */
	171	+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	172	+
	173	+/*-----------------------------------------------------------------------
	174	+ * FLASH organization
	175	+ */
	176	+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
	177	+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	178	+#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	179	+#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
	180	+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	181	+#define CFG_FLASH_BASE 0xFE000000
	182	+#define CFG_FLASH_INCREMENT 0x01000000
	183	+
	184	+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	185	+
	186	+#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
	187	+#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
	188	+
	189	+/*-----------------------------------------------------------------------
	190	+ * Environment Variable setup
	191	+ */
	192	+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	193	+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
	194	+#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
	195	+ /* total size of a CAT24WC16 is 2048 bytes */
	196	+
	197	+#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
	198	+#define CFG_NVRAM_SIZE 242 /* NVRAM size */
	199	+
	200	+/*-----------------------------------------------------------------------
	201	+ * I2C EEPROM (CAT24WC16) for environment
	202	+ */
	203	+#define CONFIG_HARD_I2C /* I2c with hardware support */
	204	+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	205	+#define CFG_I2C_SLAVE 0x7F
	206	+
	207	+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
	208	+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
	209	+/* mask of address bits that overflow into the "EEPROM chip address" */
	210	+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	211	+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	212	+ /* 16 byte page write mode using*/
	213	+ /* last 4 bits of the address */
	214	+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	215	+#define CFG_EEPROM_PAGE_WRITE_ENABLE
	216	+
	217	+/*-----------------------------------------------------------------------
	218	+ * Cache Configuration
	219	+ */
	220	+#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
	221	+ /* have only 8kB, 16kB is save here */
	222	+#define CFG_CACHELINE_SIZE 32 /* ... */
	223	+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	224	+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	225	+#endif
	226	+
	227	+/*-----------------------------------------------------------------------
	228	+ * External Bus Controller (EBC) Setup
	229	+ */
	230	+#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
	231	+#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
	232	+#define CAN_BA 0xF0000000 /* CAN Base Address */
	233	+#define RTC_BA 0xF0000500 /* RTC Base Address */
	234	+#define CF_BA 0xF0100000 /* CompactFlash Base Address */
	235	+
	236	+/* Memory Bank 0 (Flash Bank 0) initialization */
	237	+#define CFG_EBC_PB0AP 0x92015480
	238	+#define CFG_EBC_PB0CR FLASH0_BA \| 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
	239	+
	240	+/* Memory Bank 1 (Flash Bank 1) initialization */
	241	+#define CFG_EBC_PB1AP 0x92015480
	242	+#define CFG_EBC_PB1CR FLASH1_BA \| 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
	243	+
	244	+/* Memory Bank 2 (CAN0, 1, RTC) initialization */
	245	+#define CFG_EBC_PB2AP 0x03000040 /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0 */
	246	+#define CFG_EBC_PB2CR CAN_BA \| 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
	247	+
	248	+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
	249	+#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
	250	+#define CFG_EBC_PB3CR CF_BA \| 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
	251	+
	252	+/*-----------------------------------------------------------------------
	253	+ * Definitions for initial stack pointer and data area (in data cache)
	254	+ */
	255	+
	256	+/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
	257	+#define CFG_TEMP_STACK_OCM 1
	258	+
	259	+/* On Chip Memory location */
	260	+#define CFG_OCM_DATA_ADDR 0xF8000000
	261	+#define CFG_OCM_DATA_SIZE 0x1000
	262	+
	263	+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	264	+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	265	+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	266	+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	267	+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	268	+
	269	+/*
	270	+ * Internal Definitions
	271	+ *
	272	+ * Boot Flags
	273	+ */
	274	+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	275	+#define BOOTFLAG_WARM 0x02 /* Software reboot */
	276	+
	277	+#endif /* __CONFIG_H */