Eric Lee / smarc-uboot

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Commit 07ef0fab23204684d82f27baf721a72b247f30c5

Authored by Haibo Chen
1 parent a28603934e
Exists in smarc-imx_v2017.03_o8.1.0_1.3.0_8m and in 1 other branch smarc-imx_v2017.03_4.9.88_2.0.0_ga

MLK-17586-3 i.MX7ULP: change USDHC clock rate 

Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.

Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Showing 4 changed files with 66 additions and 7 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx7ulp/clock.c
Diff comments   View file @ 07ef0fa
... ... @@ -150,8 +150,8 @@
150 150 /*Disable the clock before configure it */
151 151 pcc_clock_enable(PER_CLK_USDHC0, false);
152 152  
153   - /* 158MHz / 1 = 158MHz */
154   - pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
  153 + /* 352.8MHz / 1 = 352.8MHz */
  154 + pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK);
155 155 pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
156 156 pcc_clock_enable(PER_CLK_USDHC0, true);
157 157 break;
... ... @@ -159,9 +159,9 @@
159 159 /*Disable the clock before configure it */
160 160 pcc_clock_enable(PER_CLK_USDHC1, false);
161 161  
162   - /* 158MHz / 1 = 158MHz */
163   - pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
164   - pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
  162 + /* 352.8MHz / 2 = 176.4MHz */
  163 + pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK);
  164 + pcc_clock_div_config(PER_CLK_USDHC1, false, 2);
165 165 pcc_clock_enable(PER_CLK_USDHC1, true);
166 166 break;
167 167 default:
... ... @@ -304,8 +304,8 @@
304 304  
305 305 scg_a7_init_core_clk();
306 306  
307   - /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */
308   - scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
  307 + /* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */
  308 + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27);
309 309 scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28);
310 310 scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
311 311  
arch/arm/cpu/armv7/mx7ulp/scg.c
Diff comments   View file @ 07ef0fa
... ... @@ -714,6 +714,61 @@
714 714 return 0;
715 715 }
716 716  
  717 +int scg_disable_pll_pfd(enum scg_clk clk)
  718 +{
  719 + u32 reg;
  720 + u32 gate;
  721 + u32 addr;
  722 +
  723 + switch (clk) {
  724 + case SCG_SPLL_PFD0_CLK:
  725 + case SCG_APLL_PFD0_CLK:
  726 + gate = SCG_PLL_PFD0_GATE_MASK;
  727 +
  728 + if (clk == SCG_SPLL_PFD0_CLK)
  729 + addr = (u32)(&scg1_regs->spllpfd);
  730 + else
  731 + addr = (u32)(&scg1_regs->apllpfd);
  732 + break;
  733 + case SCG_SPLL_PFD1_CLK:
  734 + case SCG_APLL_PFD1_CLK:
  735 + gate = SCG_PLL_PFD1_GATE_MASK;
  736 +
  737 + if (clk == SCG_SPLL_PFD1_CLK)
  738 + addr = (u32)(&scg1_regs->spllpfd);
  739 + else
  740 + addr = (u32)(&scg1_regs->apllpfd);
  741 + break;
  742 + case SCG_SPLL_PFD2_CLK:
  743 + case SCG_APLL_PFD2_CLK:
  744 + gate = SCG_PLL_PFD2_GATE_MASK;
  745 +
  746 + if (clk == SCG_SPLL_PFD2_CLK)
  747 + addr = (u32)(&scg1_regs->spllpfd);
  748 + else
  749 + addr = (u32)(&scg1_regs->apllpfd);
  750 + break;
  751 + case SCG_SPLL_PFD3_CLK:
  752 + case SCG_APLL_PFD3_CLK:
  753 + gate = SCG_PLL_PFD3_GATE_MASK;
  754 +
  755 + if (clk == SCG_SPLL_PFD3_CLK)
  756 + addr = (u32)(&scg1_regs->spllpfd);
  757 + else
  758 + addr = (u32)(&scg1_regs->apllpfd);
  759 + break;
  760 + default:
  761 + return -EINVAL;
  762 + }
  763 +
  764 + /* Gate the PFD */
  765 + reg = readl(addr);
  766 + reg |= gate;
  767 + writel(reg, addr);
  768 +
  769 + return 0;
  770 +}
  771 +
717 772 #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2)
718 773 int scg_enable_usb_pll(bool usb_control)
719 774 {
arch/arm/cpu/armv7/mx7ulp/soc.c
Diff comments   View file @ 07ef0fa
... ... @@ -288,6 +288,9 @@
288 288 #if defined(CONFIG_VIDEO_MXS)
289 289 lcdif_power_down();
290 290 #endif
  291 + scg_disable_pll_pfd(SCG_APLL_PFD1_CLK);
  292 + scg_disable_pll_pfd(SCG_APLL_PFD2_CLK);
  293 + scg_disable_pll_pfd(SCG_APLL_PFD3_CLK);
291 294 }
292 295  
293 296 #ifdef CONFIG_ENV_IS_IN_MMC
arch/arm/include/asm/arch-mx7ulp/scg.h
Diff comments   View file @ 07ef0fa
... ... @@ -326,6 +326,7 @@
326 326  
327 327 u32 scg_clk_get_rate(enum scg_clk clk);
328 328 int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
  329 +int scg_disable_pll_pfd(enum scg_clk clk);
329 330 int scg_enable_usb_pll(bool usb_control);
330 331 u32 decode_pll(enum pll_clocks pll);
331 332