phy: sun4i-usb: Use CLK and RESET support

Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>

phy: sun4i-usb: Use CLK and RESET support
Now clock and reset drivers are available for respective SoC's so use clk and reset ops on phy driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Marek Vasut <marex@denx.de>
Jagan Teki
1 parent e236ff0a51
Showing 1 changed file with 57 additions and 20 deletions Side-by-side Diff
drivers/phy/allwinner/phy-sun4i-usb.c
@@ -11,10 +11,12 @@
  */
  
 #include <common.h>
+#include <clk.h>
 #include <dm.h>
 #include <dm/device.h>
 #include <generic-phy.h>
 #include <phy-sun4i-usb.h>
+#include <reset.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
@@ -80,6 +82,7 @@
 	enum sun4i_usb_phy_type type;
 	u32 disc_thresh;
 	u8 phyctl_offset;
+	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
 };
  
  
  
@@ -88,30 +91,21 @@
 	const char *gpio_vbus;
 	const char *gpio_vbus_det;
 	const char *gpio_id_det;
-	int rst_mask;
 } phy_info[] = {
 	{
 		.gpio_vbus = CONFIG_USB0_VBUS_PIN,
 		.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
 		.gpio_id_det = CONFIG_USB0_ID_DET,
-		.rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB1_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-		.rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
 	},
 	{
 		.gpio_vbus = CONFIG_USB2_VBUS_PIN,
 		.gpio_vbus_det = NULL,
 		.gpio_id_det = NULL,
-#ifdef CONFIG_MACH_SUN8I_A83T
-		.rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
-			     CCM_USB_CTRL_12M_CLK),
-#else
-		.rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
-#endif
 	},
 	{
 		.gpio_vbus = CONFIG_USB3_VBUS_PIN,
  
@@ -126,13 +120,13 @@
 	int gpio_vbus;
 	int gpio_vbus_det;
 	int gpio_id_det;
-	int rst_mask;
+	struct clk clocks;
+	struct reset_ctl resets;
 	int id;
 };
  
 struct sun4i_usb_phy_data {
 	void __iomem *base;
-	struct sunxi_ccm_reg *ccm;
 	const struct sun4i_usb_phy_cfg *cfg;
 	struct sun4i_usb_phy_plat *usb_phy;
 };
  
  
@@ -266,9 +260,20 @@
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
 	u32 val;
+	int ret;
  
-	setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_enable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
  
+	ret = reset_deassert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
+
 	if (data->cfg->type == sun8i_a83t_phy) {
 		if (phy->id == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
@@ -308,6 +313,7 @@
 {
 	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
 	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
+	int ret;
  
 	if (phy->id == 0) {
 		if (data->cfg->type == sun8i_a83t_phy) {
  
@@ -320,8 +326,18 @@
  
 	sun4i_usb_phy_passby(phy, false);
  
-	clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
+	ret = clk_disable(&usb_phy->clocks);
+	if (ret) {
+		dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
+		return ret;
+	}
  
+	ret = reset_assert(&usb_phy->resets);
+	if (ret) {
+		dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
+		return ret;
+	}
+
 	return 0;
 }
  
@@ -407,10 +423,6 @@
 	if (IS_ERR(data->base))
 		return PTR_ERR(data->base);
  
-	data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-	if (IS_ERR(data->ccm))
-		return PTR_ERR(data->ccm);
-
 	data->usb_phy = plat;
 	for (i = 0; i < data->cfg->num_phys; i++) {
 		struct sun4i_usb_phy_plat *phy = &plat[i];
@@ -448,6 +460,24 @@
 			sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
 		}
  
+		if (data->cfg->dedicated_clocks)
+			snprintf(name, sizeof(name), "usb%d_phy", i);
+		else
+			strlcpy(name, "usb_phy", sizeof(name));
+
+		ret = clk_get_by_name(dev, name, &phy->clocks);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
+			return ret;
+		}
+
+		snprintf(name, sizeof(name), "usb%d_reset", i);
+		ret = reset_get_by_name(dev, name, &phy->resets);
+		if (ret) {
+			dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
+			return ret;
+		}
+
 		if (i || data->cfg->phy0_dual_route) {
 			snprintf(name, sizeof(name), "pmu%d", i);
 			phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
@@ -456,9 +486,6 @@
 		}
  
 		phy->id = i;
-		phy->rst_mask = info->rst_mask;
-		if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
-			phy->rst_mask = (BIT(3) | BIT(11));
 	};
  
 	debug("Allwinner Sun4I USB PHY driver loaded\n");
@@ -470,6 +497,7 @@
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
  
@@ -478,6 +506,7 @@
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
  
@@ -486,6 +515,7 @@
 	.type = sun6i_a31_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
  
@@ -494,6 +524,7 @@
 	.type = sun4i_a10_phy,
 	.disc_thresh = 2,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = false,
 	.enable_pmu_unk1 = false,
 };
  
@@ -502,6 +533,7 @@
 	.type = sun4i_a10_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A10,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
  
@@ -510,6 +542,7 @@
 	.type = sun8i_a33_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = false,
 };
  
@@ -517,6 +550,7 @@
 	.num_phys = 3,
 	.type = sun8i_a83t_phy,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 };
  
 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
@@ -524,6 +558,7 @@
 	.type = sun8i_h3_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };
@@ -533,6 +568,7 @@
 	.type = sun8i_v3s_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };
@@ -542,6 +578,7 @@
 	.type = sun50i_a64_phy,
 	.disc_thresh = 3,
 	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
 	.enable_pmu_unk1 = true,
 	.phy0_dual_route = true,
 };
...	...	@@ -11,10 +11,12 @@
11	11	*/
12	12
13	13	#include <common.h>
	14	+#include <clk.h>
14	15	#include <dm.h>
15	16	#include <dm/device.h>
16	17	#include <generic-phy.h>
17	18	#include <phy-sun4i-usb.h>
	19	+#include <reset.h>
18	20	#include <asm/gpio.h>
19	21	#include <asm/io.h>
20	22	#include <asm/arch/clock.h>
...	...	@@ -80,6 +82,7 @@
80	82	enum sun4i_usb_phy_type type;
81	83	u32 disc_thresh;
82	84	u8 phyctl_offset;
	85	+ bool dedicated_clocks;
83	86	bool enable_pmu_unk1;
84	87	bool phy0_dual_route;
85	88	};
86	89
87	90
88	91
...	...	@@ -88,30 +91,21 @@
88	91	const char *gpio_vbus;
89	92	const char *gpio_vbus_det;
90	93	const char *gpio_id_det;
91		- int rst_mask;
92	94	} phy_info[] = {
93	95	{
94	96	.gpio_vbus = CONFIG_USB0_VBUS_PIN,
95	97	.gpio_vbus_det = CONFIG_USB0_VBUS_DET,
96	98	.gpio_id_det = CONFIG_USB0_ID_DET,
97		- .rst_mask = (CCM_USB_CTRL_PHY0_RST \| CCM_USB_CTRL_PHY0_CLK),
98	99	},
99	100	{
100	101	.gpio_vbus = CONFIG_USB1_VBUS_PIN,
101	102	.gpio_vbus_det = NULL,
102	103	.gpio_id_det = NULL,
103		- .rst_mask = (CCM_USB_CTRL_PHY1_RST \| CCM_USB_CTRL_PHY1_CLK),
104	104	},
105	105	{
106	106	.gpio_vbus = CONFIG_USB2_VBUS_PIN,
107	107	.gpio_vbus_det = NULL,
108	108	.gpio_id_det = NULL,
109		-#ifdef CONFIG_MACH_SUN8I_A83T
110		- .rst_mask = (CCM_USB_CTRL_HSIC_RST \| CCM_USB_CTRL_HSIC_CLK \|
111		- CCM_USB_CTRL_12M_CLK),
112		-#else
113		- .rst_mask = (CCM_USB_CTRL_PHY2_RST \| CCM_USB_CTRL_PHY2_CLK),
114		-#endif
115	109	},
116	110	{
117	111	.gpio_vbus = CONFIG_USB3_VBUS_PIN,
118	112
...	...	@@ -126,13 +120,13 @@
126	120	int gpio_vbus;
127	121	int gpio_vbus_det;
128	122	int gpio_id_det;
129		- int rst_mask;
	123	+ struct clk clocks;
	124	+ struct reset_ctl resets;
130	125	int id;
131	126	};
132	127
133	128	struct sun4i_usb_phy_data {
134	129	void __iomem *base;
135		- struct sunxi_ccm_reg *ccm;
136	130	const struct sun4i_usb_phy_cfg *cfg;
137	131	struct sun4i_usb_phy_plat *usb_phy;
138	132	};
139	133
140	134
...	...	@@ -266,9 +260,20 @@
266	260	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
267	261	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
268	262	u32 val;
	263	+ int ret;
269	264
270		- setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
	265	+ ret = clk_enable(&usb_phy->clocks);
	266	+ if (ret) {
	267	+ dev_err(dev, "failed to enable usb_%ldphy clock\n", phy->id);
	268	+ return ret;
	269	+ }
271	270
	271	+ ret = reset_deassert(&usb_phy->resets);
	272	+ if (ret) {
	273	+ dev_err(dev, "failed to deassert usb_%ldreset reset\n", phy->id);
	274	+ return ret;
	275	+ }
	276	+
272	277	if (data->cfg->type == sun8i_a83t_phy) {
273	278	if (phy->id == 0) {
274	279	val = readl(data->base + data->cfg->phyctl_offset);
...	...	@@ -308,6 +313,7 @@
308	313	{
309	314	struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
310	315	struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
	316	+ int ret;
311	317
312	318	if (phy->id == 0) {
313	319	if (data->cfg->type == sun8i_a83t_phy) {
314	320
...	...	@@ -320,8 +326,18 @@
320	326
321	327	sun4i_usb_phy_passby(phy, false);
322	328
323		- clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
	329	+ ret = clk_disable(&usb_phy->clocks);
	330	+ if (ret) {
	331	+ dev_err(dev, "failed to disable usb_%ldphy clock\n", phy->id);
	332	+ return ret;
	333	+ }
324	334
	335	+ ret = reset_assert(&usb_phy->resets);
	336	+ if (ret) {
	337	+ dev_err(dev, "failed to assert usb_%ldreset reset\n", phy->id);
	338	+ return ret;
	339	+ }
	340	+
325	341	return 0;
326	342	}
327	343
...	...	@@ -407,10 +423,6 @@
407	423	if (IS_ERR(data->base))
408	424	return PTR_ERR(data->base);
409	425
410		- data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
411		- if (IS_ERR(data->ccm))
412		- return PTR_ERR(data->ccm);
413		-
414	426	data->usb_phy = plat;
415	427	for (i = 0; i < data->cfg->num_phys; i++) {
416	428	struct sun4i_usb_phy_plat *phy = &plat[i];
...	...	@@ -448,6 +460,24 @@
448	460	sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
449	461	}
450	462
	463	+ if (data->cfg->dedicated_clocks)
	464	+ snprintf(name, sizeof(name), "usb%d_phy", i);
	465	+ else
	466	+ strlcpy(name, "usb_phy", sizeof(name));
	467	+
	468	+ ret = clk_get_by_name(dev, name, &phy->clocks);
	469	+ if (ret) {
	470	+ dev_err(dev, "failed to get usb%d_phy clock phandle\n", i);
	471	+ return ret;
	472	+ }
	473	+
	474	+ snprintf(name, sizeof(name), "usb%d_reset", i);
	475	+ ret = reset_get_by_name(dev, name, &phy->resets);
	476	+ if (ret) {
	477	+ dev_err(dev, "failed to get usb%d_reset reset phandle\n", i);
	478	+ return ret;
	479	+ }
	480	+
451	481	if (i \|\| data->cfg->phy0_dual_route) {
452	482	snprintf(name, sizeof(name), "pmu%d", i);
453	483	phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
...	...	@@ -456,9 +486,6 @@
456	486	}
457	487
458	488	phy->id = i;
459		- phy->rst_mask = info->rst_mask;
460		- if ((data->cfg->type == sun8i_h3_phy) && (phy->id == 3))
461		- phy->rst_mask = (BIT(3) \| BIT(11));
462	489	};
463	490
464	491	debug("Allwinner Sun4I USB PHY driver loaded\n");
...	...	@@ -470,6 +497,7 @@
470	497	.type = sun4i_a10_phy,
471	498	.disc_thresh = 3,
472	499	.phyctl_offset = REG_PHYCTL_A10,
	500	+ .dedicated_clocks = false,
473	501	.enable_pmu_unk1 = false,
474	502	};
475	503
...	...	@@ -478,6 +506,7 @@
478	506	.type = sun4i_a10_phy,
479	507	.disc_thresh = 2,
480	508	.phyctl_offset = REG_PHYCTL_A10,
	509	+ .dedicated_clocks = false,
481	510	.enable_pmu_unk1 = false,
482	511	};
483	512
...	...	@@ -486,6 +515,7 @@
486	515	.type = sun6i_a31_phy,
487	516	.disc_thresh = 3,
488	517	.phyctl_offset = REG_PHYCTL_A10,
	518	+ .dedicated_clocks = true,
489	519	.enable_pmu_unk1 = false,
490	520	};
491	521
...	...	@@ -494,6 +524,7 @@
494	524	.type = sun4i_a10_phy,
495	525	.disc_thresh = 2,
496	526	.phyctl_offset = REG_PHYCTL_A10,
	527	+ .dedicated_clocks = false,
497	528	.enable_pmu_unk1 = false,
498	529	};
499	530
...	...	@@ -502,6 +533,7 @@
502	533	.type = sun4i_a10_phy,
503	534	.disc_thresh = 3,
504	535	.phyctl_offset = REG_PHYCTL_A10,
	536	+ .dedicated_clocks = true,
505	537	.enable_pmu_unk1 = false,
506	538	};
507	539
...	...	@@ -510,6 +542,7 @@
510	542	.type = sun8i_a33_phy,
511	543	.disc_thresh = 3,
512	544	.phyctl_offset = REG_PHYCTL_A33,
	545	+ .dedicated_clocks = true,
513	546	.enable_pmu_unk1 = false,
514	547	};
515	548
...	...	@@ -517,6 +550,7 @@
517	550	.num_phys = 3,
518	551	.type = sun8i_a83t_phy,
519	552	.phyctl_offset = REG_PHYCTL_A33,
	553	+ .dedicated_clocks = true,
520	554	};
521	555
522	556	static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
...	...	@@ -524,6 +558,7 @@
524	558	.type = sun8i_h3_phy,
525	559	.disc_thresh = 3,
526	560	.phyctl_offset = REG_PHYCTL_A33,
	561	+ .dedicated_clocks = true,
527	562	.enable_pmu_unk1 = true,
528	563	.phy0_dual_route = true,
529	564	};
...	...	@@ -533,6 +568,7 @@
533	568	.type = sun8i_v3s_phy,
534	569	.disc_thresh = 3,
535	570	.phyctl_offset = REG_PHYCTL_A33,
	571	+ .dedicated_clocks = true,
536	572	.enable_pmu_unk1 = true,
537	573	.phy0_dual_route = true,
538	574	};
...	...	@@ -542,6 +578,7 @@
542	578	.type = sun50i_a64_phy,
543	579	.disc_thresh = 3,
544	580	.phyctl_offset = REG_PHYCTL_A33,
	581	+ .dedicated_clocks = true,
545	582	.enable_pmu_unk1 = true,
546	583	.phy0_dual_route = true,
547	584	};