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Commit 08c5fabe181d663eec0feba5ecd02c0b78934a52

Authored by Nobuhiro Iwamatsu
Committed by Nobuhiro Iwamatsu
1 parent 8155efbd7a
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

sh: SH7763 SCIF support 

SH7763 has 3 SCIF channels. SCIF0 and 1 are same register constitution,
but only SCIF2 is different. This patch work all SCIF channel.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 1 changed file with 73 additions and 55 deletions Side-by-side Diff

drivers/serial/serial_sh.c
Diff comments   View file @ 08c5fab
... ... @@ -26,6 +26,8 @@
26 26 #define SCIF_BASE SCIF0_BASE
27 27 #elif defined (CONFIG_CONS_SCIF1)
28 28 #define SCIF_BASE SCIF1_BASE
  29 +#elif defined (CONFIG_CONS_SCIF2)
  30 +#define SCIF_BASE SCIF2_BASE
29 31 #else
30 32 #error "Default SCIF doesn't set....."
31 33 #endif
32 34  
33 35  
... ... @@ -36,17 +38,17 @@
36 38 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
37 39 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
38 40 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
39   -#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
40   -# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
  41 +#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */
  42 +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */
41 43 # define SCFTDR (vu_char *)(SCIF_BASE + 0x20)
42 44 # define SCFRDR (vu_char *)(SCIF_BASE + 0x24)
43 45 #else
44 46 # define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
45   -# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
  47 +# define SCFSR (vu_short *)(SCIF_BASE + 0x10)
46 48 # define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
47 49 #endif
48 50  
49   -#if defined(CONFIG_CPU_SH7780) || \
  51 +#if defined(CONFIG_CPU_SH7780) || \
50 52 defined(CONFIG_CPU_SH7785)
51 53 # define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
52 54 # define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
53 55  
54 56  
55 57  
56 58  
... ... @@ -54,20 +56,34 @@
54 56 # define SCRER (vu_short *)(SCIF_BASE + 0x2C)
55 57 # define LSR_ORER 1
56 58 # define FIFOLEVEL_MASK 0xFF
  59 +#elif defined(CONFIG_CPU_SH7763)
  60 +# if defined (CONFIG_CONS_SCIF2)
  61 +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
  62 +# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
  63 +# define LSR_ORER 1
  64 +# define FIFOLEVEL_MASK 0x1F
  65 +# else
  66 +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
  67 +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
  68 +# define SCLSR (vu_short *)(SCIF_BASE + 0x28)
  69 +# define SCRER (vu_short *)(SCIF_BASE + 0x2C)
  70 +# define LSR_ORER 1
  71 +# define FIFOLEVEL_MASK 0xFF
  72 +# endif
57 73 #elif defined(CONFIG_CPU_SH7750) || \
58 74 defined(CONFIG_CPU_SH7751) || \
59 75 defined(CONFIG_CPU_SH7722)
60 76 # define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
61   -# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
  77 +# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
62 78 # define LSR_ORER 1
63 79 # define FIFOLEVEL_MASK 0x1F
64 80 #elif defined(CONFIG_CPU_SH7720)
65   -# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
  81 +# define SCLSR (vu_short *)(SCIF_BASE + 0x24)
66 82 # define LSR_ORER 0x0200
67 83 # define FIFOLEVEL_MASK 0x1F
68   -#elif defined(CONFIG_CPU_SH7710)
  84 +#elif defined(CONFIG_CPU_SH7710) || \
69 85 defined(CONFIG_CPU_SH7712)
70   -# define SCLSR SCFSR /* SCSSR */
  86 +# define SCLSR SCFSR /* SCSSR */
71 87 # define LSR_ORER 1
72 88 # define FIFOLEVEL_MASK 0x1F
73 89 #endif
74 90  
75 91  
76 92  
77 93  
78 94  
79 95  
... ... @@ -75,35 +91,35 @@
75 91 /* SCBRR register value setting */
76 92 #if defined(CONFIG_CPU_SH7720)
77 93 # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
78   -#else /* Generic SuperH */
  94 +#else /* Generic SuperH */
79 95 # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
80 96 #endif
81 97  
82   -#define SCR_RE (1 << 4)
83   -#define SCR_TE (1 << 5)
84   -#define FCR_RFRST (1 << 1) /* RFCL */
85   -#define FCR_TFRST (1 << 2) /* TFCL */
86   -#define FSR_DR (1 << 0)
87   -#define FSR_RDF (1 << 1)
88   -#define FSR_FER (1 << 3)
89   -#define FSR_BRK (1 << 4)
90   -#define FSR_FER (1 << 3)
91   -#define FSR_TEND (1 << 6)
92   -#define FSR_ER (1 << 7)
  98 +#define SCR_RE (1 << 4)
  99 +#define SCR_TE (1 << 5)
  100 +#define FCR_RFRST (1 << 1) /* RFCL */
  101 +#define FCR_TFRST (1 << 2) /* TFCL */
  102 +#define FSR_DR (1 << 0)
  103 +#define FSR_RDF (1 << 1)
  104 +#define FSR_FER (1 << 3)
  105 +#define FSR_BRK (1 << 4)
  106 +#define FSR_FER (1 << 3)
  107 +#define FSR_TEND (1 << 6)
  108 +#define FSR_ER (1 << 7)
93 109  
94 110 /*----------------------------------------------------------------------*/
95 111  
96   -void serial_setbrg (void)
  112 +void serial_setbrg(void)
97 113 {
98 114 DECLARE_GLOBAL_DATA_PTR;
99   - *SCBRR = SCBRR_VALUE(gd->baudrate,CONFIG_SYS_CLK_FREQ);
  115 + *SCBRR = SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ);
100 116 }
101 117  
102   -int serial_init (void)
  118 +int serial_init(void)
103 119 {
104 120 *SCSCR = (SCR_RE | SCR_TE);
105   - *SCSMR = 0 ;
106 121 *SCSMR = 0;
  122 + *SCSMR = 0;
107 123 *SCFCR = (FCR_RFRST | FCR_TFRST);
108 124 *SCFCR;
109 125 *SCFCR = 0;
110 126  
111 127  
112 128  
... ... @@ -112,21 +128,21 @@
112 128 return 0;
113 129 }
114 130  
115   -static int serial_rx_fifo_level (void)
  131 +static int serial_rx_fifo_level(void)
116 132 {
117   -#if defined(CONFIG_SH4A)
  133 +#if defined(SCRFDR)
118 134 return (*SCRFDR >> 0) & FIFOLEVEL_MASK;
119 135 #else
120 136 return (*SCFDR >> 0) & FIFOLEVEL_MASK;
121 137 #endif
122 138 }
123 139  
124   -void serial_raw_putc (const char c)
  140 +void serial_raw_putc(const char c)
125 141 {
126 142 unsigned int fsr_bits_to_clear;
127 143  
128 144 while (1) {
129   - if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
  145 + if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
130 146 fsr_bits_to_clear = FSR_TEND;
131 147 break;
132 148 }
133 149  
134 150  
135 151  
136 152  
137 153  
138 154  
139 155  
140 156  
141 157  
142 158  
143 159  
144 160  
145 161  
146 162  
147 163  
148 164  
149 165  
150 166  
151 167  
152 168  
... ... @@ -137,66 +153,68 @@
137 153 *SCFSR &= ~fsr_bits_to_clear;
138 154 }
139 155  
140   -void serial_putc (const char c)
  156 +void serial_putc(const char c)
141 157 {
142 158 if (c == '\n')
143   - serial_raw_putc ('\r');
144   - serial_raw_putc (c);
  159 + serial_raw_putc('\r');
  160 + serial_raw_putc(c);
145 161 }
146 162  
147   -void serial_puts (const char *s)
  163 +void serial_puts(const char *s)
148 164 {
149 165 char c;
150 166 while ((c = *s++) != 0)
151   - serial_putc (c);
  167 + serial_putc(c);
152 168 }
153 169  
154   -int serial_tstc (void)
  170 +int serial_tstc(void)
155 171 {
156   - return serial_rx_fifo_level() ? 1 : 0;
  172 + return serial_rx_fifo_level()? 1 : 0;
157 173 }
158 174  
159   -#define FSR_ERR_CLEAR 0x0063
160   -#define RDRF_CLEAR 0x00fc
161   -void handle_error( void ){
  175 +#define FSR_ERR_CLEAR 0x0063
  176 +#define RDRF_CLEAR 0x00fc
  177 +void handle_error(void)
  178 +{
162 179  
163   - (void)*SCFSR ;
164   - *SCFSR = FSR_ERR_CLEAR ;
165   - (void)*SCLSR ;
166   - *SCLSR = 0x00 ;
  180 + (void)*SCFSR;
  181 + *SCFSR = FSR_ERR_CLEAR;
  182 + (void)*SCLSR;
  183 + *SCLSR = 0x00;
167 184 }
168 185  
169   -int serial_getc_check( void ){
  186 +int serial_getc_check(void)
  187 +{
170 188 unsigned short status;
171 189  
172   - status = *SCFSR ;
  190 + status = *SCFSR;
173 191  
174   - if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
  192 + if (status & (FSR_FER | FSR_ER | FSR_BRK))
175 193 handle_error();
176   - if( *SCLSR & LSR_ORER )
  194 + if (*SCLSR & LSR_ORER)
177 195 handle_error();
178   - return (status & ( FSR_DR | FSR_RDF ));
  196 + return (status & (FSR_DR | FSR_RDF));
179 197 }
180 198  
181   -int serial_getc (void)
  199 +int serial_getc(void)
182 200 {
183   - unsigned short status ;
  201 + unsigned short status;
184 202 char ch;
185   - while(!serial_getc_check());
  203 + while (!serial_getc_check()) ;
186 204  
187 205 ch = *SCFRDR;
188   - status = *SCFSR ;
  206 + status = *SCFSR;
189 207  
190   - *SCFSR = RDRF_CLEAR ;
  208 + *SCFSR = RDRF_CLEAR;
191 209  
192 210 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
193 211 handle_error();
194 212  
195   - if( *SCLSR & LSR_ORER )
  213 + if (*SCLSR & LSR_ORER)
196 214 handle_error();
197 215  
198   - return ch ;
  216 + return ch;
199 217 }
200 218  
201   -#endif /* CFG_SCIF_CONSOLE */
  219 +#endif /* CFG_SCIF_CONSOLE */