Commit 0911af00b09c065444e4f8842a67a11c0d9b03cd
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4425e62856
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v2017.01-smarct4x
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arm: socfpga: clock: Add missing stubs into board file
Add some stub defines, which are used by the clock code, but are missing from the auto-generated header file for the SoCFPGA family. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 3 additions and 0 deletions Inline Diff
board/altera/socfpga/pll_config.h
| 1 | /* | 1 | /* |
| 2 | * Copyright Altera Corporation (C) 2012-2014. All rights reserved | 2 | * Copyright Altera Corporation (C) 2012-2014. All rights reserved |
| 3 | * | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause | 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ | 5 | */ |
| 6 | 6 | ||
| 7 | /* This file is generated by Preloader Generator */ | 7 | /* This file is generated by Preloader Generator */ |
| 8 | 8 | ||
| 9 | #ifndef _PRELOADER_PLL_CONFIG_H_ | 9 | #ifndef _PRELOADER_PLL_CONFIG_H_ |
| 10 | #define _PRELOADER_PLL_CONFIG_H_ | 10 | #define _PRELOADER_PLL_CONFIG_H_ |
| 11 | 11 | ||
| 12 | /* PLL configuration data */ | 12 | /* PLL configuration data */ |
| 13 | /* Main PLL */ | 13 | /* Main PLL */ |
| 14 | #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) | 14 | #define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) |
| 15 | #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) | 15 | #define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) |
| 16 | #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) | 16 | #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) |
| 17 | #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) | 17 | #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) |
| 18 | #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) | 18 | #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) |
| 19 | #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) | 19 | #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3) |
| 20 | #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) | 20 | #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3) |
| 21 | #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) | 21 | #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (12) |
| 22 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) | 22 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) |
| 23 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) | 23 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) |
| 24 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) | 24 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) |
| 25 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) | 25 | #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) |
| 26 | #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) | 26 | #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) |
| 27 | #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) | 27 | #define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) |
| 28 | #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) | 28 | #define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) |
| 29 | /* | 29 | /* |
| 30 | * To tell where is the clock source: | 30 | * To tell where is the clock source: |
| 31 | * 0 = MAINPLL | 31 | * 0 = MAINPLL |
| 32 | * 1 = PERIPHPLL | 32 | * 1 = PERIPHPLL |
| 33 | */ | 33 | */ |
| 34 | #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) | 34 | #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) |
| 35 | #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) | 35 | #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) |
| 36 | 36 | ||
| 37 | /* Peripheral PLL */ | 37 | /* Peripheral PLL */ |
| 38 | #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) | 38 | #define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) |
| 39 | #define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) | 39 | #define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) |
| 40 | /* | 40 | /* |
| 41 | * To tell where is the VCOs source: | 41 | * To tell where is the VCOs source: |
| 42 | * 0 = EOSC1 | 42 | * 0 = EOSC1 |
| 43 | * 1 = EOSC2 | 43 | * 1 = EOSC2 |
| 44 | * 2 = F2S | 44 | * 2 = F2S |
| 45 | */ | 45 | */ |
| 46 | #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) | 46 | #define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) |
| 47 | #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) | 47 | #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) |
| 48 | #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) | 48 | #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3) |
| 49 | #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) | 49 | #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1) |
| 50 | #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) | 50 | #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) |
| 51 | #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) | 51 | #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) |
| 52 | #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) | 52 | #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9) |
| 53 | #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) | 53 | #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) |
| 54 | #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) | 54 | #define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0) |
| 55 | #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) | 55 | #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) |
| 56 | #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) | 56 | #define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) |
| 57 | #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) | 57 | #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) |
| 58 | /* | 58 | /* |
| 59 | * To tell where is the clock source: | 59 | * To tell where is the clock source: |
| 60 | * 0 = F2S_PERIPH_REF_CLK | 60 | * 0 = F2S_PERIPH_REF_CLK |
| 61 | * 1 = MAIN_CLK | 61 | * 1 = MAIN_CLK |
| 62 | * 2 = PERIPH_CLK | 62 | * 2 = PERIPH_CLK |
| 63 | */ | 63 | */ |
| 64 | #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) | 64 | #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) |
| 65 | #define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) | 65 | #define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) |
| 66 | #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) | 66 | #define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) |
| 67 | 67 | ||
| 68 | /* SDRAM PLL */ | 68 | /* SDRAM PLL */ |
| 69 | #ifdef CONFIG_SOCFPGA_ARRIA5 | 69 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 70 | /* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz | 70 | /* Arria V SDRAM will run at 533MHz while Cyclone V still at 400MHz |
| 71 | * This if..else... is not required if generated by tools */ | 71 | * This if..else... is not required if generated by tools */ |
| 72 | #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) | 72 | #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) |
| 73 | #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) | 73 | #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (127) |
| 74 | #else | 74 | #else |
| 75 | #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) | 75 | #define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0) |
| 76 | #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) | 76 | #define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31) |
| 77 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ | 77 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ |
| 78 | 78 | ||
| 79 | /* | 79 | /* |
| 80 | * To tell where is the VCOs source: | 80 | * To tell where is the VCOs source: |
| 81 | * 0 = EOSC1 | 81 | * 0 = EOSC1 |
| 82 | * 1 = EOSC2 | 82 | * 1 = EOSC2 |
| 83 | * 2 = F2S | 83 | * 2 = F2S |
| 84 | */ | 84 | */ |
| 85 | #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) | 85 | #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) |
| 86 | #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) | 86 | #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) |
| 87 | #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) | 87 | #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) |
| 88 | #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) | 88 | #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) |
| 89 | #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) | 89 | #define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) |
| 90 | #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) | 90 | #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) |
| 91 | #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) | 91 | #define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) |
| 92 | #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) | 92 | #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) |
| 93 | #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) | 93 | #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) |
| 94 | 94 | ||
| 95 | /* Info for driver */ | 95 | /* Info for driver */ |
| 96 | #define CONFIG_HPS_CLK_OSC1_HZ (25000000) | 96 | #define CONFIG_HPS_CLK_OSC1_HZ (25000000) |
| 97 | #define CONFIG_HPS_CLK_OSC2_HZ 0 | ||
| 98 | #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 | ||
| 99 | #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 | ||
| 97 | #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) | 100 | #define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) |
| 98 | #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) | 101 | #define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) |
| 99 | #ifdef CONFIG_SOCFPGA_ARRIA5 | 102 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 100 | /* The if..else... is not required if generated by tools */ | 103 | /* The if..else... is not required if generated by tools */ |
| 101 | #define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) | 104 | #define CONFIG_HPS_CLK_SDRVCO_HZ (1066000000) |
| 102 | #else | 105 | #else |
| 103 | #define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) | 106 | #define CONFIG_HPS_CLK_SDRVCO_HZ (800000000) |
| 104 | #endif | 107 | #endif |
| 105 | #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) | 108 | #define CONFIG_HPS_CLK_EMAC0_HZ (250000000) |
| 106 | #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) | 109 | #define CONFIG_HPS_CLK_EMAC1_HZ (250000000) |
| 107 | #define CONFIG_HPS_CLK_USBCLK_HZ (200000000) | 110 | #define CONFIG_HPS_CLK_USBCLK_HZ (200000000) |
| 108 | #define CONFIG_HPS_CLK_NAND_HZ (50000000) | 111 | #define CONFIG_HPS_CLK_NAND_HZ (50000000) |
| 109 | #define CONFIG_HPS_CLK_SDMMC_HZ (200000000) | 112 | #define CONFIG_HPS_CLK_SDMMC_HZ (200000000) |
| 110 | #define CONFIG_HPS_CLK_QSPI_HZ (400000000) | 113 | #define CONFIG_HPS_CLK_QSPI_HZ (400000000) |
| 111 | #define CONFIG_HPS_CLK_SPIM_HZ (200000000) | 114 | #define CONFIG_HPS_CLK_SPIM_HZ (200000000) |
| 112 | #define CONFIG_HPS_CLK_CAN0_HZ (100000000) | 115 | #define CONFIG_HPS_CLK_CAN0_HZ (100000000) |
| 113 | #define CONFIG_HPS_CLK_CAN1_HZ (100000000) | 116 | #define CONFIG_HPS_CLK_CAN1_HZ (100000000) |
| 114 | #define CONFIG_HPS_CLK_GPIODB_HZ (32000) | 117 | #define CONFIG_HPS_CLK_GPIODB_HZ (32000) |
| 115 | #define CONFIG_HPS_CLK_L4_MP_HZ (100000000) | 118 | #define CONFIG_HPS_CLK_L4_MP_HZ (100000000) |
| 116 | #define CONFIG_HPS_CLK_L4_SP_HZ (100000000) | 119 | #define CONFIG_HPS_CLK_L4_SP_HZ (100000000) |
| 117 | 120 | ||
| 118 | #endif /* _PRELOADER_PLL_CONFIG_H_ */ | 121 | #endif /* _PRELOADER_PLL_CONFIG_H_ */ |
| 119 | 122 |