Commit 4425e6285679a22522638bd4bb5281611635a30e
1 parent
09f7e314e4
Exists in
v2017.01-smarct4x
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arm: socfpga: clock: Drop nonsense inlining from clock manager code
The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
Showing 1 changed file with 6 additions and 6 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/clock_manager.c
| ... | ... | @@ -30,7 +30,7 @@ |
| 30 | 30 | CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ |
| 31 | 31 | CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) |
| 32 | 32 | |
| 33 | -static inline void cm_wait_for_lock(uint32_t mask) | |
| 33 | +static void cm_wait_for_lock(uint32_t mask) | |
| 34 | 34 | { |
| 35 | 35 | register uint32_t inter_val; |
| 36 | 36 | do { |
| ... | ... | @@ -39,7 +39,7 @@ |
| 39 | 39 | } |
| 40 | 40 | |
| 41 | 41 | /* function to poll in the fsm busy bit */ |
| 42 | -static inline void cm_wait_for_fsm(void) | |
| 42 | +static void cm_wait_for_fsm(void) | |
| 43 | 43 | { |
| 44 | 44 | while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) |
| 45 | 45 | ; |
| 46 | 46 | |
| 47 | 47 | |
| ... | ... | @@ -49,22 +49,22 @@ |
| 49 | 49 | * function to write the bypass register which requires a poll of the |
| 50 | 50 | * busy bit |
| 51 | 51 | */ |
| 52 | -static inline void cm_write_bypass(uint32_t val) | |
| 52 | +static void cm_write_bypass(uint32_t val) | |
| 53 | 53 | { |
| 54 | 54 | writel(val, &clock_manager_base->bypass); |
| 55 | 55 | cm_wait_for_fsm(); |
| 56 | 56 | } |
| 57 | 57 | |
| 58 | 58 | /* function to write the ctrl register which requires a poll of the busy bit */ |
| 59 | -static inline void cm_write_ctrl(uint32_t val) | |
| 59 | +static void cm_write_ctrl(uint32_t val) | |
| 60 | 60 | { |
| 61 | 61 | writel(val, &clock_manager_base->ctrl); |
| 62 | 62 | cm_wait_for_fsm(); |
| 63 | 63 | } |
| 64 | 64 | |
| 65 | 65 | /* function to write a clock register that has phase information */ |
| 66 | -static inline void cm_write_with_phase(uint32_t value, | |
| 67 | - uint32_t reg_address, uint32_t mask) | |
| 66 | +static void cm_write_with_phase(uint32_t value, | |
| 67 | + uint32_t reg_address, uint32_t mask) | |
| 68 | 68 | { |
| 69 | 69 | /* poll until phase is zero */ |
| 70 | 70 | while (readl(reg_address) & mask) |