net: keystone_net: move header file from arch to ti-common

The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

net: keystone_net: move header file from arch to ti-common
The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Khoronzhuk, Ivan · Tom Rini
1 parent e3114c9a06
Showing 10 changed files with 261 additions and 260 deletions Side-by-side Diff
arch/arm/include/asm/arch-keystone/emac_defs.h
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
arch/arm/include/asm/arch-keystone/hardware.h
arch/arm/include/asm/ti-common/keystone_net.h
board/ti/ks2_evm/board.c
board/ti/ks2_evm/board.h
board/ti/ks2_evm/board_k2hk.c
drivers/net/keystone_net.c
include/configs/k2hk_evm.h
include/configs/ks2_evm.h
-/*
- * emac definitions for keystone2 devices
- *
- * (C) Copyright 2012-2014
- *     Texas Instruments Incorporated, <www.ti.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _EMAC_DEFS_H_
-#define _EMAC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-/* EMAC */
-#ifdef KS2_NETCP_V1_0
-
-#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00090900)
-#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00090300)
-#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00090100)
-#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x)*0x040)
-
-/* Register offsets */
-#define CPGMACSL_REG_CTL		0x04
-#define CPGMACSL_REG_STATUS		0x08
-#define CPGMACSL_REG_RESET		0x0c
-#define CPGMACSL_REG_MAXLEN		0x10
-
-#elif defined KS2_NETCP_V1_5
-
-#define CPGMACSL_REG_RX_PRI_MAP		0x020
-#define EMAC_EMACSL_BASE_ADDR           (KS2_PASS_BASE + 0x00222000)
-#define EMAC_MDIO_BASE_ADDR             (KS2_PASS_BASE + 0x00200f00)
-#define EMAC_SGMII_BASE_ADDR            (KS2_PASS_BASE + 0x00200100)
-#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
-
-/* Register offsets */
-#define CPGMACSL_REG_CTL		0x330
-#define CPGMACSL_REG_STATUS		0x334
-#define CPGMACSL_REG_RESET		0x338
-#define CPGMACSL_REG_MAXLEN		0x024
-
-#endif
-
-#define KEYSTONE2_EMAC_GIG_ENABLE
-
-#define MAC_ID_BASE_ADDR                (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
-
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ              (clk_get_rate(pass_pll_clk))
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ            1000000		/* 1.0 MHz */
-
-/* MII Status Register */
-#define MII_STATUS_REG                  1
-#define MII_STATUS_LINK_MASK            (0x4)
-
-/* Marvell 88E1111 PHY ID */
-#define PHY_MARVELL_88E1111             (0x01410cc0)
-
-#define MDIO_CONTROL_IDLE               (0x80000000)
-#define MDIO_CONTROL_ENABLE             (0x40000000)
-#define MDIO_CONTROL_FAULT_ENABLE       (0x40000)
-#define MDIO_CONTROL_FAULT              (0x80000)
-#define MDIO_USERACCESS0_GO             (0x80000000)
-#define MDIO_USERACCESS0_WRITE_READ     (0x0)
-#define MDIO_USERACCESS0_WRITE_WRITE    (0x40000000)
-#define MDIO_USERACCESS0_ACK            (0x20000000)
-
-#define EMAC_MACCONTROL_MIIEN_ENABLE       (0x20)
-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE  (0x1)
-#define EMAC_MACCONTROL_GIGABIT_ENABLE     (1 << 7)
-#define EMAC_MACCONTROL_GIGFORCE           (1 << 17)
-#define EMAC_MACCONTROL_RMIISPEED_100      (1 << 15)
-
-#define EMAC_MIN_ETHERNET_PKT_SIZE         60
-
-struct mac_sl_cfg {
-	u_int32_t max_rx_len;	/* Maximum receive packet length. */
-	u_int32_t ctl;		/* Control bitfield */
-};
-
-/*
- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
- */
-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES       (1 << 24)
-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES         (1 << 23)
-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES         (1 << 22)
-#define GMACSL_RX_ENABLE_EXT_CTL                  (1 << 18)
-#define GMACSL_RX_ENABLE_GIG_FORCE                (1 << 17)
-#define GMACSL_RX_ENABLE_IFCTL_B                  (1 << 16)
-#define GMACSL_RX_ENABLE_IFCTL_A                  (1 << 15)
-#define GMACSL_RX_ENABLE_CMD_IDLE                 (1 << 11)
-#define GMACSL_TX_ENABLE_SHORT_GAP                (1 << 10)
-#define GMACSL_ENABLE_GIG_MODE                    (1 <<  7)
-#define GMACSL_TX_ENABLE_PACE                     (1 <<  6)
-#define GMACSL_ENABLE                             (1 <<  5)
-#define GMACSL_TX_ENABLE_FLOW_CTL                 (1 <<  4)
-#define GMACSL_RX_ENABLE_FLOW_CTL                 (1 <<  3)
-#define GMACSL_ENABLE_LOOPBACK                    (1 <<  1)
-#define GMACSL_ENABLE_FULL_DUPLEX                 (1 <<  0)
-
-/*
- * DEFINTITION: function return values
- */
-#define GMACSL_RET_OK                        0
-#define GMACSL_RET_INVALID_PORT             -1
-#define GMACSL_RET_WARN_RESET_INCOMPLETE    -2
-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG      -3
-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
-
-/* EMAC SL register definitions */
-#define DEVICE_EMACSL_RESET_POLL_COUNT		  100
-
-/* Soft reset register values */
-#define CPGMAC_REG_RESET_VAL_RESET_MASK      (1 << 0)
-#define CPGMAC_REG_RESET_VAL_RESET           (1 << 0)
-
-/* Maxlen register values */
-#define CPGMAC_REG_MAXLEN_LEN                0x3fff
-
-/* CPSW */
-/* Control bitfields */
-#define CPSW_CTL_P2_PASS_PRI_TAGGED     (1 << 5)
-#define CPSW_CTL_P1_PASS_PRI_TAGGED     (1 << 4)
-#define CPSW_CTL_P0_PASS_PRI_TAGGED     (1 << 3)
-#define CPSW_CTL_P0_ENABLE              (1 << 2)
-#define CPSW_CTL_VLAN_AWARE             (1 << 1)
-#define CPSW_CTL_FIFO_LOOPBACK          (1 << 0)
-
-#define DEVICE_CPSW_NUM_PORTS		CONFIG_KSNET_CPSW_NUM_PORTS
-#define DEVICE_N_GMACSL_PORTS		(DEVICE_CPSW_NUM_PORTS - 1)
-
-#ifdef KS2_NETCP_V1_0
-
-#define DEVICE_CPSW_BASE		(KS2_PASS_BASE + 0x00090800)
-#define CPSW_REG_CTL			0x004
-#define CPSW_REG_STAT_PORT_EN		0x00c
-#define CPSW_REG_MAXLEN			0x040
-#define CPSW_REG_ALE_CONTROL		0x608
-#define CPSW_REG_ALE_PORTCTL(x)		(0x640 + (x)*4)
-#define CPSW_REG_VAL_STAT_ENABLE_ALL     0xf
-
-#elif defined KS2_NETCP_V1_5
-
-#define DEVICE_CPSW_BASE		 (KS2_PASS_BASE + 0x00220000)
-#define CPSW_REG_CTL		         0x00004
-#define CPSW_REG_STAT_PORT_EN	         0x00014
-#define CPSW_REG_MAXLEN		         0x01024
-#define CPSW_REG_ALE_CONTROL	         0x1e008
-#define CPSW_REG_ALE_PORTCTL(x)		 (0x1e040 + (x) * 4)
-#define CPSW_REG_VAL_STAT_ENABLE_ALL     0x1ff
-
-#endif
-
-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE    ((u_int32_t)0xc0000000)
-#define CPSW_REG_VAL_ALE_CTL_BYPASS              ((u_int32_t)0x00000010)
-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE        0x3
-
-#define target_get_switch_ctl()     CPSW_CTL_P0_ENABLE   /* Enable port 0 */
-#define SWITCH_MAX_PKT_SIZE         9000
-
-/* SGMII */
-#define SGMII_REG_STATUS_LOCK           BIT(4)
-#define SGMII_REG_STATUS_LINK           BIT(0)
-#define SGMII_REG_STATUS_AUTONEG        BIT(2)
-#define SGMII_REG_CONTROL_AUTONEG       BIT(0)
-#define SGMII_REG_CONTROL_MASTER        BIT(5)
-#define	SGMII_REG_MR_ADV_ENABLE         BIT(0)
-#define	SGMII_REG_MR_ADV_LINK           BIT(15)
-#define	SGMII_REG_MR_ADV_FULL_DUPLEX    BIT(12)
-#define SGMII_REG_MR_ADV_GIG_MODE       BIT(11)
-
-#define SGMII_LINK_MAC_MAC_AUTONEG      0
-#define SGMII_LINK_MAC_PHY              1
-#define SGMII_LINK_MAC_MAC_FORCED       2
-#define SGMII_LINK_MAC_FIBER            3
-#define SGMII_LINK_MAC_PHY_FORCED       4
-
-#ifdef KS2_NETCP_V1_0
-#define SGMII_OFFSET(x)	((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
-#elif defined KS2_NETCP_V1_5
-#define SGMII_OFFSET(x)			((x) * 0x100)
-#endif
-
-#define SGMII_IDVER_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
-#define SGMII_SRESET_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
-#define SGMII_CTL_REG(x)      (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
-#define SGMII_STATUS_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
-#define SGMII_MRADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
-#define SGMII_LPADV_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
-#define SGMII_TXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
-#define SGMII_RXCFG_REG(x)    (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
-#define SGMII_AUXCFG_REG(x)   (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
-
-/* PSS */
-#ifdef KS2_NETCP_V1_0
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x604)
-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
-#define hw_config_streaming_switch()\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
-
-#elif defined KS2_NETCP_V1_5
-
-#define DEVICE_PSTREAM_CFG_REG_ADDR		(KS2_PASS_BASE + 0x500)
-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
-
-#define hw_config_streaming_switch()\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
-	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
-	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
-
-#endif
-
-/* EMAC MDIO Registers Structure */
-struct mdio_regs {
-	dv_reg		version;
-	dv_reg		control;
-	dv_reg		alive;
-	dv_reg		link;
-	dv_reg		linkintraw;
-	dv_reg		linkintmasked;
-	u_int8_t	rsvd0[8];
-	dv_reg		userintraw;
-	dv_reg		userintmasked;
-	dv_reg		userintmaskset;
-	dv_reg		userintmaskclear;
-	u_int8_t	rsvd1[80];
-	dv_reg		useraccess0;
-	dv_reg		userphysel0;
-	dv_reg		useraccess1;
-	dv_reg		userphysel1;
-};
-
-struct eth_priv_t {
-	char	int_name[32];
-	int	rx_flow;
-	int	phy_addr;
-	int	slave_port;
-	int	sgmii_link_type;
-};
-
-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
-void sgmii_serdes_setup_156p25mhz(void);
-void sgmii_serdes_shutdown(void);
-
-#endif  /* _EMAC_DEFS_H_ */
@@ -95,8 +95,8 @@
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
 #define KS2_NETCP_PDMA_TX_SND_QUEUE	648
  
-/* NETCP version */
-#define KS2_NETCP_V1_0
+/* NETCP */
+#define KS2_NETCP_BASE			0x02000000
  
 #endif /* __ASM_ARCH_HARDWARE_H */
@@ -175,6 +175,8 @@
 #define KS2_DEV_USB_PHY_BASE		0x02620738
 #define KS2_USB_PHY_CFG_BASE		0x02630000
  
+#define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
 #ifdef CONFIG_SOC_K2HK
 #include <asm/arch/hardware-k2hk.h>
 #endif
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NET_H_
+#define _KEYSTONE_NET_H_
+
+#include <asm/io.h>
+
+/* EMAC */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00090000)
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x900)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x300)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x04
+#define CPGMACSL_REG_STATUS		0x08
+#define CPGMACSL_REG_RESET		0x0c
+#define CPGMACSL_REG_MAXLEN		0x10
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define GBETH_BASE			(CONFIG_KSNET_NETCP_BASE + 0x00200000)
+#define CPGMACSL_REG_RX_PRI_MAP		0x020
+#define EMAC_EMACSL_BASE_ADDR		(GBETH_BASE + 0x22000)
+#define EMAC_MDIO_BASE_ADDR		(GBETH_BASE + 0x00f00)
+#define EMAC_SGMII_BASE_ADDR		(GBETH_BASE + 0x00100)
+#define DEVICE_EMACSL_BASE(x)		(EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
+
+/* Register offsets */
+#define CPGMACSL_REG_CTL		0x330
+#define CPGMACSL_REG_STATUS		0x334
+#define CPGMACSL_REG_RESET		0x338
+#define CPGMACSL_REG_MAXLEN		0x024
+
+#endif
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR		CONFIG_KSNET_MAC_ID_BASE
+
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ		(clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ		1000000                /* 1.0 MHz */
+
+/* MII Status Register */
+#define MII_STATUS_REG			1
+#define MII_STATUS_LINK_MASK		0x4
+
+#define MDIO_CONTROL_IDLE		0x80000000
+#define MDIO_CONTROL_ENABLE		0x40000000
+#define MDIO_CONTROL_FAULT_ENABLE	0x40000
+#define MDIO_CONTROL_FAULT		0x80000
+#define MDIO_USERACCESS0_GO		0x80000000
+#define MDIO_USERACCESS0_WRITE_READ	0x0
+#define MDIO_USERACCESS0_WRITE_WRITE	0x40000000
+#define MDIO_USERACCESS0_ACK		0x20000000
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE		0x20
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE	0x1
+#define EMAC_MACCONTROL_GIGABIT_ENABLE		BIT(7)
+#define EMAC_MACCONTROL_GIGFORCE		BIT(17)
+#define EMAC_MACCONTROL_RMIISPEED_100		BIT(15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE		60
+
+struct mac_sl_cfg {
+	u_int32_t max_rx_len;	/* Maximum receive packet length. */
+	u_int32_t ctl;		/* Control bitfield */
+};
+
+/**
+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES	BIT(24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES	BIT(23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES	BIT(22)
+#define GMACSL_RX_ENABLE_EXT_CTL		BIT(18)
+#define GMACSL_RX_ENABLE_GIG_FORCE		BIT(17)
+#define GMACSL_RX_ENABLE_IFCTL_B		BIT(16)
+#define GMACSL_RX_ENABLE_IFCTL_A		BIT(15)
+#define GMACSL_RX_ENABLE_CMD_IDLE		BIT(11)
+#define GMACSL_TX_ENABLE_SHORT_GAP		BIT(10)
+#define GMACSL_ENABLE_GIG_MODE			BIT(7)
+#define GMACSL_TX_ENABLE_PACE			BIT(6)
+#define GMACSL_ENABLE				BIT(5)
+#define GMACSL_TX_ENABLE_FLOW_CTL		BIT(4)
+#define GMACSL_RX_ENABLE_FLOW_CTL		BIT(3)
+#define GMACSL_ENABLE_LOOPBACK			BIT(1)
+#define GMACSL_ENABLE_FULL_DUPLEX		BIT(0)
+
+/* EMAC SL function return values */
+#define GMACSL_RET_OK				0
+#define GMACSL_RET_INVALID_PORT			-1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE	-2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG		-3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE	-4
+
+/* EMAC SL register definitions */
+#define DEVICE_EMACSL_RESET_POLL_COUNT		100
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK		BIT(0)
+#define CPGMAC_REG_RESET_VAL_RESET		BIT(0)
+#define CPGMAC_REG_MAXLEN_LEN			0x3fff
+
+/* CPSW */
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED		BIT(5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED		BIT(4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED		BIT(3)
+#define CPSW_CTL_P0_ENABLE			BIT(2)
+#define CPSW_CTL_VLAN_AWARE			BIT(1)
+#define CPSW_CTL_FIFO_LOOPBACK			BIT(0)
+
+#define DEVICE_CPSW_NUM_PORTS			CONFIG_KSNET_CPSW_NUM_PORTS
+#define DEVICE_N_GMACSL_PORTS			(DEVICE_CPSW_NUM_PORTS - 1)
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x800)
+#define CPSW_REG_CTL				0x004
+#define CPSW_REG_STAT_PORT_EN			0x00c
+#define CPSW_REG_MAXLEN				0x040
+#define CPSW_REG_ALE_CONTROL			0x608
+#define CPSW_REG_ALE_PORTCTL(x)			(0x640 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0xf
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_CPSW_BASE			(GBETH_BASE + 0x20000)
+#define CPSW_REG_CTL				0x00004
+#define CPSW_REG_STAT_PORT_EN			0x00014
+#define CPSW_REG_MAXLEN				0x01024
+#define CPSW_REG_ALE_CONTROL			0x1e008
+#define CPSW_REG_ALE_PORTCTL(x)			(0x1e040 + (x) * 4)
+#define CPSW_REG_VAL_STAT_ENABLE_ALL		0x1ff
+
+#endif
+
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE	((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS		((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE	0x3
+
+#define target_get_switch_ctl()			CPSW_CTL_P0_ENABLE
+#define SWITCH_MAX_PKT_SIZE			9000
+
+/* SGMII */
+#define SGMII_REG_STATUS_LOCK			BIT(4)
+#define SGMII_REG_STATUS_LINK			BIT(0)
+#define SGMII_REG_STATUS_AUTONEG		BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG		BIT(0)
+#define SGMII_REG_CONTROL_MASTER		BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE			BIT(0)
+#define SGMII_REG_MR_ADV_LINK			BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX		BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE		BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG		0
+#define SGMII_LINK_MAC_PHY			1
+#define SGMII_LINK_MAC_MAC_FORCED		2
+#define SGMII_LINK_MAC_FIBER			3
+#define SGMII_LINK_MAC_PHY_FORCED		4
+
+#ifdef CONFIG_KSNET_NETCP_V1_0
+#define SGMII_OFFSET(x)		((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+#elif defined CONFIG_KSNET_NETCP_V1_5
+#define SGMII_OFFSET(x)		((x) * 0x100)
+#endif
+
+#define SGMII_IDVER_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x)	(EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
+
+/* PSS */
+#ifdef CONFIG_KSNET_NETCP_V1_0
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x604)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x06060606
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
+
+#elif defined CONFIG_KSNET_NETCP_V1_5
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR	(CONFIG_KSNET_NETCP_BASE + 0x500)
+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI	0x0
+
+#define hw_config_streaming_switch()\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+4);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+8);\
+	writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
+	       DEVICE_PSTREAM_CFG_REG_ADDR+12);
+
+#endif
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+	u32 version;
+	u32 control;
+	u32 alive;
+	u32 link;
+	u32 linkintraw;
+	u32 linkintmasked;
+	u32 rsvd0[2];
+	u32 userintraw;
+	u32 userintmasked;
+	u32 userintmaskset;
+	u32 userintmaskclear;
+	u32 rsvd1[20];
+	u32 useraccess0;
+	u32 userphysel0;
+	u32 useraccess1;
+	u32 userphysel1;
+};
+
+struct eth_priv_t {
+	char int_name[32];
+	int rx_flow;
+	int phy_addr;
+	int slave_port;
+	int sgmii_link_type;
+};
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif  /* _KEYSTONE_NET_H_ */
@@ -13,8 +13,8 @@
 #include <exports.h>
 #include <fdt_support.h>
 #include <asm/arch/ddr3.h>
-#include <asm/arch/emac_defs.h>
 #include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -10,7 +10,7 @@
 #ifndef _KS2_BOARD
 #define _KS2_BOARD
  
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
  
 extern struct eth_priv_t eth_priv_cfg[];
  
@@ -10,7 +10,7 @@
 #include <common.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
-#include <asm/arch/emac_defs.h>
+#include <asm/ti-common/keystone_net.h>
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -12,9 +12,9 @@
 #include <net.h>
 #include <miiphy.h>
 #include <malloc.h>
-#include <asm/arch/emac_defs.h>
 #include <asm/arch/psc_defs.h>
 #include <asm/ti-common/keystone_nav.h>
+#include <asm/ti-common/keystone_net.h>
  
 unsigned int emac_dbg;
  
@@ -38,6 +38,7 @@
 #define CONFIG_DRIVER_TI_KEYSTONE_NET
 #define CONFIG_TI_KSNAV
 #define CONFIG_KSNAV_PKTDMA_NETCP
+#define CONFIG_KSNET_NETCP_V1_0
 #define CONFIG_KSNET_CPSW_NUM_PORTS	5
  
 #endif /* __CONFIG_K2HK_EVM_H */
@@ -133,6 +133,10 @@
 #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
 #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE
  
+/* Keystone net */
+#define CONFIG_KSNET_MAC_ID_BASE	KS2_MAC_ID_BASE_ADDR
+#define CONFIG_KSNET_NETCP_BASE		KS2_NETCP_BASE
+
 /* AEMIF */
 #define CONFIG_TI_AEMIF
 #define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE
1		-/*
2		- * emac definitions for keystone2 devices
3		- *
4		- * (C) Copyright 2012-2014
5		- * Texas Instruments Incorporated, <www.ti.com>
6		- *
7		- * SPDX-License-Identifier: GPL-2.0+
8		- */
9		-
10		-#ifndef _EMAC_DEFS_H_
11		-#define _EMAC_DEFS_H_
12		-
13		-#include <asm/arch/hardware.h>
14		-#include <asm/io.h>
15		-
16		-/* EMAC */
17		-#ifdef KS2_NETCP_V1_0
18		-
19		-#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
20		-#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
21		-#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
22		-#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x)*0x040)
23		-
24		-/* Register offsets */
25		-#define CPGMACSL_REG_CTL 0x04
26		-#define CPGMACSL_REG_STATUS 0x08
27		-#define CPGMACSL_REG_RESET 0x0c
28		-#define CPGMACSL_REG_MAXLEN 0x10
29		-
30		-#elif defined KS2_NETCP_V1_5
31		-
32		-#define CPGMACSL_REG_RX_PRI_MAP 0x020
33		-#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00222000)
34		-#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00200f00)
35		-#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00200100)
36		-#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
37		-
38		-/* Register offsets */
39		-#define CPGMACSL_REG_CTL 0x330
40		-#define CPGMACSL_REG_STATUS 0x334
41		-#define CPGMACSL_REG_RESET 0x338
42		-#define CPGMACSL_REG_MAXLEN 0x024
43		-
44		-#endif
45		-
46		-#define KEYSTONE2_EMAC_GIG_ENABLE
47		-
48		-#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
49		-
50		-/* MDIO module input frequency */
51		-#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
52		-/* MDIO clock output frequency */
53		-#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
54		-
55		-/* MII Status Register */
56		-#define MII_STATUS_REG 1
57		-#define MII_STATUS_LINK_MASK (0x4)
58		-
59		-/* Marvell 88E1111 PHY ID */
60		-#define PHY_MARVELL_88E1111 (0x01410cc0)
61		-
62		-#define MDIO_CONTROL_IDLE (0x80000000)
63		-#define MDIO_CONTROL_ENABLE (0x40000000)
64		-#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
65		-#define MDIO_CONTROL_FAULT (0x80000)
66		-#define MDIO_USERACCESS0_GO (0x80000000)
67		-#define MDIO_USERACCESS0_WRITE_READ (0x0)
68		-#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
69		-#define MDIO_USERACCESS0_ACK (0x20000000)
70		-
71		-#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
72		-#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
73		-#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
74		-#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
75		-#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
76		-
77		-#define EMAC_MIN_ETHERNET_PKT_SIZE 60
78		-
79		-struct mac_sl_cfg {
80		- u_int32_t max_rx_len; /* Maximum receive packet length. */
81		- u_int32_t ctl; /* Control bitfield */
82		-};
83		-
84		-/*
85		- * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
86		- */
87		-#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
88		-#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
89		-#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
90		-#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
91		-#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
92		-#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
93		-#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
94		-#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
95		-#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
96		-#define GMACSL_ENABLE_GIG_MODE (1 << 7)
97		-#define GMACSL_TX_ENABLE_PACE (1 << 6)
98		-#define GMACSL_ENABLE (1 << 5)
99		-#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
100		-#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
101		-#define GMACSL_ENABLE_LOOPBACK (1 << 1)
102		-#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
103		-
104		-/*
105		- * DEFINTITION: function return values
106		- */
107		-#define GMACSL_RET_OK 0
108		-#define GMACSL_RET_INVALID_PORT -1
109		-#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
110		-#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
111		-#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
112		-
113		-/* EMAC SL register definitions */
114		-#define DEVICE_EMACSL_RESET_POLL_COUNT 100
115		-
116		-/* Soft reset register values */
117		-#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
118		-#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
119		-
120		-/* Maxlen register values */
121		-#define CPGMAC_REG_MAXLEN_LEN 0x3fff
122		-
123		-/* CPSW */
124		-/* Control bitfields */
125		-#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
126		-#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
127		-#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
128		-#define CPSW_CTL_P0_ENABLE (1 << 2)
129		-#define CPSW_CTL_VLAN_AWARE (1 << 1)
130		-#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
131		-
132		-#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
133		-#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
134		-
135		-#ifdef KS2_NETCP_V1_0
136		-
137		-#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00090800)
138		-#define CPSW_REG_CTL 0x004
139		-#define CPSW_REG_STAT_PORT_EN 0x00c
140		-#define CPSW_REG_MAXLEN 0x040
141		-#define CPSW_REG_ALE_CONTROL 0x608
142		-#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
143		-#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
144		-
145		-#elif defined KS2_NETCP_V1_5
146		-
147		-#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00220000)
148		-#define CPSW_REG_CTL 0x00004
149		-#define CPSW_REG_STAT_PORT_EN 0x00014
150		-#define CPSW_REG_MAXLEN 0x01024
151		-#define CPSW_REG_ALE_CONTROL 0x1e008
152		-#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
153		-#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
154		-
155		-#endif
156		-
157		-#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
158		-#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
159		-#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
160		-
161		-#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
162		-#define SWITCH_MAX_PKT_SIZE 9000
163		-
164		-/* SGMII */
165		-#define SGMII_REG_STATUS_LOCK BIT(4)
166		-#define SGMII_REG_STATUS_LINK BIT(0)
167		-#define SGMII_REG_STATUS_AUTONEG BIT(2)
168		-#define SGMII_REG_CONTROL_AUTONEG BIT(0)
169		-#define SGMII_REG_CONTROL_MASTER BIT(5)
170		-#define SGMII_REG_MR_ADV_ENABLE BIT(0)
171		-#define SGMII_REG_MR_ADV_LINK BIT(15)
172		-#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
173		-#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
174		-
175		-#define SGMII_LINK_MAC_MAC_AUTONEG 0
176		-#define SGMII_LINK_MAC_PHY 1
177		-#define SGMII_LINK_MAC_MAC_FORCED 2
178		-#define SGMII_LINK_MAC_FIBER 3
179		-#define SGMII_LINK_MAC_PHY_FORCED 4
180		-
181		-#ifdef KS2_NETCP_V1_0
182		-#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
183		-#elif defined KS2_NETCP_V1_5
184		-#define SGMII_OFFSET(x) ((x) * 0x100)
185		-#endif
186		-
187		-#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
188		-#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
189		-#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
190		-#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
191		-#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
192		-#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
193		-#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
194		-#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
195		-#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
196		-
197		-/* PSS */
198		-#ifdef KS2_NETCP_V1_0
199		-
200		-#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
201		-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
202		-#define hw_config_streaming_switch()\
203		- writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
204		-
205		-#elif defined KS2_NETCP_V1_5
206		-
207		-#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x500)
208		-#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
209		-
210		-#define hw_config_streaming_switch()\
211		- writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
212		- DEVICE_PSTREAM_CFG_REG_ADDR);\
213		- writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
214		- DEVICE_PSTREAM_CFG_REG_ADDR+4);\
215		- writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
216		- DEVICE_PSTREAM_CFG_REG_ADDR+8);\
217		- writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
218		- DEVICE_PSTREAM_CFG_REG_ADDR+12);
219		-
220		-#endif
221		-
222		-/* EMAC MDIO Registers Structure */
223		-struct mdio_regs {
224		- dv_reg version;
225		- dv_reg control;
226		- dv_reg alive;
227		- dv_reg link;
228		- dv_reg linkintraw;
229		- dv_reg linkintmasked;
230		- u_int8_t rsvd0[8];
231		- dv_reg userintraw;
232		- dv_reg userintmasked;
233		- dv_reg userintmaskset;
234		- dv_reg userintmaskclear;
235		- u_int8_t rsvd1[80];
236		- dv_reg useraccess0;
237		- dv_reg userphysel0;
238		- dv_reg useraccess1;
239		- dv_reg userphysel1;
240		-};
241		-
242		-struct eth_priv_t {
243		- char int_name[32];
244		- int rx_flow;
245		- int phy_addr;
246		- int slave_port;
247		- int sgmii_link_type;
248		-};
249		-
250		-int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
251		-void sgmii_serdes_setup_156p25mhz(void);
252		-void sgmii_serdes_shutdown(void);
253		-
254		-#endif /* _EMAC_DEFS_H_ */
...	...	@@ -95,8 +95,8 @@
95	95	#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
96	96	#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
97	97
98		-/* NETCP version */
99		-#define KS2_NETCP_V1_0
	98	+/* NETCP */
	99	+#define KS2_NETCP_BASE 0x02000000
100	100
101	101	#endif /* __ASM_ARCH_HARDWARE_H */
...	...	@@ -175,6 +175,8 @@
175	175	#define KS2_DEV_USB_PHY_BASE 0x02620738
176	176	#define KS2_USB_PHY_CFG_BASE 0x02630000
177	177
	178	+#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
	179	+
178	180	#ifdef CONFIG_SOC_K2HK
179	181	#include <asm/arch/hardware-k2hk.h>
180	182	#endif
	1	+/*
	2	+ * emac definitions for keystone2 devices
	3	+ *
	4	+ * (C) Copyright 2012-2014
	5	+ * Texas Instruments Incorporated, <www.ti.com>
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef _KEYSTONE_NET_H_
	11	+#define _KEYSTONE_NET_H_
	12	+
	13	+#include <asm/io.h>
	14	+
	15	+/* EMAC */
	16	+#ifdef CONFIG_KSNET_NETCP_V1_0
	17	+
	18	+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
	19	+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
	20	+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
	21	+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
	22	+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
	23	+
	24	+/* Register offsets */
	25	+#define CPGMACSL_REG_CTL 0x04
	26	+#define CPGMACSL_REG_STATUS 0x08
	27	+#define CPGMACSL_REG_RESET 0x0c
	28	+#define CPGMACSL_REG_MAXLEN 0x10
	29	+
	30	+#elif defined CONFIG_KSNET_NETCP_V1_5
	31	+
	32	+#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
	33	+#define CPGMACSL_REG_RX_PRI_MAP 0x020
	34	+#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
	35	+#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
	36	+#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
	37	+#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
	38	+
	39	+/* Register offsets */
	40	+#define CPGMACSL_REG_CTL 0x330
	41	+#define CPGMACSL_REG_STATUS 0x334
	42	+#define CPGMACSL_REG_RESET 0x338
	43	+#define CPGMACSL_REG_MAXLEN 0x024
	44	+
	45	+#endif
	46	+
	47	+#define KEYSTONE2_EMAC_GIG_ENABLE
	48	+
	49	+#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
	50	+
	51	+/* MDIO module input frequency */
	52	+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
	53	+/* MDIO clock output frequency */
	54	+#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
	55	+
	56	+/* MII Status Register */
	57	+#define MII_STATUS_REG 1
	58	+#define MII_STATUS_LINK_MASK 0x4
	59	+
	60	+#define MDIO_CONTROL_IDLE 0x80000000
	61	+#define MDIO_CONTROL_ENABLE 0x40000000
	62	+#define MDIO_CONTROL_FAULT_ENABLE 0x40000
	63	+#define MDIO_CONTROL_FAULT 0x80000
	64	+#define MDIO_USERACCESS0_GO 0x80000000
	65	+#define MDIO_USERACCESS0_WRITE_READ 0x0
	66	+#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000
	67	+#define MDIO_USERACCESS0_ACK 0x20000000
	68	+
	69	+#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
	70	+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
	71	+#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
	72	+#define EMAC_MACCONTROL_GIGFORCE BIT(17)
	73	+#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
	74	+
	75	+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
	76	+
	77	+struct mac_sl_cfg {
	78	+ u_int32_t max_rx_len; /* Maximum receive packet length. */
	79	+ u_int32_t ctl; /* Control bitfield */
	80	+};
	81	+
	82	+/**
	83	+ * Definition: Control bitfields used in the ctl field of mac_sl_cfg
	84	+ */
	85	+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
	86	+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
	87	+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
	88	+#define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
	89	+#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
	90	+#define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
	91	+#define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
	92	+#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
	93	+#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
	94	+#define GMACSL_ENABLE_GIG_MODE BIT(7)
	95	+#define GMACSL_TX_ENABLE_PACE BIT(6)
	96	+#define GMACSL_ENABLE BIT(5)
	97	+#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
	98	+#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
	99	+#define GMACSL_ENABLE_LOOPBACK BIT(1)
	100	+#define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
	101	+
	102	+/* EMAC SL function return values */
	103	+#define GMACSL_RET_OK 0
	104	+#define GMACSL_RET_INVALID_PORT -1
	105	+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
	106	+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
	107	+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
	108	+
	109	+/* EMAC SL register definitions */
	110	+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
	111	+
	112	+/* Soft reset register values */
	113	+#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
	114	+#define CPGMAC_REG_RESET_VAL_RESET BIT(0)
	115	+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
	116	+
	117	+/* CPSW */
	118	+/* Control bitfields */
	119	+#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
	120	+#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
	121	+#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
	122	+#define CPSW_CTL_P0_ENABLE BIT(2)
	123	+#define CPSW_CTL_VLAN_AWARE BIT(1)
	124	+#define CPSW_CTL_FIFO_LOOPBACK BIT(0)
	125	+
	126	+#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
	127	+#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
	128	+
	129	+#ifdef CONFIG_KSNET_NETCP_V1_0
	130	+
	131	+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
	132	+#define CPSW_REG_CTL 0x004
	133	+#define CPSW_REG_STAT_PORT_EN 0x00c
	134	+#define CPSW_REG_MAXLEN 0x040
	135	+#define CPSW_REG_ALE_CONTROL 0x608
	136	+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
	137	+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
	138	+
	139	+#elif defined CONFIG_KSNET_NETCP_V1_5
	140	+
	141	+#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
	142	+#define CPSW_REG_CTL 0x00004
	143	+#define CPSW_REG_STAT_PORT_EN 0x00014
	144	+#define CPSW_REG_MAXLEN 0x01024
	145	+#define CPSW_REG_ALE_CONTROL 0x1e008
	146	+#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
	147	+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
	148	+
	149	+#endif
	150	+
	151	+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
	152	+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
	153	+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
	154	+
	155	+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
	156	+#define SWITCH_MAX_PKT_SIZE 9000
	157	+
	158	+/* SGMII */
	159	+#define SGMII_REG_STATUS_LOCK BIT(4)
	160	+#define SGMII_REG_STATUS_LINK BIT(0)
	161	+#define SGMII_REG_STATUS_AUTONEG BIT(2)
	162	+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
	163	+#define SGMII_REG_CONTROL_MASTER BIT(5)
	164	+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
	165	+#define SGMII_REG_MR_ADV_LINK BIT(15)
	166	+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
	167	+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
	168	+
	169	+#define SGMII_LINK_MAC_MAC_AUTONEG 0
	170	+#define SGMII_LINK_MAC_PHY 1
	171	+#define SGMII_LINK_MAC_MAC_FORCED 2
	172	+#define SGMII_LINK_MAC_FIBER 3
	173	+#define SGMII_LINK_MAC_PHY_FORCED 4
	174	+
	175	+#ifdef CONFIG_KSNET_NETCP_V1_0
	176	+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
	177	+#elif defined CONFIG_KSNET_NETCP_V1_5
	178	+#define SGMII_OFFSET(x) ((x) * 0x100)
	179	+#endif
	180	+
	181	+#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
	182	+#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
	183	+#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
	184	+#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
	185	+#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
	186	+#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
	187	+#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
	188	+#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
	189	+#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
	190	+
	191	+/* PSS */
	192	+#ifdef CONFIG_KSNET_NETCP_V1_0
	193	+
	194	+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
	195	+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
	196	+#define hw_config_streaming_switch()\
	197	+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
	198	+
	199	+#elif defined CONFIG_KSNET_NETCP_V1_5
	200	+
	201	+#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
	202	+#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
	203	+
	204	+#define hw_config_streaming_switch()\
	205	+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
	206	+ DEVICE_PSTREAM_CFG_REG_ADDR);\
	207	+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
	208	+ DEVICE_PSTREAM_CFG_REG_ADDR+4);\
	209	+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
	210	+ DEVICE_PSTREAM_CFG_REG_ADDR+8);\
	211	+ writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
	212	+ DEVICE_PSTREAM_CFG_REG_ADDR+12);
	213	+
	214	+#endif
	215	+
	216	+/* EMAC MDIO Registers Structure */
	217	+struct mdio_regs {
	218	+ u32 version;
	219	+ u32 control;
	220	+ u32 alive;
	221	+ u32 link;
	222	+ u32 linkintraw;
	223	+ u32 linkintmasked;
	224	+ u32 rsvd0[2];
	225	+ u32 userintraw;
	226	+ u32 userintmasked;
	227	+ u32 userintmaskset;
	228	+ u32 userintmaskclear;
	229	+ u32 rsvd1[20];
	230	+ u32 useraccess0;
	231	+ u32 userphysel0;
	232	+ u32 useraccess1;
	233	+ u32 userphysel1;
	234	+};
	235	+
	236	+struct eth_priv_t {
	237	+ char int_name[32];
	238	+ int rx_flow;
	239	+ int phy_addr;
	240	+ int slave_port;
	241	+ int sgmii_link_type;
	242	+};
	243	+
	244	+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
	245	+void sgmii_serdes_setup_156p25mhz(void);
	246	+void sgmii_serdes_shutdown(void);
	247	+
	248	+#endif /* _KEYSTONE_NET_H_ */
...	...	@@ -13,8 +13,8 @@
13	13	#include <exports.h>
14	14	#include <fdt_support.h>
15	15	#include <asm/arch/ddr3.h>
16		-#include <asm/arch/emac_defs.h>
17	16	#include <asm/ti-common/ti-aemif.h>
	17	+#include <asm/ti-common/keystone_net.h>
18	18
19	19	DECLARE_GLOBAL_DATA_PTR;
20	20
...	...	@@ -10,7 +10,7 @@
10	10	#ifndef _KS2_BOARD
11	11	#define _KS2_BOARD
12	12
13		-#include <asm/arch/emac_defs.h>
	13	+#include <asm/ti-common/keystone_net.h>
14	14
15	15	extern struct eth_priv_t eth_priv_cfg[];
16	16
...	...	@@ -10,7 +10,7 @@
10	10	#include <common.h>
11	11	#include <asm/arch/clock.h>
12	12	#include <asm/arch/hardware.h>
13		-#include <asm/arch/emac_defs.h>
	13	+#include <asm/ti-common/keystone_net.h>
14	14
15	15	DECLARE_GLOBAL_DATA_PTR;
16	16
...	...	@@ -12,9 +12,9 @@
12	12	#include <net.h>
13	13	#include <miiphy.h>
14	14	#include <malloc.h>
15		-#include <asm/arch/emac_defs.h>
16	15	#include <asm/arch/psc_defs.h>
17	16	#include <asm/ti-common/keystone_nav.h>
	17	+#include <asm/ti-common/keystone_net.h>
18	18
19	19	unsigned int emac_dbg;
20	20
...	...	@@ -38,6 +38,7 @@
38	38	#define CONFIG_DRIVER_TI_KEYSTONE_NET
39	39	#define CONFIG_TI_KSNAV
40	40	#define CONFIG_KSNAV_PKTDMA_NETCP
	41	+#define CONFIG_KSNET_NETCP_V1_0
41	42	#define CONFIG_KSNET_CPSW_NUM_PORTS 5
42	43
43	44	#endif /* __CONFIG_K2HK_EVM_H */
...	...	@@ -133,6 +133,10 @@
133	133	#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
134	134	#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
135	135
	136	+/* Keystone net */
	137	+#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
	138	+#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
	139	+
136	140	/* AEMIF */
137	141	#define CONFIG_TI_AEMIF
138	142	#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE