igep003x: Add support for IGEP SMARC AM335x

The IGEP SMARC AM335x is an industrial processor module with following highlights: o AM3352 TI processor (Up to AM3359) o Cortex-A8 ARM CPU o SMARC form factor module o Up to 512 MB DDR3 SDRAM / 512 MB FLASH o WiFi a/b/g/n and Bluetooth v4.0 on-board o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>

igep003x: Add support for IGEP SMARC AM335x
The IGEP SMARC AM335x is an industrial processor module with following highlights: o AM3352 TI processor (Up to AM3359) o Cortex-A8 ARM CPU o SMARC form factor module o Up to 512 MB DDR3 SDRAM / 512 MB FLASH o WiFi a/b/g/n and Bluetooth v4.0 on-board o Ethernet 10/100/1000 Mbps and 10/100 Mbps controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Pau Pajuelo <ppajuelo@iseebcn.com> Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
Pau Pajuelo · Tom Rini
1 parent 3607e0f86f
Showing 6 changed files with 187 additions and 73 deletions Side-by-side Diff
arch/arm/mach-omap2/am33xx/Kconfig
board/isee/igep003x/board.c
board/isee/igep003x/mux.c
configs/am335x_igep0033_defconfig
configs/am335x_igep003x_defconfig
include/configs/am335x_igep003x.h
@@ -46,6 +46,7 @@
  
 config TARGET_AM335X_IGEP003X
 	bool "Support am335x_igep003x"
+	select BOARD_LATE_INIT
 	select DM
 	select DM_SERIAL
 	select DM_GPIO
 /*
- * Board functions for IGEP COM AQUILA based boards
+ * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
  *
- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
+ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
  
  
  
  
@@ -26,21 +26,72 @@
 #include <fdt_support.h>
 #include <mtd_node.h>
 #include <jffs2/load_kernel.h>
+#include <environment.h>
 #include "board.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
+/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
+ * and control IGEP0034 green and red LEDs.
+ * U-boot configures these pins as input pullup to detect board revision:
+ * IGEP0034-LITE = 0b00
+ * IGEP0034 (FULL) = 0b01
+ * IGEP0033 = 0b1X
+ */
+#define GPIO_GREEN_REVISION	27
+#define GPIO_RED_REVISION	26
+
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  
+/*
+ * Routine: get_board_revision
+ * Description: Returns the board revision
+ */
+static int get_board_revision(void)
+{
+	int revision;
+
+	gpio_request(GPIO_GREEN_REVISION, "green_revision");
+	gpio_direction_input(GPIO_GREEN_REVISION);
+	revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
+	gpio_free(GPIO_GREEN_REVISION);
+
+	gpio_request(GPIO_RED_REVISION, "red_revision");
+	gpio_direction_input(GPIO_RED_REVISION);
+	revision = revision + gpio_get_value(GPIO_RED_REVISION);
+	gpio_free(GPIO_RED_REVISION);
+
+	return revision;
+}
+
 #ifdef CONFIG_SPL_BUILD
-static const struct ddr_data ddr3_data = {
+/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
+static const struct ddr_data ddr3_igep0034_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct ddr_data ddr3_igep0034_lite_data = {
 	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
 	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
 	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
 	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
 };
  
-static const struct cmd_control ddr3_cmd_ctrl_data = {
+static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
 	.cmd0csratio = K4B2G1646EBIH9_RATIO,
 	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  
@@ -51,7 +102,17 @@
 	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 };
  
-static struct emif_regs ddr3_emif_reg_data = {
+static struct emif_regs ddr3_igep0034_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
 	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
 	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
 	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
@@ -61,6 +122,22 @@
 	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
 };
  
+const struct ctrl_ioregs ioregs_igep0034 = {
+	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+const struct ctrl_ioregs ioregs_igep0034_lite = {
+	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
+};
+
 #define OSC    (V_OSCK/1000000)
 const struct dpll_params dpll_ddr = {
 		400, OSC-1, 1, -1, -1, -1, -1};
  
@@ -80,18 +157,14 @@
 	enable_board_pin_mux();
 }
  
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.cm2ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt0ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-	.dt1ioctl		= K4B2G1646EBIH9_IOCTRL_VALUE,
-};
-
 void sdram_init(void)
 {
-	config_ddr(400, &ioregs, &ddr3_data,
-		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+	if (get_board_revision() == 1)
+		config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
+			&ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
+	else
+		config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
+			&ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
 }
 #endif
  
@@ -107,6 +180,26 @@
 	return 0;
 }
  
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	switch (get_board_revision()) {
+		case 0:
+			setenv("board_name", "igep0034-lite");
+			break;
+		case 1:
+			setenv("board_name", "igep0034");
+			break;
+		default:
+			setenv("board_name", "igep0033");
+			break;
+	}
+#endif
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
@@ -179,6 +272,9 @@
  
 	writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
 	       &cdev->miisel);
+
+	if (get_board_revision() == 1)
+		cpsw_slaves[0].phy_addr = 1;
  
 	rv = cpsw_register(&cpsw_data);
 	if (rv < 0)
@@ -32,7 +32,7 @@
 	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
 	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
 	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
-	{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)},		/* MMC0_CD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
 	{-1},
 };
  
@@ -69,6 +69,12 @@
 	{-1},
 };
  
+static struct module_pin_mux gpio_pin_mux[] = {
+	{OFFSET(gpmc_ad10), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_26 */
+	{OFFSET(gpmc_ad11), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* GPIO0_27 */
+	{-1},
+};
+
 void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
@@ -85,5 +91,7 @@
 	configure_module_pin_mux(mmc0_pin_mux);
 	/* Ethernet pinmux. */
 	configure_module_pin_mux(rmii1_pin_mux);
+	/* GPIO pinmux. */
+	configure_module_pin_mux(gpio_pin_mux);
 }
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_AM33XX=y
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_TARGET_AM335X_IGEP003X=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_FAT_SUPPORT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SPL=y
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_EXT_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-CONFIG_CMD_UBI=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_SYS_NS16550=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
-# CONFIG_GENERATE_SMBIOS_TABLE is not set
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_AM335X_IGEP003X=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_NAND_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_FAT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_UBI=y
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_SYS_NS16550=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
@@ -34,7 +34,6 @@
 	DEFAULT_LINUX_BOOT_ENV \
 	"bootdir=/boot\0" \
 	"bootfile=zImage\0" \
-	"dtbfile=am335x-base0033.dtb\0" \
 	"console=ttyO0,115200n8\0" \
 	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
@@ -48,7 +47,7 @@
 	"importbootenv=echo Importing environment from mmc ...; " \
 		"env import -t ${loadaddr} ${filesize}\0" \
 	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
-		"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${dtbfile}file}\0" \" \
+		"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}file}\0" \" \
 	"mmcboot=mmc dev ${mmcdev}; " \
 		"if mmc rescan; then " \
 			"echo SD/MMC found on device ${mmcdev};" \
  
@@ -79,10 +78,20 @@
 	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
 		"run nandload; " \
-		"bootz ${loadaddr} - ${fdtaddr} \0"
+		"bootz ${loadaddr} - ${fdtaddr} \0" \
+	"findfdt="\
+		"if test ${board_name} = igep0033; then " \
+			"setenv fdtfile am335x-igep-base0033.dtb; fi; " \
+		"if test ${board_name} = igep0034; then " \
+			"setenv fdtfile am335x-igep-base0040.dtb; fi; " \
+		"if test ${board_name} = igep0034-lite; then " \
+			"setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \
+		"if test ${fdtfile} = ''; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0"
 #endif
  
 #define CONFIG_BOOTCOMMAND \
+	"run findfdt;" \
 	"run mmcboot;" \
 	"run nandboot;"
...	...	@@ -46,6 +46,7 @@
46	46
47	47	config TARGET_AM335X_IGEP003X
48	48	bool "Support am335x_igep003x"
	49	+ select BOARD_LATE_INIT
49	50	select DM
50	51	select DM_SERIAL
51	52	select DM_GPIO
1	1	/*
2		- * Board functions for IGEP COM AQUILA based boards
	2	+ * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
3	3	*
4		- * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
	4	+ * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
5	5	*
6	6	* SPDX-License-Identifier: GPL-2.0+
7	7	*/
8	8
9	9
10	10
11	11
...	...	@@ -26,21 +26,72 @@
26	26	#include <fdt_support.h>
27	27	#include <mtd_node.h>
28	28	#include <jffs2/load_kernel.h>
	29	+#include <environment.h>
29	30	#include "board.h"
30	31
31	32	DECLARE_GLOBAL_DATA_PTR;
32	33
	34	+/* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
	35	+ * and control IGEP0034 green and red LEDs.
	36	+ * U-boot configures these pins as input pullup to detect board revision:
	37	+ * IGEP0034-LITE = 0b00
	38	+ * IGEP0034 (FULL) = 0b01
	39	+ * IGEP0033 = 0b1X
	40	+ */
	41	+#define GPIO_GREEN_REVISION 27
	42	+#define GPIO_RED_REVISION 26
	43	+
33	44	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
34	45
	46	+/*
	47	+ * Routine: get_board_revision
	48	+ * Description: Returns the board revision
	49	+ */
	50	+static int get_board_revision(void)
	51	+{
	52	+ int revision;
	53	+
	54	+ gpio_request(GPIO_GREEN_REVISION, "green_revision");
	55	+ gpio_direction_input(GPIO_GREEN_REVISION);
	56	+ revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
	57	+ gpio_free(GPIO_GREEN_REVISION);
	58	+
	59	+ gpio_request(GPIO_RED_REVISION, "red_revision");
	60	+ gpio_direction_input(GPIO_RED_REVISION);
	61	+ revision = revision + gpio_get_value(GPIO_RED_REVISION);
	62	+ gpio_free(GPIO_RED_REVISION);
	63	+
	64	+ return revision;
	65	+}
	66	+
35	67	#ifdef CONFIG_SPL_BUILD
36		-static const struct ddr_data ddr3_data = {
	68	+/* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
	69	+static const struct ddr_data ddr3_igep0034_data = {
	70	+ .datardsratio0 = MT41K256M16HA125E_RD_DQS,
	71	+ .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	72	+ .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	73	+ .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	74	+};
	75	+
	76	+static const struct ddr_data ddr3_igep0034_lite_data = {
37	77	.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
38	78	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
39	79	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
40	80	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
41	81	};
42	82
43		-static const struct cmd_control ddr3_cmd_ctrl_data = {
	83	+static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
	84	+ .cmd0csratio = MT41K256M16HA125E_RATIO,
	85	+ .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	86	+
	87	+ .cmd1csratio = MT41K256M16HA125E_RATIO,
	88	+ .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	89	+
	90	+ .cmd2csratio = MT41K256M16HA125E_RATIO,
	91	+ .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	92	+};
	93	+
	94	+static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
44	95	.cmd0csratio = K4B2G1646EBIH9_RATIO,
45	96	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
46	97
...	...	@@ -51,7 +102,17 @@
51	102	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
52	103	};
53	104
54		-static struct emif_regs ddr3_emif_reg_data = {
	105	+static struct emif_regs ddr3_igep0034_emif_reg_data = {
	106	+ .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	107	+ .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	108	+ .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	109	+ .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	110	+ .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	111	+ .zq_config = MT41K256M16HA125E_ZQ_CFG,
	112	+ .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	113	+};
	114	+
	115	+static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
55	116	.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
56	117	.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
57	118	.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
...	...	@@ -61,6 +122,22 @@
61	122	.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
62	123	};
63	124
	125	+const struct ctrl_ioregs ioregs_igep0034 = {
	126	+ .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	127	+ .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	128	+ .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	129	+ .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	130	+ .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	131	+};
	132	+
	133	+const struct ctrl_ioregs ioregs_igep0034_lite = {
	134	+ .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	135	+ .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	136	+ .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	137	+ .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	138	+ .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
	139	+};
	140	+
64	141	#define OSC (V_OSCK/1000000)
65	142	const struct dpll_params dpll_ddr = {
66	143	400, OSC-1, 1, -1, -1, -1, -1};
67	144
...	...	@@ -80,18 +157,14 @@
80	157	enable_board_pin_mux();
81	158	}
82	159
83		-const struct ctrl_ioregs ioregs = {
84		- .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
85		- .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
86		- .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
87		- .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
88		- .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
89		-};
90		-
91	160	void sdram_init(void)
92	161	{
93		- config_ddr(400, &ioregs, &ddr3_data,
94		- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
	162	+ if (get_board_revision() == 1)
	163	+ config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
	164	+ &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
	165	+ else
	166	+ config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
	167	+ &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
95	168	}
96	169	#endif
97	170
...	...	@@ -107,6 +180,26 @@
107	180	return 0;
108	181	}
109	182
	183	+#ifdef CONFIG_BOARD_LATE_INIT
	184	+int board_late_init(void)
	185	+{
	186	+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	187	+ switch (get_board_revision()) {
	188	+ case 0:
	189	+ setenv("board_name", "igep0034-lite");
	190	+ break;
	191	+ case 1:
	192	+ setenv("board_name", "igep0034");
	193	+ break;
	194	+ default:
	195	+ setenv("board_name", "igep0033");
	196	+ break;
	197	+ }
	198	+#endif
	199	+ return 0;
	200	+}
	201	+#endif
	202	+
110	203	#ifdef CONFIG_OF_BOARD_SETUP
111	204	int ft_board_setup(void blob, bd_t bd)
112	205	{
...	...	@@ -179,6 +272,9 @@
179	272
180	273	writel((GMII1_SEL_RMII \| RMII1_IO_CLK_EN),
181	274	&cdev->miisel);
	275	+
	276	+ if (get_board_revision() == 1)
	277	+ cpsw_slaves[0].phy_addr = 1;
182	278
183	279	rv = cpsw_register(&cpsw_data);
184	280	if (rv < 0)
...	...	@@ -32,7 +32,7 @@
32	32	{OFFSET(mmc0_dat0), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_DAT0 */
33	33	{OFFSET(mmc0_clk), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CLK */
34	34	{OFFSET(mmc0_cmd), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CMD */
35		- {OFFSET(mcasp0_aclkx), (MODE(4) \| RXACTIVE)}, /* MMC0_CD */
	35	+ {OFFSET(spi0_cs1), (MODE(5) \| RXACTIVE \| PULLUP_EN)}, /* MMC0_CD */
36	36	{-1},
37	37	};
38	38
...	...	@@ -69,6 +69,12 @@
69	69	{-1},
70	70	};
71	71
	72	+static struct module_pin_mux gpio_pin_mux[] = {
	73	+ {OFFSET(gpmc_ad10), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* GPIO0_26 */
	74	+ {OFFSET(gpmc_ad11), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* GPIO0_27 */
	75	+ {-1},
	76	+};
	77	+
72	78	void enable_uart0_pin_mux(void)
73	79	{
74	80	configure_module_pin_mux(uart0_pin_mux);
...	...	@@ -85,5 +91,7 @@
85	91	configure_module_pin_mux(mmc0_pin_mux);
86	92	/* Ethernet pinmux. */
87	93	configure_module_pin_mux(rmii1_pin_mux);
	94	+ /* GPIO pinmux. */
	95	+ configure_module_pin_mux(gpio_pin_mux);
88	96	}
1		-CONFIG_ARM=y
2		-CONFIG_ARCH_OMAP2PLUS=y
3		-CONFIG_SPL_GPIO_SUPPORT=y
4		-CONFIG_SPL_LIBCOMMON_SUPPORT=y
5		-CONFIG_SPL_LIBGENERIC_SUPPORT=y
6		-CONFIG_AM33XX=y
7		-CONFIG_SYS_MALLOC_F_LEN=0x2000
8		-CONFIG_TARGET_AM335X_IGEP003X=y
9		-CONFIG_SPL_MMC_SUPPORT=y
10		-CONFIG_SPL_SERIAL_SUPPORT=y
11		-CONFIG_SPL_LIBDISK_SUPPORT=y
12		-CONFIG_SPL_NAND_SUPPORT=y
13		-CONFIG_SPL_WATCHDOG_SUPPORT=y
14		-CONFIG_SPL_FAT_SUPPORT=y
15		-CONFIG_SPL_POWER_SUPPORT=y
16		-CONFIG_SPL_STACK_R_ADDR=0x82000000
17		-CONFIG_OF_BOARD_SETUP=y
18		-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
19		-CONFIG_SYS_CONSOLE_INFO_QUIET=y
20		-CONFIG_VERSION_VARIABLE=y
21		-CONFIG_SPL=y
22		-CONFIG_SPL_STACK_R=y
23		-CONFIG_SPL_EXT_SUPPORT=y
24		-CONFIG_SPL_I2C_SUPPORT=y
25		-CONFIG_SPL_MTD_SUPPORT=y
26		-CONFIG_SPL_YMODEM_SUPPORT=y
27		-CONFIG_HUSH_PARSER=y
28		-CONFIG_CMD_BOOTZ=y
29		-# CONFIG_CMD_IMLS is not set
30		-CONFIG_CMD_ASKENV=y
31		-# CONFIG_CMD_FLASH is not set
32		-CONFIG_CMD_MMC=y
33		-CONFIG_CMD_PART=y
34		-CONFIG_CMD_SPI=y
35		-CONFIG_CMD_I2C=y
36		-CONFIG_CMD_GPIO=y
37		-# CONFIG_CMD_SETEXPR is not set
38		-CONFIG_CMD_DHCP=y
39		-CONFIG_CMD_MII=y
40		-CONFIG_CMD_PING=y
41		-CONFIG_CMD_EXT2=y
42		-CONFIG_CMD_EXT4=y
43		-CONFIG_CMD_EXT4_WRITE=y
44		-CONFIG_CMD_FAT=y
45		-CONFIG_CMD_FS_GENERIC=y
46		-CONFIG_CMD_UBI=y
47		-CONFIG_ISO_PARTITION=y
48		-CONFIG_EFI_PARTITION=y
49		-CONFIG_MMC_OMAP_HS=y
50		-CONFIG_MTD_UBI_FASTMAP=y
51		-CONFIG_SYS_NS16550=y
52		-CONFIG_OF_LIBFDT=y
53		-CONFIG_FDT_FIXUP_PARTITIONS=y
54		-# CONFIG_GENERATE_SMBIOS_TABLE is not set
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_OMAP2PLUS=y
	3	+CONFIG_SPL_GPIO_SUPPORT=y
	4	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	5	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	6	+CONFIG_AM33XX=y
	7	+CONFIG_SYS_MALLOC_F_LEN=0x2000
	8	+CONFIG_TARGET_AM335X_IGEP003X=y
	9	+CONFIG_SPL_MMC_SUPPORT=y
	10	+CONFIG_SPL_SERIAL_SUPPORT=y
	11	+CONFIG_SPL_LIBDISK_SUPPORT=y
	12	+CONFIG_SPL_NAND_SUPPORT=y
	13	+CONFIG_SPL_WATCHDOG_SUPPORT=y
	14	+CONFIG_SPL_FAT_SUPPORT=y
	15	+CONFIG_SPL_POWER_SUPPORT=y
	16	+CONFIG_SPL_STACK_R_ADDR=0x82000000
	17	+CONFIG_OF_BOARD_SETUP=y
	18	+CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0033"
	19	+CONFIG_SYS_CONSOLE_INFO_QUIET=y
	20	+CONFIG_VERSION_VARIABLE=y
	21	+CONFIG_SPL=y
	22	+CONFIG_SPL_STACK_R=y
	23	+CONFIG_SPL_EXT_SUPPORT=y
	24	+CONFIG_SPL_I2C_SUPPORT=y
	25	+CONFIG_SPL_MTD_SUPPORT=y
	26	+CONFIG_SPL_YMODEM_SUPPORT=y
	27	+CONFIG_HUSH_PARSER=y
	28	+CONFIG_CMD_BOOTZ=y
	29	+# CONFIG_CMD_IMLS is not set
	30	+CONFIG_CMD_ASKENV=y
	31	+# CONFIG_CMD_FLASH is not set
	32	+CONFIG_CMD_MMC=y
	33	+CONFIG_CMD_PART=y
	34	+CONFIG_CMD_SPI=y
	35	+CONFIG_CMD_I2C=y
	36	+CONFIG_CMD_GPIO=y
	37	+# CONFIG_CMD_SETEXPR is not set
	38	+CONFIG_CMD_DHCP=y
	39	+CONFIG_CMD_MII=y
	40	+CONFIG_CMD_PING=y
	41	+CONFIG_CMD_EXT2=y
	42	+CONFIG_CMD_EXT4=y
	43	+CONFIG_CMD_EXT4_WRITE=y
	44	+CONFIG_CMD_FAT=y
	45	+CONFIG_CMD_FS_GENERIC=y
	46	+CONFIG_CMD_UBI=y
	47	+CONFIG_ISO_PARTITION=y
	48	+CONFIG_EFI_PARTITION=y
	49	+CONFIG_MMC_OMAP_HS=y
	50	+CONFIG_MTD_UBI_FASTMAP=y
	51	+CONFIG_SYS_NS16550=y
	52	+CONFIG_OF_LIBFDT=y
	53	+CONFIG_FDT_FIXUP_PARTITIONS=y
	54	+# CONFIG_GENERATE_SMBIOS_TABLE is not set
...	...	@@ -34,7 +34,6 @@
34	34	DEFAULT_LINUX_BOOT_ENV \
35	35	"bootdir=/boot\0" \
36	36	"bootfile=zImage\0" \
37		- "dtbfile=am335x-base0033.dtb\0" \
38	37	"console=ttyO0,115200n8\0" \
39	38	"mmcdev=0\0" \
40	39	"mmcroot=/dev/mmcblk0p2 rw\0" \
...	...	@@ -48,7 +47,7 @@
48	47	"importbootenv=echo Importing environment from mmc ...; " \
49	48	"env import -t ${loadaddr} ${filesize}\0" \
50	49	"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
51		- "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${dtbfile}file}\0" \" \
	50	+ "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}file}\0" \" \
52	51	"mmcboot=mmc dev ${mmcdev}; " \
53	52	"if mmc rescan; then " \
54	53	"echo SD/MMC found on device ${mmcdev};" \
55	54
...	...	@@ -79,10 +78,20 @@
79	78	"nandboot=echo Booting from nand ...; " \
80	79	"run nandargs; " \
81	80	"run nandload; " \
82		- "bootz ${loadaddr} - ${fdtaddr} \0"
	81	+ "bootz ${loadaddr} - ${fdtaddr} \0" \
	82	+ "findfdt="\
	83	+ "if test ${board_name} = igep0033; then " \
	84	+ "setenv fdtfile am335x-igep-base0033.dtb; fi; " \
	85	+ "if test ${board_name} = igep0034; then " \
	86	+ "setenv fdtfile am335x-igep-base0040.dtb; fi; " \
	87	+ "if test ${board_name} = igep0034-lite; then " \
	88	+ "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \
	89	+ "if test ${fdtfile} = ''; then " \
	90	+ "echo WARNING: Could not determine device tree to use; fi; \0"
83	91	#endif
84	92
85	93	#define CONFIG_BOOTCOMMAND \
	94	+ "run findfdt;" \
86	95	"run mmcboot;" \
87	96	"run nandboot;"
88	97