ARMV7: OMAP3: Convert setup_auxcr() to pure asm

This function consists entirely of inline asm statements, so writing it directly in a .S file is simpler. Additionally, the inline asm is not safe as is, since registers are not guaranteed to be preserved between asm() statements. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

ARMV7: OMAP3: Convert setup_auxcr() to pure asm
This function consists entirely of inline asm statements, so writing it directly in a .S file is simpler. Additionally, the inline asm is not safe as is, since registers are not guaranteed to be preserved between asm() statements. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Steve Sakoman <steve@sakoman.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Mans Rullgard · Sandeep Paulraj
1 parent 2984470746
Showing 2 changed files with 19 additions and 35 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap3/board.c
arch/arm/cpu/armv7/omap3/cache.S
@@ -120,41 +120,6 @@
 }
  
 /******************************************************************************
- * Routine: setup_auxcr()
- * Description: Write to AuxCR desired value using SMI.
- *              general use.
- *****************************************************************************/
-void setup_auxcr()
-{
-	unsigned long i;
-	volatile unsigned int j;
-	/* Save r0, r12 and restore them after usage */
-	__asm__ __volatile__("mov %0, r12":"=r"(j));
-	__asm__ __volatile__("mov %0, r0":"=r"(i));
-
-	/*
-	 * GP Device ROM code API usage here
-	 * r12 = AUXCR Write function and r0 value
-	 */
-	__asm__ __volatile__("mov r12, #0x3");
-	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-	/* Enabling ASA */
-	__asm__ __volatile__("orr r0, r0, #0x10");
-	/* Enable L1NEON */
-	__asm__ __volatile__("orr r0, r0, #1 << 5");
-	/* SMI instruction to call ROM Code API */
-	__asm__ __volatile__(".word 0xE1600070");
-	/* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
-	__asm__ __volatile__("mov r12, #0x2");
-	__asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
-	__asm__ __volatile__("orr r0, r0, #1 << 27");
-	/* SMI instruction to call ROM Code API */
-	__asm__ __volatile__(".word 0xE1600070");
-	__asm__ __volatile__("mov r0, %0":"=r"(i));
-	__asm__ __volatile__("mov r12, %0":"=r"(j));
-}
-
-/******************************************************************************
  * Routine: try_unlock_sram()
  * Description: If chip is GP/EMU(special) type, unlock the SRAM for
  *              general use.
@@ -43,6 +43,7 @@
 .global invalidate_dcache
 .global l2_cache_enable
 .global l2_cache_disable
+.global setup_auxcr
  
 /*
  *	invalidate_dcache()
@@ -155,4 +156,22 @@
 l2_cache_disable:
 	mov	r0, #0
 	b	l2_cache_set
+
+/******************************************************************************
+ * Routine: setup_auxcr()
+ * Description: Write to AuxCR desired value using SMI.
+ *              general use.
+ *****************************************************************************/
+setup_auxcr:
+	mov	r12, #0x3
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #0x10			@ Enable ASA
+	orr	r0, r0, #1 << 5			@ Enable L1NEON
+	.word 0xE1600070			@ SMC
+	mov	r12, #0x2
+	mrc	p15, 1, r0, c9, c0, 2
+	@ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
+	orr	r0, r0, #1 << 27
+	.word 0xE1600070			@ SMC
+	bx	lr
...	...	@@ -120,41 +120,6 @@
120	120	}
121	121
122	122	/******************************************************************************
123		- * Routine: setup_auxcr()
124		- * Description: Write to AuxCR desired value using SMI.
125		- * general use.
126		- *****************************************************************************/
127		-void setup_auxcr()
128		-{
129		- unsigned long i;
130		- volatile unsigned int j;
131		- /* Save r0, r12 and restore them after usage */
132		- __asm__ __volatile__("mov %0, r12":"=r"(j));
133		- __asm__ __volatile__("mov %0, r0":"=r"(i));
134		-
135		- /*
136		- * GP Device ROM code API usage here
137		- * r12 = AUXCR Write function and r0 value
138		- */
139		- __asm__ __volatile__("mov r12, #0x3");
140		- __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
141		- /* Enabling ASA */
142		- __asm__ __volatile__("orr r0, r0, #0x10");
143		- /* Enable L1NEON */
144		- __asm__ __volatile__("orr r0, r0, #1 << 5");
145		- /* SMI instruction to call ROM Code API */
146		- __asm__ __volatile__(".word 0xE1600070");
147		- /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
148		- __asm__ __volatile__("mov r12, #0x2");
149		- __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
150		- __asm__ __volatile__("orr r0, r0, #1 << 27");
151		- /* SMI instruction to call ROM Code API */
152		- __asm__ __volatile__(".word 0xE1600070");
153		- __asm__ __volatile__("mov r0, %0":"=r"(i));
154		- __asm__ __volatile__("mov r12, %0":"=r"(j));
155		-}
156		-
157		-/******************************************************************************
158	123	* Routine: try_unlock_sram()
159	124	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
160	125	* general use.
...	...	@@ -43,6 +43,7 @@
43	43	.global invalidate_dcache
44	44	.global l2_cache_enable
45	45	.global l2_cache_disable
	46	+.global setup_auxcr
46	47
47	48	/*
48	49	* invalidate_dcache()
...	...	@@ -155,4 +156,22 @@
155	156	l2_cache_disable:
156	157	mov r0, #0
157	158	b l2_cache_set
	159	+
	160	+/******************************************************************************
	161	+ * Routine: setup_auxcr()
	162	+ * Description: Write to AuxCR desired value using SMI.
	163	+ * general use.
	164	+ *****************************************************************************/
	165	+setup_auxcr:
	166	+ mov r12, #0x3
	167	+ mrc p15, 0, r0, c1, c0, 1
	168	+ orr r0, r0, #0x10 @ Enable ASA
	169	+ orr r0, r0, #1 << 5 @ Enable L1NEON
	170	+ .word 0xE1600070 @ SMC
	171	+ mov r12, #0x2
	172	+ mrc p15, 1, r0, c9, c0, 2
	173	+ @ Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround)
	174	+ orr r0, r0, #1 << 27
	175	+ .word 0xE1600070 @ SMC
	176	+ bx lr