arm: vf610: Add clock support for DSPI

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Bhuvanchandra DV · Stefano Babic
1 parent 30748d81d0
Showing 3 changed files with 12 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/vf610/generic.c
arch/arm/include/asm/arch-vf610/clock.h
arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -198,6 +198,11 @@
 	return get_ipg_clk();
 }
  
+static u32 get_dspi_clk(void)
+{
+	return get_ipg_clk();
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
@@ -215,6 +220,8 @@
 		return get_fec_clk();
 	case MXC_I2C_CLK:
 		return get_i2c_clk();
+	case MXC_DSPI_CLK:
+		return get_dspi_clk();
 	default:
 		break;
 	}
@@ -17,6 +17,7 @@
 	MXC_ESDHC_CLK,
 	MXC_FEC_CLK,
 	MXC_I2C_CLK,
+	MXC_DSPI_CLK,
 };
  
 void enable_ocotp_clk(unsigned char enable);
@@ -189,6 +189,8 @@
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
@@ -206,6 +208,8 @@
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK		(0x3 << 12)
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK		(0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
 #define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
...	...	@@ -198,6 +198,11 @@
198	198	return get_ipg_clk();
199	199	}
200	200
	201	+static u32 get_dspi_clk(void)
	202	+{
	203	+ return get_ipg_clk();
	204	+}
	205	+
201	206	unsigned int mxc_get_clock(enum mxc_clock clk)
202	207	{
203	208	switch (clk) {
...	...	@@ -215,6 +220,8 @@
215	220	return get_fec_clk();
216	221	case MXC_I2C_CLK:
217	222	return get_i2c_clk();
	223	+ case MXC_DSPI_CLK:
	224	+ return get_dspi_clk();
218	225	default:
219	226	break;
220	227	}
...	...	@@ -17,6 +17,7 @@
17	17	MXC_ESDHC_CLK,
18	18	MXC_FEC_CLK,
19	19	MXC_I2C_CLK,
	20	+ MXC_DSPI_CLK,
20	21	};
21	22
22	23	void enable_ocotp_clk(unsigned char enable);
...	...	@@ -189,6 +189,8 @@
189	189	#define CCM_REG_CTRL_MASK 0xffffffff
190	190	#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
191	191	#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
	192	+#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
	193	+#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
192	194	#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
193	195	#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
194	196	#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
...	...	@@ -206,6 +208,8 @@
206	208	#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
207	209	#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
208	210	#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
	211	+#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
	212	+#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
209	213	#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
210	214	#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
211	215	#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)