Add support for eTSEC 3 & 4 on 8548 CDS

* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems

Add support for eTSEC 3 & 4 on 8548 CDS
* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS. This will only work on rev 1.3 boards (but doesn't break older boards) * Cleaned up some comments to reflect the expanded role of tsec in other systems
Andy Fleming · Jon Loeliger
1 parent 084d648b10
Showing 4 changed files with 111 additions and 11 deletions Side-by-side Diff
board/cds/mpc8548cds/mpc8548cds.c
drivers/tsec.c
drivers/tsec.h
include/configs/MPC8548CDS.h
@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
 #include <spd.h>
+#include <miiphy.h>
  
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"
@@ -326,5 +327,36 @@
  
 	pci_mpc85xx_init(&hose);
 #endif
+}
+
+int last_stage_init(void)
+{
+	unsigned int temp;
+
+	/* Change the resistors for the PHY */
+	/* This is needed to get the RGMII working for the 1.3+
+	 * CDS cards */
+	if (get_board_version() ==  0x13) {
+		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 29, 18);
+
+		miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, &temp);
+
+		temp = (temp & 0xf03f);
+		temp |= 2 << 9;		/* 36 ohm */
+		temp |= 2 << 6;		/* 39 ohm */
+
+		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, temp);
+
+		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 29, 3);
+
+		miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
+				TSEC1_PHY_ADDR, 30, 0x8000);
+	}
+
+	return 0;
 }
@@ -44,9 +44,7 @@
  
 /* The tsec_info structure contains 3 values which the
  * driver uses to determine how to operate a given ethernet
- * device.  For now, the structure is initialized with the
- * knowledge that all current implementations have 2 TSEC
- * devices, and one FEC.  The information needed is:
+ * device. The information needed is:
  *  phyaddr - The address of the PHY which is attached to
  *	the given device.
  *
  
  
@@ -56,18 +54,16 @@
  *
  *  phyregidx - This variable specifies which ethernet device
  *	controls the MII Management registers which are connected
- *	to the PHY.  For 8540/8560, only TSEC1 (index 0) has
+ *	to the PHY.  For now, only TSEC1 (index 0) has
  *	access to the PHYs, so all of the entries have "0".
  *
  * The values specified in the table are taken from the board's
  * config file in include/configs/.  When implementing a new
  * board with ethernet capability, it is necessary to define:
- *   TSEC1_PHY_ADDR
- *   TSEC1_PHYIDX
- *   TSEC2_PHY_ADDR
- *   TSEC2_PHYIDX
+ *   TSECn_PHY_ADDR
+ *   TSECn_PHYIDX
  *
- * and for 8560:
+ * for n = 1,2,3, etc.  And for FEC:
  *   FEC_PHY_ADDR
  *   FEC_PHYIDX
  */
@@ -91,7 +87,7 @@
 	{ 0, 0, 0},
 #    endif
 #    if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
-	{TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
+	{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
 #    else
 	{ 0, 0, 0},
 #    endif
@@ -805,6 +801,58 @@
 	},
 };
  
+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
+{
+	unsigned int temp;
+	uint mii_data = read_phy_reg(priv, mii_reg);
+
+
+	/* Setting MIIM_88E1145_PHY_EXT_CR */
+	if (priv->flags & TSEC_REDUCED)
+		return mii_data |
+			MIIM_M88E1145_RGMII_RX_DELAY |
+			MIIM_M88E1145_RGMII_TX_DELAY;
+	else
+		return mii_data;
+}
+
+static struct phy_info phy_info_M88E1145 = {
+	0x01410cd,
+	"Marvell 88E1145",
+	4,
+	(struct phy_cmd[]) { /* config */
+		/* Errata E0, E1 */
+		{29, 0x001b, NULL},
+		{30, 0x418f, NULL},
+		{29, 0x0016, NULL},
+		{30, 0xa2da, NULL},
+
+		/* Reset and configure the PHY */
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
+		{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
+		{MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
+		{MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
+		{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
+		{MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* startup */
+		/* Status is read once to clear old link state */
+		{MIIM_STATUS, miim_read, NULL},
+		/* Auto-negotiate */
+		{MIIM_STATUS, miim_read, &mii_parse_sr},
+		{MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
+		/* Read the Status */
+		{MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
+		{miim_end,}
+	},
+	(struct phy_cmd[]) { /* shutdown */
+		{miim_end,}
+	},
+};
+
+
 struct phy_info phy_info_cis8204 = {
 	0x3f11,
 	"Cicada Cis8204",
@@ -999,6 +1047,7 @@
 	&phy_info_cis8204,
 	&phy_info_M88E1011S,
 	&phy_info_M88E1111S,
+	&phy_info_M88E1145,
 	&phy_info_dm9161,
 	&phy_info_lxt971,
 	&phy_info_dp83865,
@@ -142,6 +142,23 @@
 #define MIIM_88E1011_PHYSTAT_SPDDONE	0x0800
 #define MIIM_88E1011_PHYSTAT_LINK	0x0400
  
+#define MIIM_88E1011_PHY_SCR		0x10
+#define MIIM_88E1011_PHY_MDI_X_AUTO	0x0060
+
+/* 88E1111 PHY LED Control Register */
+#define MIIM_88E1111_PHY_LED_CONTROL   24
+#define MIIM_88E1111_PHY_LED_DIRECT    0x4100
+#define MIIM_88E1111_PHY_LED_COMBINE   0x411C
+
+/* 88E1145 Extended PHY Specific Control Register */
+#define MIIM_88E1145_PHY_EXT_CR 20
+#define MIIM_M88E1145_RGMII_RX_DELAY	0x0080
+#define MIIM_M88E1145_RGMII_TX_DELAY	0x0002
+
+#define MIIM_88E1145_PHY_PAGE   29
+#define MIIM_88E1145_PHY_CAL_OV 30
+
+
 /* DM9161 Control register values */
 #define MIIM_DM9161_CR_STOP	0x0400
 #define MIIM_DM9161_CR_RSTAN	0x1200
@@ -381,7 +381,7 @@
 #define CONFIG_MPC85XX_TSEC2_NAME	"eTSEC1"
 #define CONFIG_MPC85XX_TSEC3	1
 #define CONFIG_MPC85XX_TSEC3_NAME	"eTSEC2"
-#undef CONFIG_MPC85XX_TSEC4
+#define CONFIG_MPC85XX_TSEC4	1
 #define CONFIG_MPC85XX_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
  
@@ -483,6 +483,8 @@
 #define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
 #define CONFIG_HAS_ETH2
 #define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR  00:E0:0C:00:03:FD
 #endif
  
 #define CONFIG_IPADDR    192.168.1.253
...	...	@@ -27,6 +27,7 @@
27	27	#include <asm/processor.h>
28	28	#include <asm/immap_85xx.h>
29	29	#include <spd.h>
	30	+#include <miiphy.h>
30	31
31	32	#include "../common/cadmus.h"
32	33	#include "../common/eeprom.h"
...	...	@@ -326,5 +327,36 @@
326	327
327	328	pci_mpc85xx_init(&hose);
328	329	#endif
	330	+}
	331	+
	332	+int last_stage_init(void)
	333	+{
	334	+ unsigned int temp;
	335	+
	336	+ /* Change the resistors for the PHY */
	337	+ /* This is needed to get the RGMII working for the 1.3+
	338	+ * CDS cards */
	339	+ if (get_board_version() == 0x13) {
	340	+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
	341	+ TSEC1_PHY_ADDR, 29, 18);
	342	+
	343	+ miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
	344	+ TSEC1_PHY_ADDR, 30, &temp);
	345	+
	346	+ temp = (temp & 0xf03f);
	347	+ temp \|= 2 << 9; /* 36 ohm */
	348	+ temp \|= 2 << 6; /* 39 ohm */
	349	+
	350	+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
	351	+ TSEC1_PHY_ADDR, 30, temp);
	352	+
	353	+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
	354	+ TSEC1_PHY_ADDR, 29, 3);
	355	+
	356	+ miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
	357	+ TSEC1_PHY_ADDR, 30, 0x8000);
	358	+ }
	359	+
	360	+ return 0;
329	361	}
...	...	@@ -44,9 +44,7 @@
44	44
45	45	/* The tsec_info structure contains 3 values which the
46	46	* driver uses to determine how to operate a given ethernet
47		- * device. For now, the structure is initialized with the
48		- * knowledge that all current implementations have 2 TSEC
49		- * devices, and one FEC. The information needed is:
	47	+ * device. The information needed is:
50	48	* phyaddr - The address of the PHY which is attached to
51	49	* the given device.
52	50	*
53	51
54	52
...	...	@@ -56,18 +54,16 @@
56	54	*
57	55	* phyregidx - This variable specifies which ethernet device
58	56	* controls the MII Management registers which are connected
59		- * to the PHY. For 8540/8560, only TSEC1 (index 0) has
	57	+ * to the PHY. For now, only TSEC1 (index 0) has
60	58	* access to the PHYs, so all of the entries have "0".
61	59	*
62	60	* The values specified in the table are taken from the board's
63	61	* config file in include/configs/. When implementing a new
64	62	* board with ethernet capability, it is necessary to define:
65		- * TSEC1_PHY_ADDR
66		- * TSEC1_PHYIDX
67		- * TSEC2_PHY_ADDR
68		- * TSEC2_PHYIDX
	63	+ * TSECn_PHY_ADDR
	64	+ * TSECn_PHYIDX
69	65	*
70		- * and for 8560:
	66	+ * for n = 1,2,3, etc. And for FEC:
71	67	* FEC_PHY_ADDR
72	68	* FEC_PHYIDX
73	69	*/
...	...	@@ -91,7 +87,7 @@
91	87	{ 0, 0, 0},
92	88	# endif
93	89	# if defined(CONFIG_MPC85XX_TSEC4) \|\| defined(CONFIG_MPC83XX_TSEC4)
94		- {TSEC4_PHY_ADDR, TSEC_REDUCED, TSEC4_PHYIDX},
	90	+ {TSEC4_PHY_ADDR, TSEC_GIGABIT \| TSEC_REDUCED, TSEC4_PHYIDX},
95	91	# else
96	92	{ 0, 0, 0},
97	93	# endif
...	...	@@ -805,6 +801,58 @@
805	801	},
806	802	};
807	803
	804	+static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
	805	+{
	806	+ unsigned int temp;
	807	+ uint mii_data = read_phy_reg(priv, mii_reg);
	808	+
	809	+
	810	+ /* Setting MIIM_88E1145_PHY_EXT_CR */
	811	+ if (priv->flags & TSEC_REDUCED)
	812	+ return mii_data \|
	813	+ MIIM_M88E1145_RGMII_RX_DELAY \|
	814	+ MIIM_M88E1145_RGMII_TX_DELAY;
	815	+ else
	816	+ return mii_data;
	817	+}
	818	+
	819	+static struct phy_info phy_info_M88E1145 = {
	820	+ 0x01410cd,
	821	+ "Marvell 88E1145",
	822	+ 4,
	823	+ (struct phy_cmd[]) { /* config */
	824	+ /* Errata E0, E1 */
	825	+ {29, 0x001b, NULL},
	826	+ {30, 0x418f, NULL},
	827	+ {29, 0x0016, NULL},
	828	+ {30, 0xa2da, NULL},
	829	+
	830	+ /* Reset and configure the PHY */
	831	+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
	832	+ {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
	833	+ {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
	834	+ {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
	835	+ {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
	836	+ {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
	837	+ {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
	838	+ {miim_end,}
	839	+ },
	840	+ (struct phy_cmd[]) { /* startup */
	841	+ /* Status is read once to clear old link state */
	842	+ {MIIM_STATUS, miim_read, NULL},
	843	+ /* Auto-negotiate */
	844	+ {MIIM_STATUS, miim_read, &mii_parse_sr},
	845	+ {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
	846	+ /* Read the Status */
	847	+ {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
	848	+ {miim_end,}
	849	+ },
	850	+ (struct phy_cmd[]) { /* shutdown */
	851	+ {miim_end,}
	852	+ },
	853	+};
	854	+
	855	+
808	856	struct phy_info phy_info_cis8204 = {
809	857	0x3f11,
810	858	"Cicada Cis8204",
...	...	@@ -999,6 +1047,7 @@
999	1047	&phy_info_cis8204,
1000	1048	&phy_info_M88E1011S,
1001	1049	&phy_info_M88E1111S,
	1050	+ &phy_info_M88E1145,
1002	1051	&phy_info_dm9161,
1003	1052	&phy_info_lxt971,
1004	1053	&phy_info_dp83865,
...	...	@@ -142,6 +142,23 @@
142	142	#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
143	143	#define MIIM_88E1011_PHYSTAT_LINK 0x0400
144	144
	145	+#define MIIM_88E1011_PHY_SCR 0x10
	146	+#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
	147	+
	148	+/* 88E1111 PHY LED Control Register */
	149	+#define MIIM_88E1111_PHY_LED_CONTROL 24
	150	+#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
	151	+#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
	152	+
	153	+/* 88E1145 Extended PHY Specific Control Register */
	154	+#define MIIM_88E1145_PHY_EXT_CR 20
	155	+#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
	156	+#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
	157	+
	158	+#define MIIM_88E1145_PHY_PAGE 29
	159	+#define MIIM_88E1145_PHY_CAL_OV 30
	160	+
	161	+
145	162	/* DM9161 Control register values */
146	163	#define MIIM_DM9161_CR_STOP 0x0400
147	164	#define MIIM_DM9161_CR_RSTAN 0x1200
...	...	@@ -381,7 +381,7 @@
381	381	#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
382	382	#define CONFIG_MPC85XX_TSEC3 1
383	383	#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
384		-#undef CONFIG_MPC85XX_TSEC4
	384	+#define CONFIG_MPC85XX_TSEC4 1
385	385	#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
386	386	#undef CONFIG_MPC85XX_FEC
387	387
...	...	@@ -483,6 +483,8 @@
483	483	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
484	484	#define CONFIG_HAS_ETH2
485	485	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
	486	+#define CONFIG_HAS_ETH3
	487	+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
486	488	#endif
487	489
488	490	#define CONFIG_IPADDR 192.168.1.253