rockchip: Adjust rk3399 device tree to be closer to linux

This file has changed upstream, with some additions and changes. Move the U-Boot version towards this. Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

rockchip: Adjust rk3399 device tree to be closer to linux
This file has changed upstream, with some additions and changes. Move the U-Boot version towards this. Some USB changes seem to be incompatible with how the bindings work on rockchip in U-Boot. Testing is needed to make sure that USB still works correct, and adjust the code (not device tree) if not. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Simon Glass · Philipp Tomsich
1 parent d244474f38
Showing 1 changed file with 371 additions and 61 deletions Side-by-side Diff
arch/arm/dts/rk3399.dtsi
@@ -349,46 +349,106 @@
 		status = "disabled";
 	};
  
-	dwc3_typec0: usb@fe800000 {
-		compatible = "rockchip,rk3399-xhci";
-		reg = <0x0 0xfe800000 0x0 0x100000>;
+	usbdrd3_0: dwc3_typec0: usb@fe800000 {
+		compatible = "rockchip,rk3399-dwc3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+			 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "aclk_usb3_rksoc_axi_perf",
+			      "aclk_usb3", "grf_clk";
+		resets = <&cru SRST_A_USB3_OTG0>;
+		reset-names = "usb3-otg";
 		status = "disabled";
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
  
+		usbdrd_dwc3_0: dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe800000 0x0 0x100000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "otg";
+			phys = <&u2phy0_otg>, <&tcphy0_usb3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			power-domains = <&power RK3399_PD_USB3>;
+			status = "disabled";
+		};
+	};
+
+	dwc3_typec1: usbdrd3_1: usb@fe900000 {
+		compatible = "rockchip,rk3399-dwc3";
 		#address-cells = <2>;
 		#size-cells = <2>;
-		hub {
-			compatible = "usb-hub";
-			usb,device-class = <USB_CLASS_HUB>;
+		ranges;
+		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+			 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "aclk_usb3_rksoc_axi_perf",
+			      "aclk_usb3", "grf_clk";
+		resets = <&cru SRST_A_USB3_OTG1>;
+		reset-names = "usb3-otg";
+		status = "disabled";
+
+		usbdrd_dwc3_1: dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe900000 0x0 0x100000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
+			dr_mode = "otg";
+			phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+			phy-names = "usb2-phy", "usb3-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			power-domains = <&power RK3399_PD_USB3>;
+			status = "disabled";
 		};
-		typec_phy0 {
-			compatible = "rockchip,rk3399-usb3-phy";
-			reg = <0x0 0xff7c0000 0x0 0x40000>;
-		};
 	};
  
-	dwc3_typec1: usb@fe900000 {
-		compatible = "rockchip,rk3399-xhci";
-		reg = <0x0 0xfe900000 0x0 0x100000>;
+	cdn_dp: dp@fec00000 {
+		compatible = "rockchip,rk3399-cdn-dp";
+		reg = <0x0 0xfec00000 0x0 0x100000>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+		assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
+		assigned-clock-rates = <100000000>, <200000000>;
+		clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
+			 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
+		clock-names = "core-clk", "pclk", "spdif", "grf";
+		phys = <&tcphy0_dp>, <&tcphy1_dp>;
+		power-domains = <&power RK3399_PD_HDCP>;
+		resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
+			 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
+		reset-names = "spdif", "dptx", "apb", "core";
+		rockchip,grf = <&grf>;
+		#sound-dai-cells = <1>;
 		status = "disabled";
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
  
-		#address-cells = <2>;
-		#size-cells = <2>;
-		hub {
-			compatible = "usb-hub";
-			usb,device-class = <USB_CLASS_HUB>;
+		ports {
+			dp_in: port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_dp>;
+				};
+
+				dp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_dp>;
+				};
+			};
 		};
-		typec_phy1 {
-			compatible = "rockchip,rk3399-usb3-phy";
-			reg = <0x0 0xff800000 0x0 0x40000>;
-		};
 	};
  
 	gic: interrupt-controller@fee00000 {
@@ -1054,6 +1114,21 @@
 		status = "disabled";
 	};
  
+	i2c0: i2c@ff3c0000 {
+		compatible = "rockchip,rk3399-i2c";
+		reg = <0x0 0xff3c0000 0x0 0x1000>;
+		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
+		assigned-clock-rates = <200000000>;
+		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
+		clock-names = "i2c", "pclk";
+		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0_xfer>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	i2c4: i2c@ff3d0000 {
 		compatible = "rockchip,rk3399-i2c";
 		reg = <0x0 0xff3d0000 0x0 0x1000>;
@@ -1217,7 +1292,10 @@
 			<&cru PCLK_PERIHP>,
 			<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 			<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
-			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
+			<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
+			<&cru ACLK_VIO>, <&cru ACLK_HDCP>,
+			<&cru ACLK_GIC_PRE>,
+			<&cru PCLK_DDR>;
 		assigned-clock-rates =
 			 <594000000>,  <800000000>,
 			<1000000000>,
@@ -1225,7 +1303,10 @@
 			  <37500000>,
 			 <100000000>,  <100000000>,
 			  <50000000>, <600000000>,
-			 <100000000>,   <50000000>;
+			 <100000000>,   <50000000>,
+			 <400000000>, <400000000>,
+			 <200000000>,
+			 <200000000>;
 	};
  
 	grf: syscon@ff770000 {
@@ -1314,6 +1395,56 @@
 		};
 	};
  
+	tcphy0: phy@ff7c0000 {
+		compatible = "rockchip,rk3399-typec-phy";
+		reg = <0x0 0xff7c0000 0x0 0x40000>;
+		clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+			 <&cru SCLK_UPHY0_TCPDPHY_REF>;
+		clock-names = "tcpdcore", "tcpdphy-ref";
+		assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
+		assigned-clock-rates = <50000000>;
+		power-domains = <&power RK3399_PD_TCPD0>;
+		resets = <&cru SRST_UPHY0>,
+			 <&cru SRST_UPHY0_PIPE_L00>,
+			 <&cru SRST_P_UPHY0_TCPHY>;
+		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		tcphy0_dp: dp-port {
+			#phy-cells = <0>;
+		};
+
+		tcphy0_usb3: usb3-port {
+			#phy-cells = <0>;
+		};
+	};
+
+	tcphy1: phy@ff800000 {
+		compatible = "rockchip,rk3399-typec-phy";
+		reg = <0x0 0xff800000 0x0 0x40000>;
+		clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+			 <&cru SCLK_UPHY1_TCPDPHY_REF>;
+		clock-names = "tcpdcore", "tcpdphy-ref";
+		assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
+		assigned-clock-rates = <50000000>;
+		power-domains = <&power RK3399_PD_TCPD1>;
+		resets = <&cru SRST_UPHY1>,
+			 <&cru SRST_UPHY1_PIPE_L00>,
+			 <&cru SRST_P_UPHY1_TCPHY>;
+		reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		tcphy1_dp: dp-port {
+			#phy-cells = <0>;
+		};
+
+		tcphy1_usb3: usb3-port {
+			#phy-cells = <0>;
+		};
+	};
+
 	watchdog@ff848000 {
 		compatible = "snps,dw-wdt";
 		reg = <0x0 0xff848000 0x0 0x100>;
@@ -1340,6 +1471,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&spdif_bus>;
 		power-domains = <&power RK3399_PD_SDIOAUDIO>;
+		#sound-dai-cells = <0>;
 		status = "disabled";
 	};
  
@@ -1355,6 +1487,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s0_8ch_bus>;
 		power-domains = <&power RK3399_PD_SDIOAUDIO>;
+		#sound-dai-cells = <0>;
 		status = "disabled";
 	};
  
@@ -1369,6 +1502,7 @@
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2s1_2ch_bus>;
 		power-domains = <&power RK3399_PD_SDIOAUDIO>;
+		#sound-dai-cells = <0>;
 		status = "disabled";
 	};
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -1381,92 +1515,186 @@
 		clock-names = "i2s_clk", "i2s_hclk";
 		clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 		power-domains = <&power RK3399_PD_SDIOAUDIO>;
+		#sound-dai-cells = <0>;
 		status = "disabled";
 	};
  
-	i2c0: i2c@ff3c0000 {
-		compatible = "rockchip,rk3399-i2c";
-		reg = <0x0 0xff3c0000 0x0 0x1000>;
-		assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
-		assigned-clock-rates = <200000000>;
-		clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
-		clock-names = "i2c", "pclk";
-		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&i2c0_xfer>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
 	vopl: vop@ff8f0000 {
 		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3399-vop-lit";
 		reg = <0x0 0xff8f0000 0x0 0x3efc>;
 		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+		assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+		assigned-clock-rates = <400000000>, <100000000>;
 		clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		iommus = <&vopl_mmu>;
+		power-domains = <&power RK3399_PD_VOPL>;
 		resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 		reset-names = "axi", "ahb", "dclk";
 		status = "disabled";
+
 		vopl_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
+
 			vopl_out_mipi: endpoint@0 {
-				reg = <3>;
+				reg = <0>;
 				remote-endpoint = <&mipi_in_vopl>;
 			};
  
-			vopl_out_hdmi: endpoint@1 {
+			vopl_out_edp: endpoint@1 {
 				reg = <1>;
+				remote-endpoint = <&edp_in_vopl>;
+			};
+
+			vopl_out_hdmi: endpoint@2 {
+				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopl>;
 			};
+
+			vopl_out_mipi1: endpoint@3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopl>;
+			};
+
+			vopl_out_dp: endpoint@4 {
+				reg = <4>;
+				remote-endpoint = <&dp_in_vopl>;
+			};
 		};
 	};
  
+	vopl_mmu: iommu@ff8f3f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff8f3f00 0x0 0x100>;
+		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "vopl_mmu";
+		clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RK3399_PD_VOPL>;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	vopb: vop@ff900000 {
 		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3399-vop-big";
 		reg = <0x0 0xff900000 0x0 0x3efc>;
 		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+		assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+		assigned-clock-rates = <400000000>, <100000000>;
 		clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
-		#clock-cells = <0>;
 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+		iommus = <&vopb_mmu>;
+		power-domains = <&power RK3399_PD_VOPB>;
 		resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 		reset-names = "axi", "ahb", "dclk";
 		status = "disabled";
+
 		vopb_out: port {
 			#address-cells = <1>;
 			#size-cells = <0>;
-			vopb_out_mipi: endpoint@0 {
-				reg = <3>;
-				remote-endpoint = <&mipi_in_vopb>;
+
+			vopb_out_edp: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&edp_in_vopb>;
 			};
  
-			vopb_out_hdmi: endpoint@1 {
+			vopb_out_mipi: endpoint@1 {
 				reg = <1>;
+				remote-endpoint = <&mipi_in_vopb>;
+			};
+
+			vopb_out_hdmi: endpoint@2 {
+				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopb>;
 			};
+
+			vopb_out_mipi1: endpoint@3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopb>;
+			};
+
+			vopb_out_dp: endpoint@4 {
+				reg = <4>;
+				remote-endpoint = <&dp_in_vopb>;
+			};
 		};
 	};
  
+	vopb_mmu: iommu@ff903f00 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff903f00 0x0 0x100>;
+		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "vopb_mmu";
+		clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RK3399_PD_VOPB>;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
+	isp0_mmu: iommu@ff914000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
+		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "isp0_mmu";
+		clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+	};
+
+	isp1_mmu: iommu@ff924000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
+		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "isp1_mmu";
+		clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+	};
+
+	hdmi_sound: hdmi-sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,format = "i2s";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "hdmi-sound";
+		status = "disabled";
+
+		simple-audio-card,cpu {
+			sound-dai = <&i2s2>;
+		};
+		simple-audio-card,codec {
+			sound-dai = <&hdmi>;
+		};
+	};
+
 	hdmi: hdmi@ff940000 {
 		compatible = "rockchip,rk3399-dw-hdmi";
 		reg = <0x0 0xff940000 0x0 0x20000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru PCLK_HDMI_CTRL>,
+			 <&cru SCLK_HDMI_SFR>,
+			 <&cru PLL_VPLL>,
+			 <&cru PCLK_VIO_GRF>,
+			 <&cru SCLK_HDMI_CEC>;
+		clock-names = "iahb", "isfr", "vpll", "grf", "cec";
+		power-domains = <&power RK3399_PD_HDCP>;
 		reg-io-width = <4>;
 		rockchip,grf = <&grf>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&hdmi_i2c_xfer>;
-		power-domains = <&power RK3399_PD_HDCP>;
-		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
-		clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
-		clock-names = "iahb", "isfr", "vpll", "grf";
+		#sound-dai-cells = <0>;
 		status = "disabled";
  
 		ports {
 			hdmi_in: port {
 				#address-cells = <1>;
 				#size-cells = <0>;
+
 				hdmi_in_vopb: endpoint@0 {
 					reg = <0>;
 					remote-endpoint = <&vopb_out_hdmi>;
@@ -1507,6 +1735,88 @@
 		};
 	};
  
+	mipi_dsi1: mipi@ff968000 {
+		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff968000 0x0 0x8000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+			 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
+		clock-names = "ref", "pclk", "phy_cfg", "grf";
+		power-domains = <&power RK3399_PD_VIO>;
+		resets = <&cru SRST_P_MIPI_DSI1>;
+		reset-names = "apb";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi1_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mipi1_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi1>;
+				};
+
+				mipi1_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi1>;
+				};
+			};
+		};
+	};
+
+	edp: edp@ff970000 {
+		compatible = "rockchip,rk3399-edp";
+		reg = <0x0 0xff970000 0x0 0x8000>;
+		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
+		clock-names = "dp", "pclk", "grf";
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+		power-domains = <&power RK3399_PD_EDP>;
+		resets = <&cru SRST_P_EDP_CTRL>;
+		reset-names = "dp";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+		};
+	};
+
+	gpu: gpu@ff9a0000 {
+		compatible = "rockchip,rk3399-mali", "arm,mali-t860";
+		reg = <0x0 0xff9a0000 0x0 0x10000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "gpu", "job", "mmu";
+		clocks = <&cru ACLK_GPU>;
+		power-domains = <&power RK3399_PD_GPU>;
+		status = "disabled";
+	};
+
 	pinctrl: pinctrl {
 		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3399-pinctrl";
@@ -1911,7 +2221,7 @@
 					<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
 			};
  
-			sdmmc_cd: sdmcc-cd {
+			sdmmc_cd: sdmmc-cd {
 				rockchip,pins =
 					<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
 			};
...	...	@@ -349,46 +349,106 @@
349	349	status = "disabled";
350	350	};
351	351
352		- dwc3_typec0: usb@fe800000 {
353		- compatible = "rockchip,rk3399-xhci";
354		- reg = <0x0 0xfe800000 0x0 0x100000>;
	352	+ usbdrd3_0: dwc3_typec0: usb@fe800000 {
	353	+ compatible = "rockchip,rk3399-dwc3";
	354	+ #address-cells = <2>;
	355	+ #size-cells = <2>;
	356	+ ranges;
	357	+ clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
	358	+ <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	359	+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
	360	+ clock-names = "ref_clk", "suspend_clk",
	361	+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
	362	+ "aclk_usb3", "grf_clk";
	363	+ resets = <&cru SRST_A_USB3_OTG0>;
	364	+ reset-names = "usb3-otg";
355	365	status = "disabled";
356		- snps,dis-enblslpm-quirk;
357		- snps,phyif-utmi-bits = <16>;
358		- snps,dis-u2-freeclk-exists-quirk;
359		- snps,dis-u2-susphy-quirk;
360	366
	367	+ usbdrd_dwc3_0: dwc3 {
	368	+ compatible = "snps,dwc3";
	369	+ reg = <0x0 0xfe800000 0x0 0x100000>;
	370	+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
	371	+ dr_mode = "otg";
	372	+ phys = <&u2phy0_otg>, <&tcphy0_usb3>;
	373	+ phy-names = "usb2-phy", "usb3-phy";
	374	+ phy_type = "utmi_wide";
	375	+ snps,dis_enblslpm_quirk;
	376	+ snps,dis-u2-freeclk-exists-quirk;
	377	+ snps,dis_u2_susphy_quirk;
	378	+ snps,dis-del-phy-power-chg-quirk;
	379	+ snps,dis-tx-ipgap-linecheck-quirk;
	380	+ power-domains = <&power RK3399_PD_USB3>;
	381	+ status = "disabled";
	382	+ };
	383	+ };
	384	+
	385	+ dwc3_typec1: usbdrd3_1: usb@fe900000 {
	386	+ compatible = "rockchip,rk3399-dwc3";
361	387	#address-cells = <2>;
362	388	#size-cells = <2>;
363		- hub {
364		- compatible = "usb-hub";
365		- usb,device-class = <USB_CLASS_HUB>;
	389	+ ranges;
	390	+ clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
	391	+ <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
	392	+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
	393	+ clock-names = "ref_clk", "suspend_clk",
	394	+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
	395	+ "aclk_usb3", "grf_clk";
	396	+ resets = <&cru SRST_A_USB3_OTG1>;
	397	+ reset-names = "usb3-otg";
	398	+ status = "disabled";
	399	+
	400	+ usbdrd_dwc3_1: dwc3 {
	401	+ compatible = "snps,dwc3";
	402	+ reg = <0x0 0xfe900000 0x0 0x100000>;
	403	+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
	404	+ dr_mode = "otg";
	405	+ phys = <&u2phy1_otg>, <&tcphy1_usb3>;
	406	+ phy-names = "usb2-phy", "usb3-phy";
	407	+ phy_type = "utmi_wide";
	408	+ snps,dis_enblslpm_quirk;
	409	+ snps,dis-u2-freeclk-exists-quirk;
	410	+ snps,dis_u2_susphy_quirk;
	411	+ snps,dis-del-phy-power-chg-quirk;
	412	+ snps,dis-tx-ipgap-linecheck-quirk;
	413	+ power-domains = <&power RK3399_PD_USB3>;
	414	+ status = "disabled";
366	415	};
367		- typec_phy0 {
368		- compatible = "rockchip,rk3399-usb3-phy";
369		- reg = <0x0 0xff7c0000 0x0 0x40000>;
370		- };
371	416	};
372	417
373		- dwc3_typec1: usb@fe900000 {
374		- compatible = "rockchip,rk3399-xhci";
375		- reg = <0x0 0xfe900000 0x0 0x100000>;
	418	+ cdn_dp: dp@fec00000 {
	419	+ compatible = "rockchip,rk3399-cdn-dp";
	420	+ reg = <0x0 0xfec00000 0x0 0x100000>;
	421	+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
	422	+ assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
	423	+ assigned-clock-rates = <100000000>, <200000000>;
	424	+ clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
	425	+ <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
	426	+ clock-names = "core-clk", "pclk", "spdif", "grf";
	427	+ phys = <&tcphy0_dp>, <&tcphy1_dp>;
	428	+ power-domains = <&power RK3399_PD_HDCP>;
	429	+ resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
	430	+ <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
	431	+ reset-names = "spdif", "dptx", "apb", "core";
	432	+ rockchip,grf = <&grf>;
	433	+ #sound-dai-cells = <1>;
376	434	status = "disabled";
377		- snps,dis-enblslpm-quirk;
378		- snps,phyif-utmi-bits = <16>;
379		- snps,dis-u2-freeclk-exists-quirk;
380		- snps,dis-u2-susphy-quirk;
381	435
382		- #address-cells = <2>;
383		- #size-cells = <2>;
384		- hub {
385		- compatible = "usb-hub";
386		- usb,device-class = <USB_CLASS_HUB>;
	436	+ ports {
	437	+ dp_in: port {
	438	+ #address-cells = <1>;
	439	+ #size-cells = <0>;
	440	+
	441	+ dp_in_vopb: endpoint@0 {
	442	+ reg = <0>;
	443	+ remote-endpoint = <&vopb_out_dp>;
	444	+ };
	445	+
	446	+ dp_in_vopl: endpoint@1 {
	447	+ reg = <1>;
	448	+ remote-endpoint = <&vopl_out_dp>;
	449	+ };
	450	+ };
387	451	};
388		- typec_phy1 {
389		- compatible = "rockchip,rk3399-usb3-phy";
390		- reg = <0x0 0xff800000 0x0 0x40000>;
391		- };
392	452	};
393	453
394	454	gic: interrupt-controller@fee00000 {
...	...	@@ -1054,6 +1114,21 @@
1054	1114	status = "disabled";
1055	1115	};
1056	1116
	1117	+ i2c0: i2c@ff3c0000 {
	1118	+ compatible = "rockchip,rk3399-i2c";
	1119	+ reg = <0x0 0xff3c0000 0x0 0x1000>;
	1120	+ assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
	1121	+ assigned-clock-rates = <200000000>;
	1122	+ clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
	1123	+ clock-names = "i2c", "pclk";
	1124	+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
	1125	+ pinctrl-names = "default";
	1126	+ pinctrl-0 = <&i2c0_xfer>;
	1127	+ #address-cells = <1>;
	1128	+ #size-cells = <0>;
	1129	+ status = "disabled";
	1130	+ };
	1131	+
1057	1132	i2c4: i2c@ff3d0000 {
1058	1133	compatible = "rockchip,rk3399-i2c";
1059	1134	reg = <0x0 0xff3d0000 0x0 0x1000>;
...	...	@@ -1217,7 +1292,10 @@
1217	1292	<&cru PCLK_PERIHP>,
1218	1293	<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1219	1294	<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1220		- <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
	1295	+ <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
	1296	+ <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
	1297	+ <&cru ACLK_GIC_PRE>,
	1298	+ <&cru PCLK_DDR>;
1221	1299	assigned-clock-rates =
1222	1300	<594000000>, <800000000>,
1223	1301	<1000000000>,
...	...	@@ -1225,7 +1303,10 @@
1225	1303	<37500000>,
1226	1304	<100000000>, <100000000>,
1227	1305	<50000000>, <600000000>,
1228		- <100000000>, <50000000>;
	1306	+ <100000000>, <50000000>,
	1307	+ <400000000>, <400000000>,
	1308	+ <200000000>,
	1309	+ <200000000>;
1229	1310	};
1230	1311
1231	1312	grf: syscon@ff770000 {
...	...	@@ -1314,6 +1395,56 @@
1314	1395	};
1315	1396	};
1316	1397
	1398	+ tcphy0: phy@ff7c0000 {
	1399	+ compatible = "rockchip,rk3399-typec-phy";
	1400	+ reg = <0x0 0xff7c0000 0x0 0x40000>;
	1401	+ clocks = <&cru SCLK_UPHY0_TCPDCORE>,
	1402	+ <&cru SCLK_UPHY0_TCPDPHY_REF>;
	1403	+ clock-names = "tcpdcore", "tcpdphy-ref";
	1404	+ assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
	1405	+ assigned-clock-rates = <50000000>;
	1406	+ power-domains = <&power RK3399_PD_TCPD0>;
	1407	+ resets = <&cru SRST_UPHY0>,
	1408	+ <&cru SRST_UPHY0_PIPE_L00>,
	1409	+ <&cru SRST_P_UPHY0_TCPHY>;
	1410	+ reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
	1411	+ rockchip,grf = <&grf>;
	1412	+ status = "disabled";
	1413	+
	1414	+ tcphy0_dp: dp-port {
	1415	+ #phy-cells = <0>;
	1416	+ };
	1417	+
	1418	+ tcphy0_usb3: usb3-port {
	1419	+ #phy-cells = <0>;
	1420	+ };
	1421	+ };
	1422	+
	1423	+ tcphy1: phy@ff800000 {
	1424	+ compatible = "rockchip,rk3399-typec-phy";
	1425	+ reg = <0x0 0xff800000 0x0 0x40000>;
	1426	+ clocks = <&cru SCLK_UPHY1_TCPDCORE>,
	1427	+ <&cru SCLK_UPHY1_TCPDPHY_REF>;
	1428	+ clock-names = "tcpdcore", "tcpdphy-ref";
	1429	+ assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
	1430	+ assigned-clock-rates = <50000000>;
	1431	+ power-domains = <&power RK3399_PD_TCPD1>;
	1432	+ resets = <&cru SRST_UPHY1>,
	1433	+ <&cru SRST_UPHY1_PIPE_L00>,
	1434	+ <&cru SRST_P_UPHY1_TCPHY>;
	1435	+ reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
	1436	+ rockchip,grf = <&grf>;
	1437	+ status = "disabled";
	1438	+
	1439	+ tcphy1_dp: dp-port {
	1440	+ #phy-cells = <0>;
	1441	+ };
	1442	+
	1443	+ tcphy1_usb3: usb3-port {
	1444	+ #phy-cells = <0>;
	1445	+ };
	1446	+ };
	1447	+
1317	1448	watchdog@ff848000 {
1318	1449	compatible = "snps,dw-wdt";
1319	1450	reg = <0x0 0xff848000 0x0 0x100>;
...	...	@@ -1340,6 +1471,7 @@
1340	1471	pinctrl-names = "default";
1341	1472	pinctrl-0 = <&spdif_bus>;
1342	1473	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	1474	+ #sound-dai-cells = <0>;
1343	1475	status = "disabled";
1344	1476	};
1345	1477
...	...	@@ -1355,6 +1487,7 @@
1355	1487	pinctrl-names = "default";
1356	1488	pinctrl-0 = <&i2s0_8ch_bus>;
1357	1489	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	1490	+ #sound-dai-cells = <0>;
1358	1491	status = "disabled";
1359	1492	};
1360	1493
...	...	@@ -1369,6 +1502,7 @@
1369	1502	pinctrl-names = "default";
1370	1503	pinctrl-0 = <&i2s1_2ch_bus>;
1371	1504	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	1505	+ #sound-dai-cells = <0>;
1372	1506	status = "disabled";
1373	1507	};
1374	1508
1375	1509
1376	1510
1377	1511
1378	1512
1379	1513
1380	1514
1381	1515
1382	1516
1383	1517
1384	1518
1385	1519
1386	1520
1387	1521
1388	1522
1389	1523
1390	1524
1391	1525
1392	1526
1393	1527
1394	1528
1395	1529
1396	1530
...	...	@@ -1381,92 +1515,186 @@
1381	1515	clock-names = "i2s_clk", "i2s_hclk";
1382	1516	clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1383	1517	power-domains = <&power RK3399_PD_SDIOAUDIO>;
	1518	+ #sound-dai-cells = <0>;
1384	1519	status = "disabled";
1385	1520	};
1386	1521
1387		- i2c0: i2c@ff3c0000 {
1388		- compatible = "rockchip,rk3399-i2c";
1389		- reg = <0x0 0xff3c0000 0x0 0x1000>;
1390		- assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1391		- assigned-clock-rates = <200000000>;
1392		- clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1393		- clock-names = "i2c", "pclk";
1394		- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1395		- pinctrl-names = "default";
1396		- pinctrl-0 = <&i2c0_xfer>;
1397		- #address-cells = <1>;
1398		- #size-cells = <0>;
1399		- status = "disabled";
1400		- };
1401		-
1402	1522	vopl: vop@ff8f0000 {
1403	1523	u-boot,dm-pre-reloc;
1404	1524	compatible = "rockchip,rk3399-vop-lit";
1405	1525	reg = <0x0 0xff8f0000 0x0 0x3efc>;
1406	1526	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
	1527	+ assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
	1528	+ assigned-clock-rates = <400000000>, <100000000>;
1407	1529	clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1408	1530	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	1531	+ iommus = <&vopl_mmu>;
	1532	+ power-domains = <&power RK3399_PD_VOPL>;
1409	1533	resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1410	1534	reset-names = "axi", "ahb", "dclk";
1411	1535	status = "disabled";
	1536	+
1412	1537	vopl_out: port {
1413	1538	#address-cells = <1>;
1414	1539	#size-cells = <0>;
	1540	+
1415	1541	vopl_out_mipi: endpoint@0 {
1416		- reg = <3>;
	1542	+ reg = <0>;
1417	1543	remote-endpoint = <&mipi_in_vopl>;
1418	1544	};
1419	1545
1420		- vopl_out_hdmi: endpoint@1 {
	1546	+ vopl_out_edp: endpoint@1 {
1421	1547	reg = <1>;
	1548	+ remote-endpoint = <&edp_in_vopl>;
	1549	+ };
	1550	+
	1551	+ vopl_out_hdmi: endpoint@2 {
	1552	+ reg = <2>;
1422	1553	remote-endpoint = <&hdmi_in_vopl>;
1423	1554	};
	1555	+
	1556	+ vopl_out_mipi1: endpoint@3 {
	1557	+ reg = <3>;
	1558	+ remote-endpoint = <&mipi1_in_vopl>;
	1559	+ };
	1560	+
	1561	+ vopl_out_dp: endpoint@4 {
	1562	+ reg = <4>;
	1563	+ remote-endpoint = <&dp_in_vopl>;
	1564	+ };
1424	1565	};
1425	1566	};
1426	1567
	1568	+ vopl_mmu: iommu@ff8f3f00 {
	1569	+ compatible = "rockchip,iommu";
	1570	+ reg = <0x0 0xff8f3f00 0x0 0x100>;
	1571	+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
	1572	+ interrupt-names = "vopl_mmu";
	1573	+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
	1574	+ clock-names = "aclk", "iface";
	1575	+ power-domains = <&power RK3399_PD_VOPL>;
	1576	+ #iommu-cells = <0>;
	1577	+ status = "disabled";
	1578	+ };
	1579	+
1427	1580	vopb: vop@ff900000 {
1428	1581	u-boot,dm-pre-reloc;
1429	1582	compatible = "rockchip,rk3399-vop-big";
1430	1583	reg = <0x0 0xff900000 0x0 0x3efc>;
1431	1584	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
	1585	+ assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
	1586	+ assigned-clock-rates = <400000000>, <100000000>;
1432	1587	clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1433		- #clock-cells = <0>;
1434	1588	clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
	1589	+ iommus = <&vopb_mmu>;
	1590	+ power-domains = <&power RK3399_PD_VOPB>;
1435	1591	resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1436	1592	reset-names = "axi", "ahb", "dclk";
1437	1593	status = "disabled";
	1594	+
1438	1595	vopb_out: port {
1439	1596	#address-cells = <1>;
1440	1597	#size-cells = <0>;
1441		- vopb_out_mipi: endpoint@0 {
1442		- reg = <3>;
1443		- remote-endpoint = <&mipi_in_vopb>;
	1598	+
	1599	+ vopb_out_edp: endpoint@0 {
	1600	+ reg = <0>;
	1601	+ remote-endpoint = <&edp_in_vopb>;
1444	1602	};
1445	1603
1446		- vopb_out_hdmi: endpoint@1 {
	1604	+ vopb_out_mipi: endpoint@1 {
1447	1605	reg = <1>;
	1606	+ remote-endpoint = <&mipi_in_vopb>;
	1607	+ };
	1608	+
	1609	+ vopb_out_hdmi: endpoint@2 {
	1610	+ reg = <2>;
1448	1611	remote-endpoint = <&hdmi_in_vopb>;
1449	1612	};
	1613	+
	1614	+ vopb_out_mipi1: endpoint@3 {
	1615	+ reg = <3>;
	1616	+ remote-endpoint = <&mipi1_in_vopb>;
	1617	+ };
	1618	+
	1619	+ vopb_out_dp: endpoint@4 {
	1620	+ reg = <4>;
	1621	+ remote-endpoint = <&dp_in_vopb>;
	1622	+ };
1450	1623	};
1451	1624	};
1452	1625
	1626	+ vopb_mmu: iommu@ff903f00 {
	1627	+ compatible = "rockchip,iommu";
	1628	+ reg = <0x0 0xff903f00 0x0 0x100>;
	1629	+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
	1630	+ interrupt-names = "vopb_mmu";
	1631	+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
	1632	+ clock-names = "aclk", "iface";
	1633	+ power-domains = <&power RK3399_PD_VOPB>;
	1634	+ #iommu-cells = <0>;
	1635	+ status = "disabled";
	1636	+ };
	1637	+
	1638	+ isp0_mmu: iommu@ff914000 {
	1639	+ compatible = "rockchip,iommu";
	1640	+ reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
	1641	+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
	1642	+ interrupt-names = "isp0_mmu";
	1643	+ clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
	1644	+ clock-names = "aclk", "iface";
	1645	+ #iommu-cells = <0>;
	1646	+ rockchip,disable-mmu-reset;
	1647	+ status = "disabled";
	1648	+ };
	1649	+
	1650	+ isp1_mmu: iommu@ff924000 {
	1651	+ compatible = "rockchip,iommu";
	1652	+ reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
	1653	+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
	1654	+ interrupt-names = "isp1_mmu";
	1655	+ clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
	1656	+ clock-names = "aclk", "iface";
	1657	+ #iommu-cells = <0>;
	1658	+ rockchip,disable-mmu-reset;
	1659	+ status = "disabled";
	1660	+ };
	1661	+
	1662	+ hdmi_sound: hdmi-sound {
	1663	+ compatible = "simple-audio-card";
	1664	+ simple-audio-card,format = "i2s";
	1665	+ simple-audio-card,mclk-fs = <256>;
	1666	+ simple-audio-card,name = "hdmi-sound";
	1667	+ status = "disabled";
	1668	+
	1669	+ simple-audio-card,cpu {
	1670	+ sound-dai = <&i2s2>;
	1671	+ };
	1672	+ simple-audio-card,codec {
	1673	+ sound-dai = <&hdmi>;
	1674	+ };
	1675	+ };
	1676	+
1453	1677	hdmi: hdmi@ff940000 {
1454	1678	compatible = "rockchip,rk3399-dw-hdmi";
1455	1679	reg = <0x0 0xff940000 0x0 0x20000>;
	1680	+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
	1681	+ clocks = <&cru PCLK_HDMI_CTRL>,
	1682	+ <&cru SCLK_HDMI_SFR>,
	1683	+ <&cru PLL_VPLL>,
	1684	+ <&cru PCLK_VIO_GRF>,
	1685	+ <&cru SCLK_HDMI_CEC>;
	1686	+ clock-names = "iahb", "isfr", "vpll", "grf", "cec";
	1687	+ power-domains = <&power RK3399_PD_HDCP>;
1456	1688	reg-io-width = <4>;
1457	1689	rockchip,grf = <&grf>;
1458		- pinctrl-names = "default";
1459		- pinctrl-0 = <&hdmi_i2c_xfer>;
1460		- power-domains = <&power RK3399_PD_HDCP>;
1461		- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1462		- clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1463		- clock-names = "iahb", "isfr", "vpll", "grf";
	1690	+ #sound-dai-cells = <0>;
1464	1691	status = "disabled";
1465	1692
1466	1693	ports {
1467	1694	hdmi_in: port {
1468	1695	#address-cells = <1>;
1469	1696	#size-cells = <0>;
	1697	+
1470	1698	hdmi_in_vopb: endpoint@0 {
1471	1699	reg = <0>;
1472	1700	remote-endpoint = <&vopb_out_hdmi>;
...	...	@@ -1507,6 +1735,88 @@
1507	1735	};
1508	1736	};
1509	1737
	1738	+ mipi_dsi1: mipi@ff968000 {
	1739	+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
	1740	+ reg = <0x0 0xff968000 0x0 0x8000>;
	1741	+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
	1742	+ clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
	1743	+ <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
	1744	+ clock-names = "ref", "pclk", "phy_cfg", "grf";
	1745	+ power-domains = <&power RK3399_PD_VIO>;
	1746	+ resets = <&cru SRST_P_MIPI_DSI1>;
	1747	+ reset-names = "apb";
	1748	+ rockchip,grf = <&grf>;
	1749	+ status = "disabled";
	1750	+
	1751	+ ports {
	1752	+ #address-cells = <1>;
	1753	+ #size-cells = <0>;
	1754	+
	1755	+ mipi1_in: port@0 {
	1756	+ reg = <0>;
	1757	+ #address-cells = <1>;
	1758	+ #size-cells = <0>;
	1759	+
	1760	+ mipi1_in_vopb: endpoint@0 {
	1761	+ reg = <0>;
	1762	+ remote-endpoint = <&vopb_out_mipi1>;
	1763	+ };
	1764	+
	1765	+ mipi1_in_vopl: endpoint@1 {
	1766	+ reg = <1>;
	1767	+ remote-endpoint = <&vopl_out_mipi1>;
	1768	+ };
	1769	+ };
	1770	+ };
	1771	+ };
	1772	+
	1773	+ edp: edp@ff970000 {
	1774	+ compatible = "rockchip,rk3399-edp";
	1775	+ reg = <0x0 0xff970000 0x0 0x8000>;
	1776	+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
	1777	+ clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
	1778	+ clock-names = "dp", "pclk", "grf";
	1779	+ pinctrl-names = "default";
	1780	+ pinctrl-0 = <&edp_hpd>;
	1781	+ power-domains = <&power RK3399_PD_EDP>;
	1782	+ resets = <&cru SRST_P_EDP_CTRL>;
	1783	+ reset-names = "dp";
	1784	+ rockchip,grf = <&grf>;
	1785	+ status = "disabled";
	1786	+
	1787	+ ports {
	1788	+ #address-cells = <1>;
	1789	+ #size-cells = <0>;
	1790	+ edp_in: port@0 {
	1791	+ reg = <0>;
	1792	+ #address-cells = <1>;
	1793	+ #size-cells = <0>;
	1794	+
	1795	+ edp_in_vopb: endpoint@0 {
	1796	+ reg = <0>;
	1797	+ remote-endpoint = <&vopb_out_edp>;
	1798	+ };
	1799	+
	1800	+ edp_in_vopl: endpoint@1 {
	1801	+ reg = <1>;
	1802	+ remote-endpoint = <&vopl_out_edp>;
	1803	+ };
	1804	+ };
	1805	+ };
	1806	+ };
	1807	+
	1808	+ gpu: gpu@ff9a0000 {
	1809	+ compatible = "rockchip,rk3399-mali", "arm,mali-t860";
	1810	+ reg = <0x0 0xff9a0000 0x0 0x10000>;
	1811	+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
	1812	+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
	1813	+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
	1814	+ interrupt-names = "gpu", "job", "mmu";
	1815	+ clocks = <&cru ACLK_GPU>;
	1816	+ power-domains = <&power RK3399_PD_GPU>;
	1817	+ status = "disabled";
	1818	+ };
	1819	+
1510	1820	pinctrl: pinctrl {
1511	1821	u-boot,dm-pre-reloc;
1512	1822	compatible = "rockchip,rk3399-pinctrl";
...	...	@@ -1911,7 +2221,7 @@
1911	2221	<4 RK_PB5 RK_FUNC_1 &pcfg_pull_up>;
1912	2222	};
1913	2223
1914		- sdmmc_cd: sdmcc-cd {
	2224	+ sdmmc_cd: sdmmc-cd {
1915	2225	rockchip,pins =
1916	2226	<0 RK_PA7 RK_FUNC_1 &pcfg_pull_up>;
1917	2227	};