Eric Lee / smarc-uboot

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Commit 0a15827f5d952831316f07906e6a5108877fb1f4

Authored by Ye Li
1 parent ec1c5aab18
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-23574-15 phy: Add USB PHY driver for the cadence USB3 

The cdns3-usb-phy driver supports both host and peripheral
mode of usb driver which use cadence usb3 IP.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>

Showing 3 changed files with 250 additions and 0 deletions Side-by-side Diff

... ... @@ -217,5 +217,13 @@
217 217 multi-ports is first version, otherwise is second veriosn,
218 218 so you can easily distinguish them by banks layout.
219 219  
  220 +config CDNS3_USB_PHY
  221 + bool "Support CDNS3 USB PHY"
  222 + depends on PHY
  223 + help
  224 + Support for the USB PHY in CDNS3 IP.
  225 +
  226 + This PHY is found on CDNS3 IP devices supporting USB.
  227 +
220 228 endmenu
drivers/phy/Makefile
Diff comments   View file @ 0a15827
... ... @@ -22,6 +22,7 @@
22 22 obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o
23 23 obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o
24 24 obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o
  25 +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o
25 26 obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o
26 27 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
drivers/phy/cdns3-usb-phy.c
Diff comments   View file @ 0a15827
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 NXP
  4 + *
  5 + * Cadence3 USB PHY driver
  6 + *
  7 + * Author: Sherry Sun <sherry.sun@nxp.com>
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <clk.h>
  12 +#include <dm.h>
  13 +#include <generic-phy.h>
  14 +#include <asm/io.h>
  15 +
  16 +/* PHY registers */
  17 +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4)
  18 +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4)
  19 +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4)
  20 +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4)
  21 +#define TB_ADDR_CMN_PLL0_INTDIV (0x0094 * 4)
  22 +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4)
  23 +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4)
  24 +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4)
  25 +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4)
  26 +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4)
  27 +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4)
  28 +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4)
  29 +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4)
  30 +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4)
  31 +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4)
  32 +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4)
  33 +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (0x01c4 * 4)
  34 +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4)
  35 +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4)
  36 +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4)
  37 +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4)
  38 +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4)
  39 +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4)
  40 +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4)
  41 +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4)
  42 +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4)
  43 +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4)
  44 +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4)
  45 +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4)
  46 +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4)
  47 +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4)
  48 +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4)
  49 +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4)
  50 +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4)
  51 +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4)
  52 +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4)
  53 +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4)
  54 +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4)
  55 +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (0x81dc * 4)
  56 +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4)
  57 +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4)
  58 +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4)
  59 +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4)
  60 +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 (0x81c2 * 4)
  61 +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4)
  62 +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4)
  63 +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4)
  64 +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4)
  65 +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4)
  66 +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4)
  67 +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4)
  68 +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4)
  69 +#define TB_ADDR_XCVR_PSM_CAL_TMR (0x4002 * 4)
  70 +#define TB_ADDR_XCVR_PSM_A0BYP_TMR (0x4004 * 4)
  71 +#define TB_ADDR_XCVR_PSM_A0IN_TMR (0x4003 * 4)
  72 +#define TB_ADDR_XCVR_PSM_A1IN_TMR (0x4005 * 4)
  73 +#define TB_ADDR_XCVR_PSM_A2IN_TMR (0x4006 * 4)
  74 +#define TB_ADDR_XCVR_PSM_A3IN_TMR (0x4007 * 4)
  75 +#define TB_ADDR_XCVR_PSM_A4IN_TMR (0x4008 * 4)
  76 +#define TB_ADDR_XCVR_PSM_A5IN_TMR (0x4009 * 4)
  77 +#define TB_ADDR_XCVR_PSM_A0OUT_TMR (0x400a * 4)
  78 +#define TB_ADDR_XCVR_PSM_A1OUT_TMR (0x400b * 4)
  79 +#define TB_ADDR_XCVR_PSM_A2OUT_TMR (0x400c * 4)
  80 +#define TB_ADDR_XCVR_PSM_A3OUT_TMR (0x400d * 4)
  81 +#define TB_ADDR_XCVR_PSM_A4OUT_TMR (0x400e * 4)
  82 +#define TB_ADDR_XCVR_PSM_A5OUT_TMR (0x400f * 4)
  83 +#define TB_ADDR_TX_RCVDET_EN_TMR (0x4122 * 4)
  84 +#define TB_ADDR_TX_RCVDET_ST_TMR (0x4123 * 4)
  85 +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR (0x40f2 * 4)
  86 +
  87 +struct cdns3_usb_phy {
  88 + struct clk phy_clk;
  89 + void __iomem *phy_regs;
  90 +};
  91 +
  92 +static int cdns3_usb_phy_init(struct phy *phy)
  93 +{
  94 + struct udevice *dev = phy->dev;
  95 + struct cdns3_usb_phy *priv = dev_get_priv(dev);
  96 + void __iomem *regs = priv->phy_regs;
  97 +
  98 + writel(0x0830, regs + PHY_PMA_CMN_CTRL1);
  99 + writel(0x10, regs + TB_ADDR_CMN_DIAG_HSCLK_SEL);
  100 + writel(0x00F0, regs + TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR);
  101 + writel(0x0018, regs + TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR);
  102 + writel(0x00D0, regs + TB_ADDR_CMN_PLL0_INTDIV);
  103 + writel(0x4aaa, regs + TB_ADDR_CMN_PLL0_FRACDIV);
  104 + writel(0x0034, regs + TB_ADDR_CMN_PLL0_HIGH_THR);
  105 + writel(0x1ee, regs + TB_ADDR_CMN_PLL0_SS_CTRL1);
  106 + writel(0x7F03, regs + TB_ADDR_CMN_PLL0_SS_CTRL2);
  107 + writel(0x0020, regs + TB_ADDR_CMN_PLL0_DSM_DIAG);
  108 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_OVRD);
  109 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD);
  110 + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD);
  111 + writel(0x0007, regs + TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE);
  112 + writel(0x0027, regs + TB_ADDR_CMN_DIAG_PLL0_CP_TUNE);
  113 + writel(0x0008, regs + TB_ADDR_CMN_DIAG_PLL0_LF_PROG);
  114 + writel(0x0022, regs + TB_ADDR_CMN_DIAG_PLL0_TEST_MODE);
  115 + writel(0x000a, regs + TB_ADDR_CMN_PSM_CLK_CTRL);
  116 + writel(0x139, regs + TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR);
  117 + writel(0xbefc, regs + TB_ADDR_XCVR_PSM_RCTRL);
  118 +
  119 + writel(0x7799, regs + TB_ADDR_TX_PSC_A0);
  120 + writel(0x7798, regs + TB_ADDR_TX_PSC_A1);
  121 + writel(0x509b, regs + TB_ADDR_TX_PSC_A2);
  122 + writel(0x3, regs + TB_ADDR_TX_DIAG_ECTRL_OVRD);
  123 + writel(0x509b, regs + TB_ADDR_TX_PSC_A3);
  124 + writel(0x2090, regs + TB_ADDR_TX_PSC_CAL);
  125 + writel(0x2090, regs + TB_ADDR_TX_PSC_RDY);
  126 +
  127 + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A0);
  128 + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A1);
  129 + writel(0xA410, regs + TB_ADDR_RX_PSC_A2);
  130 + writel(0x2410, regs + TB_ADDR_RX_PSC_A3);
  131 +
  132 + writel(0x23FF, regs + TB_ADDR_RX_PSC_CAL);
  133 + writel(0x2010, regs + TB_ADDR_RX_PSC_RDY);
  134 +
  135 + writel(0x0020, regs + TB_ADDR_TX_TXCC_MGNLS_MULT_000);
  136 + writel(0x00ff, regs + TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY);
  137 + writel(0x0002, regs + TB_ADDR_RX_SLC_CU_ITER_TMR);
  138 + writel(0x0013, regs + TB_ADDR_RX_SIGDET_HL_FILT_TMR);
  139 + writel(0x0000, regs + TB_ADDR_RX_SAMP_DAC_CTRL);
  140 + writel(0x1004, regs + TB_ADDR_RX_DIAG_SIGDET_TUNE);
  141 + writel(0x4041, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE2);
  142 + writel(0x0480, regs + TB_ADDR_RX_DIAG_BS_TM);
  143 + writel(0x8006, regs + TB_ADDR_RX_DIAG_DFE_CTRL1);
  144 + writel(0x003f, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM4);
  145 + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_E_TRIM0);
  146 + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_IQ_TRIM0);
  147 + writel(0x0000, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM6);
  148 + writel(0x8000, regs + TB_ADDR_RX_DIAG_RXFE_TM3);
  149 + writel(0x0003, regs + TB_ADDR_RX_DIAG_RXFE_TM4);
  150 + writel(0x2408, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE);
  151 + writel(0x05ca, regs + TB_ADDR_RX_DIAG_DFE_CTRL3);
  152 + writel(0x0258, regs + TB_ADDR_RX_DIAG_SC2C_DELAY);
  153 + writel(0x1fff, regs + TB_ADDR_RX_REE_VGA_GAIN_NODFE);
  154 +
  155 + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_CAL_TMR);
  156 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0BYP_TMR);
  157 + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_A0IN_TMR);
  158 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A1IN_TMR);
  159 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A2IN_TMR);
  160 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A3IN_TMR);
  161 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A4IN_TMR);
  162 + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A5IN_TMR);
  163 +
  164 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0OUT_TMR);
  165 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A1OUT_TMR);
  166 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A2OUT_TMR);
  167 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A3OUT_TMR);
  168 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A4OUT_TMR);
  169 + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A5OUT_TMR);
  170 +
  171 + /* Change rx detect parameter */
  172 + writel(0x960, regs + TB_ADDR_TX_RCVDET_EN_TMR);
  173 + writel(0x01e0, regs + TB_ADDR_TX_RCVDET_ST_TMR);
  174 + writel(0x0090, regs + TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR);
  175 +
  176 + udelay(10);
  177 + return 0;
  178 +}
  179 +
  180 +struct phy_ops cdns3_usb_phy_ops = {
  181 + .init = cdns3_usb_phy_init,
  182 +};
  183 +
  184 +static int cdns3_usb_phy_remove(struct udevice *dev)
  185 +{
  186 +#if CONFIG_IS_ENABLED(CLK)
  187 + struct cdns3_usb_phy *priv = dev_get_priv(dev);
  188 + int ret;
  189 +
  190 + if (priv->phy_clk.dev) {
  191 + ret = clk_disable(&priv->phy_clk);
  192 + if (ret)
  193 + return ret;
  194 +
  195 + ret = clk_free(&priv->phy_clk);
  196 + if (ret)
  197 + return ret;
  198 + }
  199 +#endif
  200 +
  201 + return 0;
  202 +}
  203 +
  204 +static int cdns3_usb_phy_probe(struct udevice *dev)
  205 +{
  206 + struct cdns3_usb_phy *priv = dev_get_priv(dev);
  207 +
  208 +#if CONFIG_IS_ENABLED(CLK)
  209 + int ret;
  210 +
  211 + ret = clk_get_by_name(dev, "main_clk", &priv->phy_clk);
  212 + if (ret) {
  213 + printf("Failed to get phy_clk\n");
  214 + return ret;
  215 + }
  216 +
  217 + ret = clk_enable(&priv->phy_clk);
  218 + if (ret) {
  219 + printf("Failed to enable phy_clk\n");
  220 + return ret;
  221 + }
  222 +#endif
  223 + priv->phy_regs = (void *__iomem)devfdt_get_addr(dev);
  224 +
  225 + return 0;
  226 +}
  227 +
  228 +static const struct udevice_id cdns3_usb_phy_ids[] = {
  229 + { .compatible = "cdns,usb3-phy" },
  230 + { }
  231 +};
  232 +
  233 +U_BOOT_DRIVER(cdns3_usb_phy) = {
  234 + .name = "cdns3_usb_phy",
  235 + .id = UCLASS_PHY,
  236 + .of_match = cdns3_usb_phy_ids,
  237 + .probe = cdns3_usb_phy_probe,
  238 + .remove = cdns3_usb_phy_remove,
  239 + .ops = &cdns3_usb_phy_ops,
  240 + .priv_auto_alloc_size = sizeof(struct cdns3_usb_phy),
  241 +};