ARM: imx6: Add DHCOM i.MX6 PDK board support

Add support for the DHCOM i.MX6 PDK board. This board has: - FEC ethernet - EHCI USB host - 3x SDMMC Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>

ARM: imx6: Add DHCOM i.MX6 PDK board support
Add support for the DHCOM i.MX6 PDK board. This board has: - FEC ethernet - EHCI USB host - 3x SDMMC Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut · Stefano Babic
1 parent 1a95913979
Showing 8 changed files with 1118 additions and 0 deletions Side-by-side Diff
arch/arm/mach-imx/mx6/Kconfig
board/dhelectronics/dh_imx6/Kconfig
board/dhelectronics/dh_imx6/MAINTAINERS
board/dhelectronics/dh_imx6/Makefile
board/dhelectronics/dh_imx6/dh_imx6.c
board/dhelectronics/dh_imx6/dh_imx6_spl.c
configs/dh_imx6_defconfig
include/configs/dh_imx6.h
@@ -129,6 +129,15 @@
 	select DM_SERIAL
 	select DM_THERMAL
  
+config TARGET_DHCOMIMX6
+	bool "dh_imx6"
+	select BOARD_LATE_INIT
+	select BOARD_EARLY_INIT_F
+	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
+	imply CMD_SPL
+
 config TARGET_EMBESTMX6BOARDS
 	bool "embestmx6boards"
 	select BOARD_LATE_INIT
@@ -428,6 +437,7 @@
 source "board/ccv/xpress/Kconfig"
 source "board/compulab/cm_fx6/Kconfig"
 source "board/congatec/cgtqmx6eval/Kconfig"
+source "board/dhelectronics/dh_imx6/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/engicam/geam6ul/Kconfig"
+if TARGET_DHCOMIMX6
+
+config SYS_BOARD
+	default "dh_imx6"
+
+config SYS_VENDOR
+	default "dhelectronics"
+
+config SYS_CONFIG_NAME
+	default "dh_imx6"
+
+endif
+DH_IMX6 BOARD
+M:	Andreas Geisreiter <ageisreiter@dh-electronics.de>, Ludwig Zenz <lzenz@dh-electronics.de>
+S:	Maintained
+F:	board/dhelectronics/dh_imx6/
+F:	include/configs/dh_imx6.h
+F:	configs/dh_mx6q_defconfig
+F:	configs/dh_mx6dl_defconfig
+#
+# Copyright (C) 2017 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y	:= dh_imx6_spl.o
+else
+obj-y	:= dh_imx6.o
+endif
+/*
+ * DHCOM DH-iMX6 PDK board support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <errno.h>
+#include <fsl_esdhc.h>
+#include <fuse.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define EEPROM_I2C_ADDRESS	0x50
+
+#define PC			MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+		 .gp = IMX_GPIO_NR(3, 28)
+	 }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		 .gp = IMX_GPIO_NR(4, 13)
+	 }
+};
+
+static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode  = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+		 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
+		 .gp = IMX_GPIO_NR(1, 6)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+		.gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+		.gp = IMX_GPIO_NR(3, 21)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+		 .gp = IMX_GPIO_NR(3, 28)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		 .gp = IMX_GPIO_NR(4, 13)
+	 }
+};
+
+static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
+	.scl = {
+		.i2c_mode  = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.gp = IMX_GPIO_NR(1, 3)
+	},
+	.sda = {
+		 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+		 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+		 .gp = IMX_GPIO_NR(1, 6)
+	 }
+};
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_FEC_MXC
+static void eth_phy_reset(void)
+{
+	/* Reset PHY */
+	gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
+	udelay(500);
+	gpio_set_value(IMX_GPIO_NR(5, 0), 1);
+
+	/* Enable VIO */
+	gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
+
+	/*
+	 * KSZ9021 PHY needs at least 10 mSec after PHY reset
+	 * is released to stabilize
+	 */
+	mdelay(10);
+}
+
+static int setup_fec_clock(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* set gpr1[21] to select anatop clock */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
+
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	uint32_t base = IMX_FEC_BASE;
+	struct mii_dev *bus = NULL;
+	struct phy_device *phydev = NULL;
+
+	setup_fec_clock();
+
+	eth_phy_reset();
+
+	bus = fec_get_miibus(base, -1);
+	if (!bus)
+		return -EINVAL;
+
+	/* Scan PHY 0 */
+	phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
+	if (!phydev) {
+		printf("Ethernet PHY not found!\n");
+		return -EINVAL;
+	}
+
+	return fec_probe(bis, -1, base, bus, phydev);
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 16)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(7, 8)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+	{ USDHC2_BASE_ADDR },
+	{ USDHC3_BASE_ADDR },
+	{ USDHC4_BASE_ADDR },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		return gpio_get_value(USDHC2_CD_GPIO);
+	case USDHC3_BASE_ADDR:
+		return !gpio_get_value(USDHC3_CD_GPIO);
+	case USDHC4_BASE_ADDR:
+		return 1; /* eMMC/uSDHC4 is always present */
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    SD interface
+	 * mmc1                    micro SD
+	 * mmc2                    eMMC
+	 */
+	gpio_direction_input(USDHC2_CD_GPIO);
+	gpio_direction_input(USDHC3_CD_GPIO);
+
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+static void setup_usb(void)
+{
+	/*
+	 * Set daisy chain for otg_pin_id on MX6Q.
+	 * For MX6DL, this bit is reserved.
+	 */
+	imx_iomux_set_gpr_register(1, 13, 1, 0);
+}
+
+int board_usb_phy_mode(int port)
+{
+	return USB_INIT_HOST;
+}
+
+/* Use only Port 1 == DHCOM USB Host 1 */
+int board_ehci_hcd_init(int port)
+{
+	if (port == 1)
+		return 0;
+	else
+		return -ENODEV;
+}
+
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		break;
+	case 1:
+		gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#endif
+
+static int setup_dhcom_mac_from_fuse(void)
+{
+	unsigned char enetaddr[6];
+	int ret;
+
+	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
+	if (ret)	/* ethaddr is already set */
+		return 0;
+
+	imx_get_mac_from_fuse(0, enetaddr);
+
+	if (is_valid_ethaddr(enetaddr)) {
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+		return 0;
+	}
+
+	ret = i2c_set_bus_num(2);
+	if (ret) {
+		printf("Error switching I2C bus!\n");
+		return ret;
+	}
+
+	ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
+	if (ret) {
+		printf("Error reading configuration EEPROM!\n");
+		return ret;
+	}
+
+	if (is_valid_ethaddr(enetaddr))
+		eth_env_set_enetaddr("ethaddr", enetaddr);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_USB_EHCI_MX6
+	setup_usb();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return IMX_GPIO_NR(2, 30);
+	else
+		return -1;
+}
+#endif
+
+int board_init(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/* Enable eim_slow clocks */
+	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
+
+#ifdef CONFIG_SYS_I2C_MXC
+	if (is_mx6dq()) {
+		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
+	} else {
+		setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
+	}
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+	setup_dhcom_mac_from_fuse();
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	/* 8 bit bus width */
+	{"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+#define HW_CODE_BIT_0	IMX_GPIO_NR(2, 19)
+#define HW_CODE_BIT_1	IMX_GPIO_NR(6, 6)
+#define HW_CODE_BIT_2	IMX_GPIO_NR(2, 16)
+
+static int board_get_hwcode(void)
+{
+	int hw_code;
+
+	gpio_direction_input(HW_CODE_BIT_0);
+	gpio_direction_input(HW_CODE_BIT_1);
+	gpio_direction_input(HW_CODE_BIT_2);
+
+	/* HW 100 + HW 200 = 00b; HW 300 = 01b */
+	hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
+		   (gpio_get_value(HW_CODE_BIT_1) << 1) |
+		    gpio_get_value(HW_CODE_BIT_0)) + 2;
+
+	return hw_code;
+}
+
+int board_late_init(void)
+{
+	u32 hw_code;
+	char buf[16];
+
+	hw_code = board_get_hwcode();
+
+	switch (get_cpu_type()) {
+	case MXC_CPU_MX6SOLO:
+		snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6DL:
+		snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6D:
+		snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
+		break;
+	case MXC_CPU_MX6Q:
+		snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
+		break;
+	default:
+		snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
+		break;
+	}
+
+	env_set("dhcom", buf);
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DHCOM i.MX6\n");
+	return 0;
+}
+/*
+ * DHCOM DH-iMX6 PDK SPL support
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <fuse.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <spl.h>
+
+#define ENET_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_HYS)
+
+#define GPIO_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
+
+#define SPI_PAD_CTRL							\
+	(PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL							\
+	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	 PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL							\
+	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |	\
+	 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
+	.dram_sdclk_0	= 0x00020030,
+	.dram_sdclk_1	= 0x00020030,
+	.dram_cas	= 0x00020030,
+	.dram_ras	= 0x00020030,
+	.dram_reset	= 0x00020030,
+	.dram_sdcke0	= 0x00003000,
+	.dram_sdcke1	= 0x00003000,
+	.dram_sdba2	= 0x00000000,
+	.dram_sdodt0	= 0x00003030,
+	.dram_sdodt1	= 0x00003030,
+	.dram_sdqs0	= 0x00000030,
+	.dram_sdqs1	= 0x00000030,
+	.dram_sdqs2	= 0x00000030,
+	.dram_sdqs3	= 0x00000030,
+	.dram_sdqs4	= 0x00000030,
+	.dram_sdqs5	= 0x00000030,
+	.dram_sdqs6	= 0x00000030,
+	.dram_sdqs7	= 0x00000030,
+	.dram_dqm0	= 0x00020030,
+	.dram_dqm1	= 0x00020030,
+	.dram_dqm2	= 0x00020030,
+	.dram_dqm3	= 0x00020030,
+	.dram_dqm4	= 0x00020030,
+	.dram_dqm5	= 0x00020030,
+	.dram_dqm6	= 0x00020030,
+	.dram_dqm7	= 0x00020030,
+};
+
+static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
+	.grp_ddr_type	= 0x000C0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke	= 0x00000000,
+	.grp_addds	= 0x00000030,
+	.grp_ctlds	= 0x00000030,
+	.grp_ddrmode	= 0x00020000,
+	.grp_b0ds	= 0x00000030,
+	.grp_b1ds	= 0x00000030,
+	.grp_b2ds	= 0x00000030,
+	.grp_b3ds	= 0x00000030,
+	.grp_b4ds	= 0x00000030,
+	.grp_b5ds	= 0x00000030,
+	.grp_b6ds	= 0x00000030,
+	.grp_b7ds	= 0x00000030,
+};
+
+static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
+	.p0_mpwldectrl0	= 0x001F001F,
+	.p0_mpwldectrl1	= 0x001F001F,
+	.p1_mpwldectrl0	= 0x00440044,
+	.p1_mpwldectrl1	= 0x00440044,
+	.p0_mpdgctrl0	= 0x434B0350,
+	.p0_mpdgctrl1	= 0x034C0359,
+	.p1_mpdgctrl0	= 0x434B0350,
+	.p1_mpdgctrl1	= 0x03650348,
+	.p0_mprddlctl	= 0x4436383B,
+	.p1_mprddlctl	= 0x39393341,
+	.p0_mpwrdlctl	= 0x35373933,
+	.p1_mpwrdlctl	= 0x48254A36,
+};
+
+static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
+	.mem_speed	= 1600,
+	.density	= 4,
+	.width		= 64,
+	.banks		= 8,
+	.rowaddr	= 14,
+	.coladdr	= 10,
+	.pagesz		= 2,
+	.trcd		= 1375,
+	.trcmin		= 4875,
+	.trasmin	= 3500,
+};
+
+static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
+	/* width of data bus:0=16,1=32,2=64 */
+	.dsize		= 2,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,	/* 32Gb per CS */
+	.ncs		= 1,	/* single chip select */
+	.cs1_mirror	= 0,
+	.rtt_wr		= 1,	/* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
+	.rtt_nom	= 1,	/* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
+	.walat		= 1,	/* Write additional latency */
+	.ralat		= 5,	/* Read additional latency */
+	.mif3_mode	= 3,	/* Command prediction working mode */
+	.bi_on		= 1,	/* Bank interleaving enabled */
+	.sde_to_rst	= 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke	= 0x23,	/* 33 cycles, 500us (JEDEC default) */
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+/* Board ID */
+static iomux_v3_cfg_t const hwcode_pads[] = {
+	IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_boardid(void)
+{
+	/* HW code pins: Setup alternate function and configure pads */
+	SETUP_IOMUX_PADS(hwcode_pads);
+}
+
+/* GPIO */
+static iomux_v3_cfg_t const gpio_pads[] = {
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
+};
+
+static void setup_iomux_gpio(void)
+{
+	SETUP_IOMUX_PADS(gpio_pads);
+}
+
+/* Ethernet */
+static iomux_v3_cfg_t const enet_pads[] = {
+	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN	| MUX_PAD_CTRL(ENET_PAD_CTRL)),
+	/* SMSC PHY Reset */
+	IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_VIO_GPIO */
+	IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* ENET_Interrupt - (not used) */
+	IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_enet(void)
+{
+	SETUP_IOMUX_PADS(enet_pads);
+}
+
+/* SD interface */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* onboard microSD */
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+/* eMMC */
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+/* SD */
+static void setup_iomux_sd(void)
+{
+	SETUP_IOMUX_PADS(usdhc2_pads);
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	SETUP_IOMUX_PADS(usdhc4_pads);
+}
+
+/* SPI */
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+	/* SS0 */
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK	| MUX_PAD_CTRL(SPI_PAD_CTRL)),
+};
+
+static void setup_iomux_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return IMX_GPIO_NR(2, 30);
+	else
+		return -1;
+}
+
+/* UART */
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA	| MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+/* USB */
+static iomux_v3_cfg_t const usb_pads[] = {
+	IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31	| MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_usb(void)
+{
+	SETUP_IOMUX_PADS(usb_pads);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+	gpr_init();
+
+	/* setup GP timer */
+	timer_init();
+
+	setup_iomux_boardid();
+	setup_iomux_gpio();
+	setup_iomux_enet();
+	setup_iomux_sd();
+	setup_iomux_spi();
+	setup_iomux_uart();
+	setup_iomux_usb();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* Start the DDR DRAM */
+	if (is_mx6dq())
+		mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
+				 &dhcom6dq_grp_ioregs);
+	else
+		mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
+				  &dhcom6sdl_grp_ioregs);
+	mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
+
+	/* Perform DDR DRAM calibration */
+	udelay(100);
+	mmdc_do_write_level_calibration(&dhcom_ddr_info);
+	mmdc_do_dqs_calibration(&dhcom_ddr_info);
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
+CONFIG_TARGET_DHCOMIMX6=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+/*
+ * DHCOM DH-iMX6 PDK board configuration
+ *
+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DH_IMX6_CONFIG_H
+#define __DH_IMX6_CONFIG_H
+
+#include <asm/arch/imx-regs.h>
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+/*
+ * SPI NOR layout:
+ * 0x00_0000-0x00_ffff ... U-Boot SPL
+ * 0x01_0000-0x0f_ffff ... U-Boot
+ * 0x10_0000-0x10_ffff ... U-Boot env #1
+ * 0x11_0000-0x11_ffff ... U-Boot env #2
+ * 0x12_0000-0x1f_ffff ... UNUSED
+ */
+
+/* SPL */
+#include "imx6_spl.h"			/* common IMX6 SPL configuration */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x11400
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.imx"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SUPPORT_RAW_INITRD	/* bootz raw initrd support */
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_BZIP2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(4 * SZ_1M)
+
+/* Bootcounter */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_SYS_BOOTCOUNT_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* FEC ethernet */
+#define CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE		RMII
+#define CONFIG_ETHPRIME			"FEC"
+#define CONFIG_FEC_MXC_PHYADDR		0
+#define CONFIG_ARP_TIMEOUT		200UL
+
+/* Fuses */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	3
+#define CONFIG_SYS_MMC_ENV_DEV		2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* SPI Flash Configs */
+#ifdef CONFIG_CMD_SF
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		0
+#define CONFIG_SF_DEFAULT_SPEED		25000000
+#define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS		0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT	2 /* Enabled USB controller number */
+#endif
+
+/* Watchdog */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+#define CONFIG_WATCHDOG_TIMEOUT_MSECS	60000
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+#define CONFIG_LOADADDR			0x12000000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"console=ttymxc0,115200\0"	\
+	"fdt_addr=0x18000000\0"		\
+	"fdt_high=0xffffffff\0"		\
+	"initrd_high=0xffffffff\0"	\
+	"kernel_addr_r=0x10008000\0"	\
+	"fdt_addr_r=0x13000000\0"	\
+	"ramdisk_addr_r=0x18000000\0"	\
+	"scriptaddr=0x14000000\0"	\
+	"fdtfile=imx6q-dhcom-pdk2.dtb\0"\
+	BOOTENV
+
+#define CONFIG_BOOTCOMMAND		"run distro_bootcmd"
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 2) \
+	func(USB, usb, 1) \
+	func(SATA, sata, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_SYS_MEMTEST_SCRATCH	0x10800000
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(16 * 1024)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(1024 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_OFFSET_REDUND	\
+	(CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#endif
+
+#endif	/* __DH_IMX6_CONFIG_H */
...	...	@@ -129,6 +129,15 @@
129	129	select DM_SERIAL
130	130	select DM_THERMAL
131	131
	132	+config TARGET_DHCOMIMX6
	133	+ bool "dh_imx6"
	134	+ select BOARD_LATE_INIT
	135	+ select BOARD_EARLY_INIT_F
	136	+ select SUPPORT_SPL
	137	+ select DM
	138	+ select DM_THERMAL
	139	+ imply CMD_SPL
	140	+
132	141	config TARGET_EMBESTMX6BOARDS
133	142	bool "embestmx6boards"
134	143	select BOARD_LATE_INIT
...	...	@@ -428,6 +437,7 @@
428	437	source "board/ccv/xpress/Kconfig"
429	438	source "board/compulab/cm_fx6/Kconfig"
430	439	source "board/congatec/cgtqmx6eval/Kconfig"
	440	+source "board/dhelectronics/dh_imx6/Kconfig"
431	441	source "board/el/el6x/Kconfig"
432	442	source "board/embest/mx6boards/Kconfig"
433	443	source "board/engicam/geam6ul/Kconfig"
	1	+if TARGET_DHCOMIMX6
	2	+
	3	+config SYS_BOARD
	4	+ default "dh_imx6"
	5	+
	6	+config SYS_VENDOR
	7	+ default "dhelectronics"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "dh_imx6"
	11	+
	12	+endif
	1	+DH_IMX6 BOARD
	2	+M: Andreas Geisreiter <ageisreiter@dh-electronics.de>, Ludwig Zenz <lzenz@dh-electronics.de>
	3	+S: Maintained
	4	+F: board/dhelectronics/dh_imx6/
	5	+F: include/configs/dh_imx6.h
	6	+F: configs/dh_mx6q_defconfig
	7	+F: configs/dh_mx6dl_defconfig
	1	+#
	2	+# Copyright (C) 2017 Marek Vasut <marex@denx.de>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+ifdef CONFIG_SPL_BUILD
	8	+obj-y := dh_imx6_spl.o
	9	+else
	10	+obj-y := dh_imx6.o
	11	+endif
	1	+/*
	2	+ * DHCOM DH-iMX6 PDK board support
	3	+ *
	4	+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <asm/arch/clock.h>
	11	+#include <asm/arch/crm_regs.h>
	12	+#include <asm/arch/imx-regs.h>
	13	+#include <asm/arch/iomux.h>
	14	+#include <asm/arch/mx6-pins.h>
	15	+#include <asm/arch/sys_proto.h>
	16	+#include <asm/gpio.h>
	17	+#include <asm/io.h>
	18	+#include <asm/mach-imx/boot_mode.h>
	19	+#include <asm/mach-imx/iomux-v3.h>
	20	+#include <asm/mach-imx/mxc_i2c.h>
	21	+#include <asm/mach-imx/sata.h>
	22	+#include <errno.h>
	23	+#include <fsl_esdhc.h>
	24	+#include <fuse.h>
	25	+#include <i2c.h>
	26	+#include <miiphy.h>
	27	+#include <mmc.h>
	28	+#include <net.h>
	29	+#include <netdev.h>
	30	+#include <usb.h>
	31	+#include <usb/ehci-ci.h>
	32	+
	33	+DECLARE_GLOBAL_DATA_PTR;
	34	+
	35	+#define I2C_PAD_CTRL \
	36	+ (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	37	+ PAD_CTL_HYS \| PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	38	+
	39	+#define EEPROM_I2C_ADDRESS 0x50
	40	+
	41	+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	42	+
	43	+static struct i2c_pads_info dh6sdl_i2c_pad_info0 = {
	44	+ .scl = {
	45	+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL \| PC,
	46	+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 \| PC,
	47	+ .gp = IMX_GPIO_NR(3, 21)
	48	+ },
	49	+ .sda = {
	50	+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA \| PC,
	51	+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 \| PC,
	52	+ .gp = IMX_GPIO_NR(3, 28)
	53	+ }
	54	+};
	55	+
	56	+static struct i2c_pads_info dh6sdl_i2c_pad_info1 = {
	57	+ .scl = {
	58	+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL \| PC,
	59	+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 \| PC,
	60	+ .gp = IMX_GPIO_NR(4, 12)
	61	+ },
	62	+ .sda = {
	63	+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA \| PC,
	64	+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
	65	+ .gp = IMX_GPIO_NR(4, 13)
	66	+ }
	67	+};
	68	+
	69	+static struct i2c_pads_info dh6sdl_i2c_pad_info2 = {
	70	+ .scl = {
	71	+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL \| PC,
	72	+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 \| PC,
	73	+ .gp = IMX_GPIO_NR(1, 3)
	74	+ },
	75	+ .sda = {
	76	+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA \| PC,
	77	+ .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 \| PC,
	78	+ .gp = IMX_GPIO_NR(1, 6)
	79	+ }
	80	+};
	81	+
	82	+static struct i2c_pads_info dh6dq_i2c_pad_info0 = {
	83	+ .scl = {
	84	+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL \| PC,
	85	+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 \| PC,
	86	+ .gp = IMX_GPIO_NR(3, 21)
	87	+ },
	88	+ .sda = {
	89	+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA \| PC,
	90	+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 \| PC,
	91	+ .gp = IMX_GPIO_NR(3, 28)
	92	+ }
	93	+};
	94	+
	95	+static struct i2c_pads_info dh6dq_i2c_pad_info1 = {
	96	+ .scl = {
	97	+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL \| PC,
	98	+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 \| PC,
	99	+ .gp = IMX_GPIO_NR(4, 12)
	100	+ },
	101	+ .sda = {
	102	+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA \| PC,
	103	+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
	104	+ .gp = IMX_GPIO_NR(4, 13)
	105	+ }
	106	+};
	107	+
	108	+static struct i2c_pads_info dh6dq_i2c_pad_info2 = {
	109	+ .scl = {
	110	+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL \| PC,
	111	+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 \| PC,
	112	+ .gp = IMX_GPIO_NR(1, 3)
	113	+ },
	114	+ .sda = {
	115	+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA \| PC,
	116	+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 \| PC,
	117	+ .gp = IMX_GPIO_NR(1, 6)
	118	+ }
	119	+};
	120	+
	121	+int dram_init(void)
	122	+{
	123	+ gd->ram_size = imx_ddr_size();
	124	+ return 0;
	125	+}
	126	+
	127	+/*
	128	+ * Do not overwrite the console
	129	+ * Use always serial for U-Boot console
	130	+ */
	131	+int overwrite_console(void)
	132	+{
	133	+ return 1;
	134	+}
	135	+
	136	+#ifdef CONFIG_FEC_MXC
	137	+static void eth_phy_reset(void)
	138	+{
	139	+ /* Reset PHY */
	140	+ gpio_direction_output(IMX_GPIO_NR(5, 0) , 0);
	141	+ udelay(500);
	142	+ gpio_set_value(IMX_GPIO_NR(5, 0), 1);
	143	+
	144	+ /* Enable VIO */
	145	+ gpio_direction_output(IMX_GPIO_NR(1, 7) , 0);
	146	+
	147	+ /*
	148	+ * KSZ9021 PHY needs at least 10 mSec after PHY reset
	149	+ * is released to stabilize
	150	+ */
	151	+ mdelay(10);
	152	+}
	153	+
	154	+static int setup_fec_clock(void)
	155	+{
	156	+ struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	157	+
	158	+ /* set gpr1[21] to select anatop clock */
	159	+ clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
	160	+
	161	+ return enable_fec_anatop_clock(0, ENET_50MHZ);
	162	+}
	163	+
	164	+int board_eth_init(bd_t *bis)
	165	+{
	166	+ uint32_t base = IMX_FEC_BASE;
	167	+ struct mii_dev *bus = NULL;
	168	+ struct phy_device *phydev = NULL;
	169	+
	170	+ setup_fec_clock();
	171	+
	172	+ eth_phy_reset();
	173	+
	174	+ bus = fec_get_miibus(base, -1);
	175	+ if (!bus)
	176	+ return -EINVAL;
	177	+
	178	+ /* Scan PHY 0 */
	179	+ phydev = phy_find_by_mask(bus, 0xf, PHY_INTERFACE_MODE_RGMII);
	180	+ if (!phydev) {
	181	+ printf("Ethernet PHY not found!\n");
	182	+ return -EINVAL;
	183	+ }
	184	+
	185	+ return fec_probe(bis, -1, base, bus, phydev);
	186	+}
	187	+#endif
	188	+
	189	+#ifdef CONFIG_FSL_ESDHC
	190	+
	191	+#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 16)
	192	+#define USDHC3_CD_GPIO IMX_GPIO_NR(7, 8)
	193	+
	194	+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	195	+ { USDHC2_BASE_ADDR },
	196	+ { USDHC3_BASE_ADDR },
	197	+ { USDHC4_BASE_ADDR },
	198	+};
	199	+
	200	+int board_mmc_getcd(struct mmc *mmc)
	201	+{
	202	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	203	+
	204	+ switch (cfg->esdhc_base) {
	205	+ case USDHC2_BASE_ADDR:
	206	+ return gpio_get_value(USDHC2_CD_GPIO);
	207	+ case USDHC3_BASE_ADDR:
	208	+ return !gpio_get_value(USDHC3_CD_GPIO);
	209	+ case USDHC4_BASE_ADDR:
	210	+ return 1; /* eMMC/uSDHC4 is always present */
	211	+ }
	212	+
	213	+ return 0;
	214	+}
	215	+
	216	+int board_mmc_init(bd_t *bis)
	217	+{
	218	+ int i, ret;
	219	+
	220	+ /*
	221	+ * According to the board_mmc_init() the following map is done:
	222	+ * (U-Boot device node) (Physical Port)
	223	+ * mmc0 SD interface
	224	+ * mmc1 micro SD
	225	+ * mmc2 eMMC
	226	+ */
	227	+ gpio_direction_input(USDHC2_CD_GPIO);
	228	+ gpio_direction_input(USDHC3_CD_GPIO);
	229	+
	230	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
	231	+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	232	+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
	233	+
	234	+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	235	+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	236	+ if (ret)
	237	+ return ret;
	238	+ }
	239	+
	240	+ return 0;
	241	+}
	242	+#endif
	243	+
	244	+#ifdef CONFIG_USB_EHCI_MX6
	245	+static void setup_usb(void)
	246	+{
	247	+ /*
	248	+ * Set daisy chain for otg_pin_id on MX6Q.
	249	+ * For MX6DL, this bit is reserved.
	250	+ */
	251	+ imx_iomux_set_gpr_register(1, 13, 1, 0);
	252	+}
	253	+
	254	+int board_usb_phy_mode(int port)
	255	+{
	256	+ return USB_INIT_HOST;
	257	+}
	258	+
	259	+/* Use only Port 1 == DHCOM USB Host 1 */
	260	+int board_ehci_hcd_init(int port)
	261	+{
	262	+ if (port == 1)
	263	+ return 0;
	264	+ else
	265	+ return -ENODEV;
	266	+}
	267	+
	268	+int board_ehci_power(int port, int on)
	269	+{
	270	+ switch (port) {
	271	+ case 0:
	272	+ break;
	273	+ case 1:
	274	+ gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
	275	+ break;
	276	+ default:
	277	+ printf("MXC USB port %d not yet supported\n", port);
	278	+ return -EINVAL;
	279	+ }
	280	+
	281	+ return 0;
	282	+}
	283	+#endif
	284	+
	285	+static int setup_dhcom_mac_from_fuse(void)
	286	+{
	287	+ unsigned char enetaddr[6];
	288	+ int ret;
	289	+
	290	+ ret = eth_env_get_enetaddr("ethaddr", enetaddr);
	291	+ if (ret) /* ethaddr is already set */
	292	+ return 0;
	293	+
	294	+ imx_get_mac_from_fuse(0, enetaddr);
	295	+
	296	+ if (is_valid_ethaddr(enetaddr)) {
	297	+ eth_env_set_enetaddr("ethaddr", enetaddr);
	298	+ return 0;
	299	+ }
	300	+
	301	+ ret = i2c_set_bus_num(2);
	302	+ if (ret) {
	303	+ printf("Error switching I2C bus!\n");
	304	+ return ret;
	305	+ }
	306	+
	307	+ ret = i2c_read(EEPROM_I2C_ADDRESS, 0xfa, 0x1, enetaddr, 0x6);
	308	+ if (ret) {
	309	+ printf("Error reading configuration EEPROM!\n");
	310	+ return ret;
	311	+ }
	312	+
	313	+ if (is_valid_ethaddr(enetaddr))
	314	+ eth_env_set_enetaddr("ethaddr", enetaddr);
	315	+
	316	+ return 0;
	317	+}
	318	+
	319	+int board_early_init_f(void)
	320	+{
	321	+#ifdef CONFIG_USB_EHCI_MX6
	322	+ setup_usb();
	323	+#endif
	324	+
	325	+ return 0;
	326	+}
	327	+
	328	+#ifdef CONFIG_MXC_SPI
	329	+int board_spi_cs_gpio(unsigned bus, unsigned cs)
	330	+{
	331	+ if (bus == 0 && cs == 0)
	332	+ return IMX_GPIO_NR(2, 30);
	333	+ else
	334	+ return -1;
	335	+}
	336	+#endif
	337	+
	338	+int board_init(void)
	339	+{
	340	+ struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	341	+
	342	+ /* address of boot parameters */
	343	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	344	+
	345	+ /* Enable eim_slow clocks */
	346	+ setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
	347	+
	348	+#ifdef CONFIG_SYS_I2C_MXC
	349	+ if (is_mx6dq()) {
	350	+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info0);
	351	+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info1);
	352	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6dq_i2c_pad_info2);
	353	+ } else {
	354	+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info0);
	355	+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info1);
	356	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &dh6sdl_i2c_pad_info2);
	357	+ }
	358	+#endif
	359	+
	360	+#ifdef CONFIG_SATA
	361	+ setup_sata();
	362	+#endif
	363	+
	364	+ setup_dhcom_mac_from_fuse();
	365	+
	366	+ return 0;
	367	+}
	368	+
	369	+#ifdef CONFIG_CMD_BMODE
	370	+static const struct boot_mode board_boot_modes[] = {
	371	+ /* 4 bit bus width */
	372	+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	373	+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	374	+ /* 8 bit bus width */
	375	+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
	376	+ {NULL, 0},
	377	+};
	378	+#endif
	379	+
	380	+#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
	381	+#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
	382	+#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
	383	+
	384	+static int board_get_hwcode(void)
	385	+{
	386	+ int hw_code;
	387	+
	388	+ gpio_direction_input(HW_CODE_BIT_0);
	389	+ gpio_direction_input(HW_CODE_BIT_1);
	390	+ gpio_direction_input(HW_CODE_BIT_2);
	391	+
	392	+ /* HW 100 + HW 200 = 00b; HW 300 = 01b */
	393	+ hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) \|
	394	+ (gpio_get_value(HW_CODE_BIT_1) << 1) \|
	395	+ gpio_get_value(HW_CODE_BIT_0)) + 2;
	396	+
	397	+ return hw_code;
	398	+}
	399	+
	400	+int board_late_init(void)
	401	+{
	402	+ u32 hw_code;
	403	+ char buf[16];
	404	+
	405	+ hw_code = board_get_hwcode();
	406	+
	407	+ switch (get_cpu_type()) {
	408	+ case MXC_CPU_MX6SOLO:
	409	+ snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
	410	+ break;
	411	+ case MXC_CPU_MX6DL:
	412	+ snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
	413	+ break;
	414	+ case MXC_CPU_MX6D:
	415	+ snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
	416	+ break;
	417	+ case MXC_CPU_MX6Q:
	418	+ snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
	419	+ break;
	420	+ default:
	421	+ snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
	422	+ break;
	423	+ }
	424	+
	425	+ env_set("dhcom", buf);
	426	+
	427	+#ifdef CONFIG_CMD_BMODE
	428	+ add_board_boot_modes(board_boot_modes);
	429	+#endif
	430	+ return 0;
	431	+}
	432	+
	433	+int checkboard(void)
	434	+{
	435	+ puts("Board: DHCOM i.MX6\n");
	436	+ return 0;
	437	+}
	1	+/*
	2	+ * DHCOM DH-iMX6 PDK SPL support
	3	+ *
	4	+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <asm/arch/clock.h>
	11	+#include <asm/arch/crm_regs.h>
	12	+#include <asm/arch/imx-regs.h>
	13	+#include <asm/arch/iomux.h>
	14	+#include <asm/arch/mx6-ddr.h>
	15	+#include <asm/arch/mx6-pins.h>
	16	+#include <asm/arch/sys_proto.h>
	17	+#include <asm/gpio.h>
	18	+#include <asm/mach-imx/boot_mode.h>
	19	+#include <asm/mach-imx/iomux-v3.h>
	20	+#include <asm/mach-imx/mxc_i2c.h>
	21	+#include <asm/io.h>
	22	+#include <errno.h>
	23	+#include <fuse.h>
	24	+#include <fsl_esdhc.h>
	25	+#include <i2c.h>
	26	+#include <mmc.h>
	27	+#include <spl.h>
	28	+
	29	+#define ENET_PAD_CTRL \
	30	+ (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	31	+ PAD_CTL_HYS)
	32	+
	33	+#define GPIO_PAD_CTRL \
	34	+ (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm)
	35	+
	36	+#define SPI_PAD_CTRL \
	37	+ (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	38	+ PAD_CTL_SRE_FAST)
	39	+
	40	+#define UART_PAD_CTRL \
	41	+ (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	42	+ PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	43	+
	44	+#define USDHC_PAD_CTRL \
	45	+ (PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	46	+ PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	47	+
	48	+DECLARE_GLOBAL_DATA_PTR;
	49	+
	50	+static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
	51	+ .dram_sdclk_0 = 0x00020030,
	52	+ .dram_sdclk_1 = 0x00020030,
	53	+ .dram_cas = 0x00020030,
	54	+ .dram_ras = 0x00020030,
	55	+ .dram_reset = 0x00020030,
	56	+ .dram_sdcke0 = 0x00003000,
	57	+ .dram_sdcke1 = 0x00003000,
	58	+ .dram_sdba2 = 0x00000000,
	59	+ .dram_sdodt0 = 0x00003030,
	60	+ .dram_sdodt1 = 0x00003030,
	61	+ .dram_sdqs0 = 0x00000030,
	62	+ .dram_sdqs1 = 0x00000030,
	63	+ .dram_sdqs2 = 0x00000030,
	64	+ .dram_sdqs3 = 0x00000030,
	65	+ .dram_sdqs4 = 0x00000030,
	66	+ .dram_sdqs5 = 0x00000030,
	67	+ .dram_sdqs6 = 0x00000030,
	68	+ .dram_sdqs7 = 0x00000030,
	69	+ .dram_dqm0 = 0x00020030,
	70	+ .dram_dqm1 = 0x00020030,
	71	+ .dram_dqm2 = 0x00020030,
	72	+ .dram_dqm3 = 0x00020030,
	73	+ .dram_dqm4 = 0x00020030,
	74	+ .dram_dqm5 = 0x00020030,
	75	+ .dram_dqm6 = 0x00020030,
	76	+ .dram_dqm7 = 0x00020030,
	77	+};
	78	+
	79	+static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
	80	+ .grp_ddr_type = 0x000C0000,
	81	+ .grp_ddrmode_ctl = 0x00020000,
	82	+ .grp_ddrpke = 0x00000000,
	83	+ .grp_addds = 0x00000030,
	84	+ .grp_ctlds = 0x00000030,
	85	+ .grp_ddrmode = 0x00020000,
	86	+ .grp_b0ds = 0x00000030,
	87	+ .grp_b1ds = 0x00000030,
	88	+ .grp_b2ds = 0x00000030,
	89	+ .grp_b3ds = 0x00000030,
	90	+ .grp_b4ds = 0x00000030,
	91	+ .grp_b5ds = 0x00000030,
	92	+ .grp_b6ds = 0x00000030,
	93	+ .grp_b7ds = 0x00000030,
	94	+};
	95	+
	96	+static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
	97	+ .dram_sdclk_0 = 0x00020030,
	98	+ .dram_sdclk_1 = 0x00020030,
	99	+ .dram_cas = 0x00020030,
	100	+ .dram_ras = 0x00020030,
	101	+ .dram_reset = 0x00020030,
	102	+ .dram_sdcke0 = 0x00003000,
	103	+ .dram_sdcke1 = 0x00003000,
	104	+ .dram_sdba2 = 0x00000000,
	105	+ .dram_sdodt0 = 0x00003030,
	106	+ .dram_sdodt1 = 0x00003030,
	107	+ .dram_sdqs0 = 0x00000030,
	108	+ .dram_sdqs1 = 0x00000030,
	109	+ .dram_sdqs2 = 0x00000030,
	110	+ .dram_sdqs3 = 0x00000030,
	111	+ .dram_sdqs4 = 0x00000030,
	112	+ .dram_sdqs5 = 0x00000030,
	113	+ .dram_sdqs6 = 0x00000030,
	114	+ .dram_sdqs7 = 0x00000030,
	115	+ .dram_dqm0 = 0x00020030,
	116	+ .dram_dqm1 = 0x00020030,
	117	+ .dram_dqm2 = 0x00020030,
	118	+ .dram_dqm3 = 0x00020030,
	119	+ .dram_dqm4 = 0x00020030,
	120	+ .dram_dqm5 = 0x00020030,
	121	+ .dram_dqm6 = 0x00020030,
	122	+ .dram_dqm7 = 0x00020030,
	123	+};
	124	+
	125	+static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
	126	+ .grp_ddr_type = 0x000C0000,
	127	+ .grp_ddrmode_ctl = 0x00020000,
	128	+ .grp_ddrpke = 0x00000000,
	129	+ .grp_addds = 0x00000030,
	130	+ .grp_ctlds = 0x00000030,
	131	+ .grp_ddrmode = 0x00020000,
	132	+ .grp_b0ds = 0x00000030,
	133	+ .grp_b1ds = 0x00000030,
	134	+ .grp_b2ds = 0x00000030,
	135	+ .grp_b3ds = 0x00000030,
	136	+ .grp_b4ds = 0x00000030,
	137	+ .grp_b5ds = 0x00000030,
	138	+ .grp_b6ds = 0x00000030,
	139	+ .grp_b7ds = 0x00000030,
	140	+};
	141	+
	142	+static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
	143	+ .p0_mpwldectrl0 = 0x001F001F,
	144	+ .p0_mpwldectrl1 = 0x001F001F,
	145	+ .p1_mpwldectrl0 = 0x00440044,
	146	+ .p1_mpwldectrl1 = 0x00440044,
	147	+ .p0_mpdgctrl0 = 0x434B0350,
	148	+ .p0_mpdgctrl1 = 0x034C0359,
	149	+ .p1_mpdgctrl0 = 0x434B0350,
	150	+ .p1_mpdgctrl1 = 0x03650348,
	151	+ .p0_mprddlctl = 0x4436383B,
	152	+ .p1_mprddlctl = 0x39393341,
	153	+ .p0_mpwrdlctl = 0x35373933,
	154	+ .p1_mpwrdlctl = 0x48254A36,
	155	+};
	156	+
	157	+static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
	158	+ .mem_speed = 1600,
	159	+ .density = 4,
	160	+ .width = 64,
	161	+ .banks = 8,
	162	+ .rowaddr = 14,
	163	+ .coladdr = 10,
	164	+ .pagesz = 2,
	165	+ .trcd = 1375,
	166	+ .trcmin = 4875,
	167	+ .trasmin = 3500,
	168	+};
	169	+
	170	+static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
	171	+ /* width of data bus:0=16,1=32,2=64 */
	172	+ .dsize = 2,
	173	+ /* config for full 4GB range so that get_mem_size() works */
	174	+ .cs_density = 32, /* 32Gb per CS */
	175	+ .ncs = 1, /* single chip select */
	176	+ .cs1_mirror = 0,
	177	+ .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
	178	+ .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
	179	+ .walat = 1, /* Write additional latency */
	180	+ .ralat = 5, /* Read additional latency */
	181	+ .mif3_mode = 3, /* Command prediction working mode */
	182	+ .bi_on = 1, /* Bank interleaving enabled */
	183	+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	184	+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
	185	+};
	186	+
	187	+static void ccgr_init(void)
	188	+{
	189	+ struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	190	+
	191	+ writel(0x00C03F3F, &ccm->CCGR0);
	192	+ writel(0x0030FC03, &ccm->CCGR1);
	193	+ writel(0x0FFFC000, &ccm->CCGR2);
	194	+ writel(0x3FF00000, &ccm->CCGR3);
	195	+ writel(0x00FFF300, &ccm->CCGR4);
	196	+ writel(0x0F0000C3, &ccm->CCGR5);
	197	+ writel(0x000003FF, &ccm->CCGR6);
	198	+}
	199	+
	200	+/* Board ID */
	201	+static iomux_v3_cfg_t const hwcode_pads[] = {
	202	+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	203	+ IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	204	+ IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	205	+};
	206	+
	207	+static void setup_iomux_boardid(void)
	208	+{
	209	+ /* HW code pins: Setup alternate function and configure pads */
	210	+ SETUP_IOMUX_PADS(hwcode_pads);
	211	+}
	212	+
	213	+/* GPIO */
	214	+static iomux_v3_cfg_t const gpio_pads[] = {
	215	+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	216	+ IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	217	+ IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	218	+ IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	219	+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	220	+ IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	221	+ IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	222	+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	223	+ IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	224	+ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	225	+ IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	226	+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	227	+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	228	+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	229	+ IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	230	+ IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	231	+ IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	232	+ IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	233	+ IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	234	+ IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	235	+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	236	+ IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	237	+ IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 \| MUX_PAD_CTRL(GPIO_PAD_CTRL)),
	238	+};
	239	+
	240	+static void setup_iomux_gpio(void)
	241	+{
	242	+ SETUP_IOMUX_PADS(gpio_pads);
	243	+}
	244	+
	245	+/* Ethernet */
	246	+static iomux_v3_cfg_t const enet_pads[] = {
	247	+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	248	+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	249	+ IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	250	+ IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	251	+ IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	252	+ IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	253	+ IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	254	+ IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	255	+ IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	256	+ IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	257	+ /* SMSC PHY Reset */
	258	+ IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	259	+ /* ENET_VIO_GPIO */
	260	+ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	261	+ /* ENET_Interrupt - (not used) */
	262	+ IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	263	+};
	264	+
	265	+static void setup_iomux_enet(void)
	266	+{
	267	+ SETUP_IOMUX_PADS(enet_pads);
	268	+}
	269	+
	270	+/* SD interface */
	271	+static iomux_v3_cfg_t const usdhc2_pads[] = {
	272	+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	273	+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	274	+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	275	+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	276	+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	277	+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	278	+ IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
	279	+};
	280	+
	281	+/* onboard microSD */
	282	+static iomux_v3_cfg_t const usdhc3_pads[] = {
	283	+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	284	+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	285	+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	286	+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	287	+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	288	+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	289	+ IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
	290	+};
	291	+
	292	+/* eMMC */
	293	+static iomux_v3_cfg_t const usdhc4_pads[] = {
	294	+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	295	+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	296	+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	297	+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	298	+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	299	+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	300	+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	301	+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	302	+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	303	+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	304	+};
	305	+
	306	+/* SD */
	307	+static void setup_iomux_sd(void)
	308	+{
	309	+ SETUP_IOMUX_PADS(usdhc2_pads);
	310	+ SETUP_IOMUX_PADS(usdhc3_pads);
	311	+ SETUP_IOMUX_PADS(usdhc4_pads);
	312	+}
	313	+
	314	+/* SPI */
	315	+static iomux_v3_cfg_t const ecspi1_pads[] = {
	316	+ /* SS0 */
	317	+ IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	318	+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	319	+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	320	+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	321	+};
	322	+
	323	+static void setup_iomux_spi(void)
	324	+{
	325	+ SETUP_IOMUX_PADS(ecspi1_pads);
	326	+}
	327	+
	328	+int board_spi_cs_gpio(unsigned bus, unsigned cs)
	329	+{
	330	+ if (bus == 0 && cs == 0)
	331	+ return IMX_GPIO_NR(2, 30);
	332	+ else
	333	+ return -1;
	334	+}
	335	+
	336	+/* UART */
	337	+static iomux_v3_cfg_t const uart1_pads[] = {
	338	+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	339	+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	340	+};
	341	+
	342	+static void setup_iomux_uart(void)
	343	+{
	344	+ SETUP_IOMUX_PADS(uart1_pads);
	345	+}
	346	+
	347	+/* USB */
	348	+static iomux_v3_cfg_t const usb_pads[] = {
	349	+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	350	+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	351	+};
	352	+
	353	+static void setup_iomux_usb(void)
	354	+{
	355	+ SETUP_IOMUX_PADS(usb_pads);
	356	+}
	357	+
	358	+void board_init_f(ulong dummy)
	359	+{
	360	+ /* setup AIPS and disable watchdog */
	361	+ arch_cpu_init();
	362	+
	363	+ ccgr_init();
	364	+ gpr_init();
	365	+
	366	+ /* setup GP timer */
	367	+ timer_init();
	368	+
	369	+ setup_iomux_boardid();
	370	+ setup_iomux_gpio();
	371	+ setup_iomux_enet();
	372	+ setup_iomux_sd();
	373	+ setup_iomux_spi();
	374	+ setup_iomux_uart();
	375	+ setup_iomux_usb();
	376	+
	377	+ /* UART clocks enabled and gd valid - init serial console */
	378	+ preloader_console_init();
	379	+
	380	+ /* Start the DDR DRAM */
	381	+ if (is_mx6dq())
	382	+ mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
	383	+ &dhcom6dq_grp_ioregs);
	384	+ else
	385	+ mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
	386	+ &dhcom6sdl_grp_ioregs);
	387	+ mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
	388	+
	389	+ /* Perform DDR DRAM calibration */
	390	+ udelay(100);
	391	+ mmdc_do_write_level_calibration(&dhcom_ddr_info);
	392	+ mmdc_do_dqs_calibration(&dhcom_ddr_info);
	393	+
	394	+ /* Clear the BSS. */
	395	+ memset(__bss_start, 0, __bss_end - __bss_start);
	396	+
	397	+ /* load/boot image from boot device */
	398	+ board_init_r(NULL, 0);
	399	+}
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_MX6=y
	3	+CONFIG_SPL_GPIO_SUPPORT=y
	4	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	5	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	6	+CONFIG_MX6_DDRCAL=y
	7	+CONFIG_TARGET_DHCOMIMX6=y
	8	+CONFIG_SPL_SERIAL_SUPPORT=y
	9	+CONFIG_SPL_SPI_FLASH_SUPPORT=y
	10	+CONFIG_SPL_SPI_SUPPORT=y
	11	+CONFIG_SPL_WATCHDOG_SUPPORT=y
	12	+CONFIG_FIT=y
	13	+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
	14	+CONFIG_BOOTDELAY=3
	15	+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
	16	+CONFIG_SPL=y
	17	+CONFIG_SPL_I2C_SUPPORT=y
	18	+CONFIG_HUSH_PARSER=y
	19	+CONFIG_CMD_BOOTZ=y
	20	+# CONFIG_CMD_IMLS is not set
	21	+CONFIG_CMD_MEMTEST=y
	22	+CONFIG_CMD_UNZIP=y
	23	+# CONFIG_CMD_FLASH is not set
	24	+CONFIG_CMD_GPIO=y
	25	+CONFIG_CMD_I2C=y
	26	+CONFIG_CMD_MMC=y
	27	+CONFIG_CMD_PART=y
	28	+CONFIG_CMD_SATA=y
	29	+CONFIG_CMD_SF=y
	30	+CONFIG_CMD_USB=y
	31	+CONFIG_CMD_DHCP=y
	32	+CONFIG_CMD_MII=y
	33	+CONFIG_CMD_PING=y
	34	+CONFIG_CMD_CACHE=y
	35	+CONFIG_CMD_TIME=y
	36	+CONFIG_CMD_EXT2=y
	37	+CONFIG_CMD_EXT4=y
	38	+CONFIG_CMD_EXT4_WRITE=y
	39	+CONFIG_CMD_FAT=y
	40	+CONFIG_CMD_FS_GENERIC=y
	41	+CONFIG_ENV_IS_IN_SPI_FLASH=y
	42	+CONFIG_SPI_FLASH=y
	43	+CONFIG_SPI_FLASH_SPANSION=y
	44	+CONFIG_PHYLIB=y
	45	+CONFIG_PHY_MICREL=y
	46	+CONFIG_PHY_MICREL_KSZ90X1=y
	47	+CONFIG_NETDEVICES=y
	48	+CONFIG_FEC_MXC=y
	49	+CONFIG_USB=y
	50	+CONFIG_USB_STORAGE=y
	51	+CONFIG_OF_LIBFDT=y
	1	+/*
	2	+ * DHCOM DH-iMX6 PDK board configuration
	3	+ *
	4	+ * Copyright (C) 2017 Marek Vasut <marex@denx.de>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef __DH_IMX6_CONFIG_H
	10	+#define __DH_IMX6_CONFIG_H
	11	+
	12	+#include <asm/arch/imx-regs.h>
	13	+
	14	+#include <config_distro_defaults.h>
	15	+#include "mx6_common.h"
	16	+
	17	+/*
	18	+ * SPI NOR layout:
	19	+ * 0x00_0000-0x00_ffff ... U-Boot SPL
	20	+ * 0x01_0000-0x0f_ffff ... U-Boot
	21	+ * 0x10_0000-0x10_ffff ... U-Boot env #1
	22	+ * 0x11_0000-0x11_ffff ... U-Boot env #2
	23	+ * 0x12_0000-0x1f_ffff ... UNUSED
	24	+ */
	25	+
	26	+/* SPL */
	27	+#include "imx6_spl.h" /* common IMX6 SPL configuration */
	28	+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400
	29	+#define CONFIG_SPL_SPI_LOAD
	30	+#define CONFIG_SPL_TARGET "u-boot-with-spl.imx"
	31	+
	32	+/* Miscellaneous configurable options */
	33	+#define CONFIG_SYS_LONGHELP
	34	+#define CONFIG_AUTO_COMPLETE
	35	+#define CONFIG_CMDLINE_EDITING
	36	+
	37	+#define CONFIG_CMDLINE_TAG
	38	+#define CONFIG_SETUP_MEMORY_TAGS
	39	+#define CONFIG_INITRD_TAG
	40	+#define CONFIG_REVISION_TAG
	41	+
	42	+#define CONFIG_SUPPORT_RAW_INITRD /* bootz raw initrd support */
	43	+#define CONFIG_BOUNCE_BUFFER
	44	+#define CONFIG_BZIP2
	45	+
	46	+/* Size of malloc() pool */
	47	+#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M)
	48	+
	49	+/* Bootcounter */
	50	+#define CONFIG_BOOTCOUNT_LIMIT
	51	+#define CONFIG_SYS_BOOTCOUNT_ADDR IRAM_BASE_ADDR
	52	+#define CONFIG_SYS_BOOTCOUNT_BE
	53	+
	54	+/* FEC ethernet */
	55	+#define CONFIG_MII
	56	+#define IMX_FEC_BASE ENET_BASE_ADDR
	57	+#define CONFIG_FEC_XCV_TYPE RMII
	58	+#define CONFIG_ETHPRIME "FEC"
	59	+#define CONFIG_FEC_MXC_PHYADDR 0
	60	+#define CONFIG_ARP_TIMEOUT 200UL
	61	+
	62	+/* Fuses */
	63	+#ifdef CONFIG_CMD_FUSE
	64	+#define CONFIG_MXC_OCOTP
	65	+#endif
	66	+
	67	+/* GPIO */
	68	+#define CONFIG_MXC_GPIO
	69	+
	70	+/* I2C Configs */
	71	+#define CONFIG_SYS_I2C
	72	+#define CONFIG_SYS_I2C_MXC
	73	+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
	74	+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	75	+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
	76	+#define CONFIG_SYS_I2C_SPEED 100000
	77	+
	78	+/* MMC Configs */
	79	+#define CONFIG_FSL_ESDHC
	80	+#define CONFIG_FSL_USDHC
	81	+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	82	+#define CONFIG_SYS_FSL_USDHC_NUM 3
	83	+#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */
	84	+
	85	+/* SATA Configs */
	86	+#ifdef CONFIG_CMD_SATA
	87	+#define CONFIG_DWC_AHSATA
	88	+#define CONFIG_SYS_SATA_MAX_DEVICE 1
	89	+#define CONFIG_DWC_AHSATA_PORT_ID 0
	90	+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	91	+#define CONFIG_LBA48
	92	+#define CONFIG_LIBATA
	93	+#endif
	94	+
	95	+/* SPI Flash Configs */
	96	+#ifdef CONFIG_CMD_SF
	97	+#define CONFIG_MXC_SPI
	98	+#define CONFIG_SF_DEFAULT_BUS 0
	99	+#define CONFIG_SF_DEFAULT_CS 0
	100	+#define CONFIG_SF_DEFAULT_SPEED 25000000
	101	+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
	102	+#endif
	103	+
	104	+/* UART */
	105	+#define CONFIG_MXC_UART
	106	+#define CONFIG_MXC_UART_BASE UART1_BASE
	107	+#define CONFIG_CONS_INDEX 1
	108	+#define CONFIG_BAUDRATE 115200
	109	+
	110	+/* USB Configs */
	111	+#ifdef CONFIG_CMD_USB
	112	+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	113	+#define CONFIG_USB_HOST_ETHER
	114	+#define CONFIG_USB_ETHER_ASIX
	115	+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	116	+#define CONFIG_MXC_USB_FLAGS 0
	117	+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
	118	+#endif
	119	+
	120	+/* Watchdog */
	121	+#define CONFIG_HW_WATCHDOG
	122	+#define CONFIG_IMX_WATCHDOG
	123	+#define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
	124	+
	125	+/* allow to overwrite serial and ethaddr */
	126	+#define CONFIG_ENV_OVERWRITE
	127	+
	128	+#define CONFIG_SYS_TEXT_BASE 0x17800000
	129	+#define CONFIG_LOADADDR 0x12000000
	130	+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	131	+
	132	+#ifndef CONFIG_SPL_BUILD
	133	+#define CONFIG_EXTRA_ENV_SETTINGS \
	134	+ "console=ttymxc0,115200\0" \
	135	+ "fdt_addr=0x18000000\0" \
	136	+ "fdt_high=0xffffffff\0" \
	137	+ "initrd_high=0xffffffff\0" \
	138	+ "kernel_addr_r=0x10008000\0" \
	139	+ "fdt_addr_r=0x13000000\0" \
	140	+ "ramdisk_addr_r=0x18000000\0" \
	141	+ "scriptaddr=0x14000000\0" \
	142	+ "fdtfile=imx6q-dhcom-pdk2.dtb\0"\
	143	+ BOOTENV
	144	+
	145	+#define CONFIG_BOOTCOMMAND "run distro_bootcmd"
	146	+
	147	+#define BOOT_TARGET_DEVICES(func) \
	148	+ func(MMC, mmc, 0) \
	149	+ func(MMC, mmc, 2) \
	150	+ func(USB, usb, 1) \
	151	+ func(SATA, sata, 0) \
	152	+ func(DHCP, dhcp, na)
	153	+
	154	+#include <config_distro_bootcmd.h>
	155	+#endif
	156	+
	157	+/* Physical Memory Map */
	158	+#define CONFIG_NR_DRAM_BANKS 1
	159	+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	160	+
	161	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	162	+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	163	+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	164	+
	165	+#define CONFIG_SYS_INIT_SP_OFFSET \
	166	+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	167	+
	168	+#define CONFIG_SYS_INIT_SP_ADDR \
	169	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	170	+
	171	+#define CONFIG_SYS_MEMTEST_START 0x10000000
	172	+#define CONFIG_SYS_MEMTEST_END 0x20000000
	173	+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
	174	+
	175	+/* Environment */
	176	+#define CONFIG_ENV_SIZE (16 * 1024)
	177	+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
	178	+
	179	+#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
	180	+#define CONFIG_ENV_OFFSET (1024 * 1024)
	181	+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	182	+#define CONFIG_ENV_OFFSET_REDUND \
	183	+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	184	+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	185	+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	186	+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	187	+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	188	+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	189	+#endif
	190	+
	191	+#endif /* __DH_IMX6_CONFIG_H */