x86: apl: Add pinctrl driver

Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: apl: Add pinctrl driver
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass · Bin Meng
1 parent 7656582378
Showing 4 changed files with 691 additions and 3 deletions Side-by-side Diff
arch/x86/include/asm/arch-apollolake/gpio.h
drivers/pinctrl/intel/Kconfig
drivers/pinctrl/intel/Makefile
drivers/pinctrl/intel/pinctrl_apl.c
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Definitions for the GPIO subsystem on Apollolake
+ *
+ * Copyright (C) 2015 - 2017 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
+ *
+ * Placed in a separate file since some of these definitions can be used from
+ * assembly code
+ *
+ * Taken from gpio_apl.h in coreboot
+ */
+
+#ifndef _ASM_ARCH_GPIO_H_
+#define _ASM_ARCH_GPIO_H_
+
+/* Port ids */
+#define PID_GPIO_SW	0xC0
+#define PID_GPIO_S	0xC2
+#define PID_GPIO_W	0xC7
+#define PID_GPIO_NW	0xC4
+#define PID_GPIO_N	0xC5
+#define PID_ITSS	0xD0
+#define PID_RTC		0xD1
+
+/*
+ * Miscellaneous Configuration register(MISCCFG). These are community-specific
+ * registers and are meant to house miscellaneous configuration fields per
+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
+ */
+#define GPIO_MISCCFG		0x10 /* Miscellaneous Configuration offset */
+#define  GPIO_GPE_SW_31_0	0 /* SOUTHWEST GPIO#  0 ~ 31 belong to GROUP0 */
+#define  GPIO_GPE_SW_63_32	1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */
+#define  GPIO_GPE_W_31_0	2 /* WEST      GPIO#  0 ~ 25 belong to GROUP2 */
+#define  GPIO_GPE_NW_31_0	4 /* NORTHWEST GPIO#  0 ~ 17 belong to GROUP4 */
+#define  GPIO_GPE_NW_63_32	5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */
+#define  GPIO_GPE_NW_95_64	6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */
+#define  GPIO_GPE_N_31_0	7 /* NORTH     GPIO#  0 ~ 31 belong to GROUP7 */
+#define  GPIO_GPE_N_63_32	8 /* NORTH     GPIO# 32 ~ 61 belong to GROUP8 */
+
+#define GPIO_MAX_NUM_PER_GROUP	32
+
+/*
+ * Host Software Pad Ownership Register.
+ * The pins in the community are divided into 3 groups:
+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
+ */
+#define HOSTSW_OWN_REG_0		0x80
+
+#define PAD_CFG_BASE			0x500
+
+#define GPI_INT_STS_0			0x100
+#define GPI_INT_EN_0			0x110
+
+#define GPI_SMI_STS_0			0x140
+#define GPI_SMI_EN_0			0x150
+
+#define NUM_N_PADS			(PAD_N(SVID0_CLK) + 1)
+#define NUM_NW_PADS			(PAD_NW(GPIO_123) + 1)
+#define NUM_W_PADS			(PAD_W(SUSPWRDNACK) + 1)
+#define NUM_SW_PADS			(PAD_SW(LPC_FRAMEB) + 1)
+
+#define NUM_N_GPI_REGS	\
+	(ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_NW_GPI_REGS	\
+	(ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_W_GPI_REGS	\
+	(ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_SW_GPI_REGS	\
+	(ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+/*
+ * Total number of GPI status registers across all GPIO communities in the SOC
+ */
+#define NUM_GPI_STATUS_REGS		(NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
+					+ NUM_W_GPI_REGS + NUM_SW_GPI_REGS)
+
+/* North community pads */
+#define GPIO_0				0
+#define GPIO_1				1
+#define GPIO_2				2
+#define GPIO_3				3
+#define GPIO_4				4
+#define GPIO_5				5
+#define GPIO_6				6
+#define GPIO_7				7
+#define GPIO_8				8
+#define GPIO_9				9
+#define GPIO_10				10
+#define GPIO_11				11
+#define GPIO_12				12
+#define GPIO_13				13
+#define GPIO_14				14
+#define GPIO_15				15
+#define GPIO_16				16
+#define GPIO_17				17
+#define GPIO_18				18
+#define GPIO_19				19
+#define GPIO_20				20
+#define GPIO_21				21
+#define GPIO_22				22
+#define GPIO_23				23
+#define GPIO_24				24
+#define GPIO_25				25
+#define GPIO_26				26
+#define GPIO_27				27
+#define GPIO_28				28
+#define GPIO_29				29
+#define GPIO_30				30
+#define GPIO_31				31
+#define GPIO_32				32
+#define GPIO_33				33
+#define GPIO_34				34
+#define GPIO_35				35
+#define GPIO_36				36
+#define GPIO_37				37
+#define GPIO_38				38
+#define GPIO_39				39
+#define GPIO_40				40
+#define GPIO_41				41
+#define GPIO_42				42
+#define GPIO_43				43
+#define GPIO_44				44
+#define GPIO_45				45
+#define GPIO_46				46
+#define GPIO_47				47
+#define GPIO_48				48
+#define GPIO_49				49
+#define GPIO_62				50
+#define GPIO_63				51
+#define GPIO_64				52
+#define GPIO_65				53
+#define GPIO_66				54
+#define GPIO_67				55
+#define GPIO_68				56
+#define GPIO_69				57
+#define GPIO_70				58
+#define GPIO_71				59
+#define GPIO_72				60
+#define GPIO_73				61
+#define JTAG_TCK			62
+#define JTAG_TRST_B			63
+#define JTAG_TMS			64
+#define JTAG_TDI			65
+#define JTAG_CX_PMODE			66
+#define JTAG_CX_PREQ_B			67
+#define JTAGX				68
+#define JTAG_CX_PRDY_B			69
+#define JTAG_TDO			70
+#define CNV_BRI_DT			71
+#define CNV_BRI_RSP			72
+#define CNV_RGI_DT			73
+#define CNV_RGI_RSP			74
+#define SVID0_ALERT_B			75
+#define SVID0_DATA			76
+#define SVID0_CLK			77
+
+/* Northwest community pads */
+#define GPIO_187			78
+#define GPIO_188			79
+#define GPIO_189			80
+#define GPIO_190			81
+#define GPIO_191			82
+#define GPIO_192			83
+#define GPIO_193			84
+#define GPIO_194			85
+#define GPIO_195			86
+#define GPIO_196			87
+#define GPIO_197			88
+#define GPIO_198			89
+#define GPIO_199			90
+#define GPIO_200			91
+#define GPIO_201			92
+#define GPIO_202			93
+#define GPIO_203			94
+#define GPIO_204			95
+#define PMC_SPI_FS0			96
+#define PMC_SPI_FS1			97
+#define PMC_SPI_FS2			98
+#define PMC_SPI_RXD			99
+#define PMC_SPI_TXD			100
+#define PMC_SPI_CLK			101
+#define PMIC_PWRGOOD			102
+#define PMIC_RESET_B			103
+#define GPIO_213			104
+#define GPIO_214			105
+#define GPIO_215			106
+#define PMIC_THERMTRIP_B		107
+#define PMIC_STDBY			108
+#define PROCHOT_B			109
+#define PMIC_I2C_SCL			110
+#define PMIC_I2C_SDA			111
+#define GPIO_74				112
+#define GPIO_75				113
+#define GPIO_76				114
+#define GPIO_77				115
+#define GPIO_78				116
+#define GPIO_79				117
+#define GPIO_80				118
+#define GPIO_81				119
+#define GPIO_82				120
+#define GPIO_83				121
+#define GPIO_84				122
+#define GPIO_85				123
+#define GPIO_86				124
+#define GPIO_87				125
+#define GPIO_88				126
+#define GPIO_89				127
+#define GPIO_90				128
+#define GPIO_91				129
+#define GPIO_92				130
+#define GPIO_97				131
+#define GPIO_98				132
+#define GPIO_99				133
+#define GPIO_100			134
+#define GPIO_101			135
+#define GPIO_102			136
+#define GPIO_103			137
+#define FST_SPI_CLK_FB			138
+#define GPIO_104			139
+#define GPIO_105			140
+#define GPIO_106			141
+#define GPIO_109			142
+#define GPIO_110			143
+#define GPIO_111			144
+#define GPIO_112			145
+#define GPIO_113			146
+#define GPIO_116			147
+#define GPIO_117			148
+#define GPIO_118			149
+#define GPIO_119			150
+#define GPIO_120			151
+#define GPIO_121			152
+#define GPIO_122			153
+#define GPIO_123			154
+
+/* West community pads */
+#define GPIO_124			155
+#define GPIO_125			156
+#define GPIO_126			157
+#define GPIO_127			158
+#define GPIO_128			159
+#define GPIO_129			160
+#define GPIO_130			161
+#define GPIO_131			162
+#define GPIO_132			163
+#define GPIO_133			164
+#define GPIO_134			165
+#define GPIO_135			166
+#define GPIO_136			167
+#define GPIO_137			168
+#define GPIO_138			169
+#define GPIO_139			170
+#define GPIO_146			171
+#define GPIO_147			172
+#define GPIO_148			173
+#define GPIO_149			174
+#define GPIO_150			175
+#define GPIO_151			176
+#define GPIO_152			177
+#define GPIO_153			178
+#define GPIO_154			179
+#define GPIO_155			180
+#define GPIO_209			181
+#define GPIO_210			182
+#define GPIO_211			183
+#define GPIO_212			184
+#define OSC_CLK_OUT_0			185
+#define OSC_CLK_OUT_1			186
+#define OSC_CLK_OUT_2			187
+#define OSC_CLK_OUT_3			188
+#define OSC_CLK_OUT_4			189
+#define PMU_AC_PRESENT			190
+#define PMU_BATLOW_B			191
+#define PMU_PLTRST_B			192
+#define PMU_PWRBTN_B			193
+#define PMU_RESETBUTTON_B		194
+#define PMU_SLP_S0_B			195
+#define PMU_SLP_S3_B			196
+#define PMU_SLP_S4_B			197
+#define PMU_SUSCLK			198
+#define PMU_WAKE_B			199
+#define SUS_STAT_B			200
+#define SUSPWRDNACK			201
+
+/* Southwest community pads */
+#define GPIO_205			202
+#define GPIO_206			203
+#define GPIO_207			204
+#define GPIO_208			205
+#define GPIO_156			206
+#define GPIO_157			207
+#define GPIO_158			208
+#define GPIO_159			209
+#define GPIO_160			210
+#define GPIO_161			211
+#define GPIO_162			212
+#define GPIO_163			213
+#define GPIO_164			214
+#define GPIO_165			215
+#define GPIO_166			216
+#define GPIO_167			217
+#define GPIO_168			218
+#define GPIO_169			219
+#define GPIO_170			220
+#define GPIO_171			221
+#define GPIO_172			222
+#define GPIO_179			223
+#define GPIO_173			224
+#define GPIO_174			225
+#define GPIO_175			226
+#define GPIO_176			227
+#define GPIO_177			228
+#define GPIO_178			229
+#define GPIO_186			230
+#define GPIO_182			231
+#define GPIO_183			232
+#define SMB_ALERTB			233
+#define SMB_CLK				234
+#define SMB_DATA			235
+#define LPC_ILB_SERIRQ			236
+#define LPC_CLKOUT0			237
+#define LPC_CLKOUT1			238
+#define LPC_AD0				239
+#define LPC_AD1				240
+#define LPC_AD2				241
+#define LPC_AD3				242
+#define LPC_CLKRUNB			243
+#define LPC_FRAMEB			244
+
+/* PERST_0 not defined */
+#define GPIO_PRT0_UDEF			0xFF
+
+#define TOTAL_PADS			245
+#define N_OFFSET			GPIO_0
+#define NW_OFFSET			GPIO_187
+#define W_OFFSET			GPIO_124
+#define SW_OFFSET			GPIO_205
+
+/* Macros for translating a global pad offset to a local offset */
+#define PAD_N(pad)			(pad - N_OFFSET)
+#define PAD_NW(pad)			(pad - NW_OFFSET)
+#define PAD_W(pad)			(pad - W_OFFSET)
+#define PAD_SW(pad)			(pad - SW_OFFSET)
+
+/* Linux names of the GPIO devices */
+#define GPIO_COMM_N_NAME		"INT3452:00"
+#define GPIO_COMM_NW_NAME		"INT3452:01"
+#define GPIO_COMM_W_NAME		"INT3452:02"
+#define GPIO_COMM_SW_NAME		"INT3452:03"
+
+/* Following is used in gpio asl */
+#define GPIO_COMM_NAME			"INT3452"
+#define GPIO_COMM_0_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - North"
+#define GPIO_COMM_1_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Northwest"
+#define GPIO_COMM_2_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - West"
+#define GPIO_COMM_3_DESC	\
+	"General Purpose Input/Output (GPIO) Controller - Southwest"
+
+#define GPIO_COMM0_PID			PID_GPIO_N
+#define GPIO_COMM1_PID			PID_GPIO_NW
+#define GPIO_COMM2_PID			PID_GPIO_W
+#define GPIO_COMM3_PID			PID_GPIO_SW
+
+/*
+ * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
+ * shared IRQ instead of direct IRQ, in case of overlapping, we can easily
+ * program one of the overlap to shared IRQ to avoid the conflict.
+ */
+
+/* NorthWest community pads */
+#define PMIC_I2C_SDA_IRQ		0x32
+#define GPIO_74_IRQ			0x33
+#define GPIO_75_IRQ			0x34
+#define GPIO_76_IRQ			0x35
+#define GPIO_77_IRQ			0x36
+#define GPIO_78_IRQ			0x37
+#define GPIO_79_IRQ			0x38
+#define GPIO_80_IRQ			0x39
+#define GPIO_81_IRQ			0x3A
+#define GPIO_82_IRQ			0x3B
+#define GPIO_83_IRQ			0x3C
+#define GPIO_84_IRQ			0x3D
+#define GPIO_85_IRQ			0x3E
+#define GPIO_86_IRQ			0x3F
+#define GPIO_87_IRQ			0x40
+#define GPIO_88_IRQ			0x41
+#define GPIO_89_IRQ			0x42
+#define GPIO_90_IRQ			0x43
+#define GPIO_91_IRQ			0x44
+#define GPIO_97_IRQ			0x49
+#define GPIO_98_IRQ			0x4A
+#define GPIO_99_IRQ			0x4B
+#define GPIO_100_IRQ			0x4C
+#define GPIO_101_IRQ			0x4D
+#define GPIO_102_IRQ			0x4E
+#define GPIO_103_IRQ			0x4F
+#define GPIO_104_IRQ			0x50
+#define GPIO_105_IRQ			0x51
+#define GPIO_106_IRQ			0x52
+#define GPIO_109_IRQ			0x54
+#define GPIO_110_IRQ			0x55
+#define GPIO_111_IRQ			0x56
+#define GPIO_112_IRQ			0x57
+#define GPIO_113_IRQ			0x58
+#define GPIO_116_IRQ			0x5B
+#define GPIO_117_IRQ			0x5C
+#define GPIO_118_IRQ			0x5D
+#define GPIO_119_IRQ			0x5E
+#define GPIO_120_IRQ			0x5F
+#define GPIO_121_IRQ			0x60
+#define GPIO_122_IRQ			0x61
+#define GPIO_123_IRQ			0x62
+
+/* North community pads */
+#define GPIO_0_IRQ			0x63
+#define GPIO_1_IRQ			0x64
+#define GPIO_2_IRQ			0x65
+#define GPIO_3_IRQ			0x66
+#define GPIO_4_IRQ			0x67
+#define GPIO_5_IRQ			0x68
+#define GPIO_6_IRQ			0x69
+#define GPIO_7_IRQ			0x6A
+#define GPIO_8_IRQ			0x6B
+#define GPIO_9_IRQ			0x6C
+#define GPIO_10_IRQ			0x6D
+#define GPIO_11_IRQ			0x6E
+#define GPIO_12_IRQ			0x6F
+#define GPIO_13_IRQ			0x70
+#define GPIO_14_IRQ			0x71
+#define GPIO_15_IRQ			0x72
+#define GPIO_16_IRQ			0x73
+#define GPIO_17_IRQ			0x74
+#define GPIO_18_IRQ			0x75
+#define GPIO_19_IRQ			0x76
+#define GPIO_20_IRQ			0x77
+#define GPIO_21_IRQ			0x32
+#define GPIO_22_IRQ			0x33
+#define GPIO_23_IRQ			0x34
+#define GPIO_24_IRQ			0x35
+#define GPIO_25_IRQ			0x36
+#define GPIO_26_IRQ			0x37
+#define GPIO_27_IRQ			0x38
+#define GPIO_28_IRQ			0x39
+#define GPIO_29_IRQ			0x3A
+#define GPIO_30_IRQ			0x3B
+#define GPIO_31_IRQ			0x3C
+#define GPIO_32_IRQ			0x3D
+#define GPIO_33_IRQ			0x3E
+#define GPIO_34_IRQ			0x3F
+#define GPIO_35_IRQ			0x40
+#define GPIO_36_IRQ			0x41
+#define GPIO_37_IRQ			0x42
+#define GPIO_38_IRQ			0x43
+#define GPIO_39_IRQ			0x44
+#define GPIO_40_IRQ			0x45
+#define GPIO_41_IRQ			0x46
+#define GPIO_42_IRQ			0x47
+#define GPIO_43_IRQ			0x48
+#define GPIO_44_IRQ			0x49
+#define GPIO_45_IRQ			0x4A
+#define GPIO_46_IRQ			0x4B
+#define GPIO_47_IRQ			0x4C
+#define GPIO_48_IRQ			0x4D
+#define GPIO_49_IRQ			0x4E
+#define GPIO_62_IRQ			0x5B
+#define GPIO_63_IRQ			0x5C
+#define GPIO_64_IRQ			0x5D
+#define GPIO_65_IRQ			0x5E
+#define GPIO_66_IRQ			0x5F
+#define GPIO_67_IRQ			0x60
+#define GPIO_68_IRQ			0x61
+#define GPIO_69_IRQ			0x62
+#define GPIO_70_IRQ			0x63
+#define GPIO_71_IRQ			0x64
+#define GPIO_72_IRQ			0x65
+#define GPIO_73_IRQ			0x66
+
+#endif /* _ASM_ARCH_GPIO_H_ */
@@ -5,13 +5,23 @@
 if PINCTRL_INTEL
  
 config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
-	def_bool y
+	bool
+	default y
  
 config INTEL_PINCTRL_PADCFG_PADTOL
-	def_bool n
+	bool n
  
 config INTEL_PINCTRL_IOSTANDBY
-	def_bool y
+	bool
+	default y
+
+config PINCTRL_INTEL_APL
+	bool "Support Intel Apollo Lake (APL)"
+	help
+	  Add support for Intel Apollo Lake pin-control and pin-mux settings.
+	  These are mostly read from the device tree, with the early-pads
+	  property in the host bridge and the pads property in the fsp-s
+	  subnode of the host bridge.
  
 endif
@@ -3,4 +3,5 @@
 # Copyright 2019 Google LLC
  
 obj-y += pinctrl.o
+obj-$(CONFIG_PINCTRL_INTEL_APL) += pinctrl_apl.o
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Intel Corp.
+ * Copyright 2019 Google LLC
+ *
+ * Taken partly from coreboot gpio.c
+ */
+
+#define LOG_CATEGORY UCLASS_GPIO
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+#include <p2sb.h>
+#include <asm/intel_pinctrl.h>
+#include <asm-generic/gpio.h>
+#include <asm/intel_pinctrl_defs.h>
+
+/**
+ * struct apl_gpio_platdata - platform data for each device
+ *
+ * @dtplat: of-platdata data from C struct
+ */
+struct apl_gpio_platdata {
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	/* Put this first since driver model will copy the data here */
+	struct dtd_intel_apl_pinctrl dtplat;
+#endif
+};
+
+static const struct reset_mapping rst_map[] = {
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
+	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
+};
+
+/* Groups for each community */
+static const struct pad_group apl_community_n_groups[] = {
+	INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31),		/* NORTH 0 */
+	INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B),	/* NORTH 1 */
+	INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK),	/* NORTH 2 */
+};
+
+static const struct pad_group apl_community_w_groups[] = {
+	INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1),	/* WEST 0 */
+	INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
+};
+
+static const struct pad_group apl_community_sw_groups[] = {
+	INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB),	/* SOUTHWEST 0 */
+	INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB),	/* SOUTHWEST 1 */
+};
+
+static const struct pad_group apl_community_nw_groups[] = {
+	INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B),	/* NORTHWEST 0 */
+	INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106),	/* NORTHWEST 1 */
+	INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123),	/* NORTHWEST 2 */
+};
+
+/* TODO(sjg@chromium.org): Consider moving this to device tree */
+static const struct pad_community apl_gpio_communities[] = {
+	{
+		.port = PID_GPIO_N,
+		.first_pad = N_OFFSET,
+		.last_pad = SVID0_CLK,
+		.num_gpi_regs = NUM_N_GPI_REGS,
+		.gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
+			+ NUM_SW_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_GPE_N",
+		.acpi_path = "\\_SB.GPO0",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_n_groups,
+		.num_groups = ARRAY_SIZE(apl_community_n_groups),
+	}, {
+		.port = PID_GPIO_NW,
+		.first_pad = NW_OFFSET,
+		.last_pad = GPIO_123,
+		.num_gpi_regs = NUM_NW_GPI_REGS,
+		.gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_GPE_NW",
+		.acpi_path = "\\_SB.GPO1",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_nw_groups,
+		.num_groups = ARRAY_SIZE(apl_community_nw_groups),
+	}, {
+		.port = PID_GPIO_W,
+		.first_pad = W_OFFSET,
+		.last_pad = SUSPWRDNACK,
+		.num_gpi_regs = NUM_W_GPI_REGS,
+		.gpi_status_offset = NUM_SW_GPI_REGS,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_GPE_W",
+		.acpi_path = "\\_SB.GPO2",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_w_groups,
+		.num_groups = ARRAY_SIZE(apl_community_w_groups),
+	}, {
+		.port = PID_GPIO_SW,
+		.first_pad = SW_OFFSET,
+		.last_pad = LPC_FRAMEB,
+		.num_gpi_regs = NUM_SW_GPI_REGS,
+		.gpi_status_offset = 0,
+		.pad_cfg_base = PAD_CFG_BASE,
+		.host_own_reg_0 = HOSTSW_OWN_REG_0,
+		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
+		.gpi_int_en_reg_0 = GPI_INT_EN_0,
+		.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+		.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+		.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+		.name = "GPIO_GPE_SW",
+		.acpi_path = "\\_SB.GPO3",
+		.reset_map = rst_map,
+		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_sw_groups,
+		.num_groups = ARRAY_SIZE(apl_community_sw_groups),
+	},
+};
+
+static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev)
+{
+	struct p2sb_child_platdata *pplat;
+	const struct pad_community *comm = NULL;
+	int i;
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+	struct apl_gpio_platdata *plat = dev_get_platdata(dev);
+	int ret;
+
+	/*
+	 * It would be nice to do this in the bind() method, but with
+	 * of-platdata binding happens in the order that DM finds things in the
+	 * linker list (i.e. alphabetical order by driver name). So the GPIO
+	 * device may well be bound before its parent (p2sb), and this call
+	 * will fail if p2sb is not bound yet.
+	 *
+	 * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
+	 */
+	ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
+	if (ret)
+		return log_msg_ret("Could not set port id", ret);
+#endif
+	/* Attach this device to its community structure */
+	pplat = dev_get_parent_platdata(dev);
+	for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
+		if (apl_gpio_communities[i].port == pplat->pid)
+			comm = &apl_gpio_communities[i];
+	}
+
+	return intel_pinctrl_ofdata_to_platdata(dev, comm, 2);
+}
+
+static const struct udevice_id apl_gpio_ids[] = {
+	{ .compatible = "intel,apl-pinctrl"},
+	{ }
+};
+
+U_BOOT_DRIVER(apl_pinctrl_drv) = {
+	.name		= "intel_apl_pinctrl",
+	.id		= UCLASS_PINCTRL,
+	.of_match	= apl_gpio_ids,
+	.probe		= intel_pinctrl_probe,
+	.ops		= &intel_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+	.bind		= dm_scan_fdt_dev,
+#endif
+	.ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata,
+	.priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv),
+	.platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata),
+};
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * Definitions for the GPIO subsystem on Apollolake
	4	+ *
	5	+ * Copyright (C) 2015 - 2017 Intel Corp.
	6	+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
	7	+ *
	8	+ * Placed in a separate file since some of these definitions can be used from
	9	+ * assembly code
	10	+ *
	11	+ * Taken from gpio_apl.h in coreboot
	12	+ */
	13	+
	14	+#ifndef _ASM_ARCH_GPIO_H_
	15	+#define _ASM_ARCH_GPIO_H_
	16	+
	17	+/* Port ids */
	18	+#define PID_GPIO_SW 0xC0
	19	+#define PID_GPIO_S 0xC2
	20	+#define PID_GPIO_W 0xC7
	21	+#define PID_GPIO_NW 0xC4
	22	+#define PID_GPIO_N 0xC5
	23	+#define PID_ITSS 0xD0
	24	+#define PID_RTC 0xD1
	25	+
	26	+/*
	27	+ * Miscellaneous Configuration register(MISCCFG). These are community-specific
	28	+ * registers and are meant to house miscellaneous configuration fields per
	29	+ * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent)
	30	+ */
	31	+#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */
	32	+#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */
	33	+#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */
	34	+#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */
	35	+#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */
	36	+#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */
	37	+#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */
	38	+#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */
	39	+#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */
	40	+
	41	+#define GPIO_MAX_NUM_PER_GROUP 32
	42	+
	43	+/*
	44	+ * Host Software Pad Ownership Register.
	45	+ * The pins in the community are divided into 3 groups:
	46	+ * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95
	47	+ */
	48	+#define HOSTSW_OWN_REG_0 0x80
	49	+
	50	+#define PAD_CFG_BASE 0x500
	51	+
	52	+#define GPI_INT_STS_0 0x100
	53	+#define GPI_INT_EN_0 0x110
	54	+
	55	+#define GPI_SMI_STS_0 0x140
	56	+#define GPI_SMI_EN_0 0x150
	57	+
	58	+#define NUM_N_PADS (PAD_N(SVID0_CLK) + 1)
	59	+#define NUM_NW_PADS (PAD_NW(GPIO_123) + 1)
	60	+#define NUM_W_PADS (PAD_W(SUSPWRDNACK) + 1)
	61	+#define NUM_SW_PADS (PAD_SW(LPC_FRAMEB) + 1)
	62	+
	63	+#define NUM_N_GPI_REGS \
	64	+ (ALIGN(NUM_N_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
	65	+
	66	+#define NUM_NW_GPI_REGS \
	67	+ (ALIGN(NUM_NW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
	68	+
	69	+#define NUM_W_GPI_REGS \
	70	+ (ALIGN(NUM_W_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
	71	+
	72	+#define NUM_SW_GPI_REGS \
	73	+ (ALIGN(NUM_SW_PADS, GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
	74	+
	75	+/*
	76	+ * Total number of GPI status registers across all GPIO communities in the SOC
	77	+ */
	78	+#define NUM_GPI_STATUS_REGS (NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
	79	+ + NUM_W_GPI_REGS + NUM_SW_GPI_REGS)
	80	+
	81	+/* North community pads */
	82	+#define GPIO_0 0
	83	+#define GPIO_1 1
	84	+#define GPIO_2 2
	85	+#define GPIO_3 3
	86	+#define GPIO_4 4
	87	+#define GPIO_5 5
	88	+#define GPIO_6 6
	89	+#define GPIO_7 7
	90	+#define GPIO_8 8
	91	+#define GPIO_9 9
	92	+#define GPIO_10 10
	93	+#define GPIO_11 11
	94	+#define GPIO_12 12
	95	+#define GPIO_13 13
	96	+#define GPIO_14 14
	97	+#define GPIO_15 15
	98	+#define GPIO_16 16
	99	+#define GPIO_17 17
	100	+#define GPIO_18 18
	101	+#define GPIO_19 19
	102	+#define GPIO_20 20
	103	+#define GPIO_21 21
	104	+#define GPIO_22 22
	105	+#define GPIO_23 23
	106	+#define GPIO_24 24
	107	+#define GPIO_25 25
	108	+#define GPIO_26 26
	109	+#define GPIO_27 27
	110	+#define GPIO_28 28
	111	+#define GPIO_29 29
	112	+#define GPIO_30 30
	113	+#define GPIO_31 31
	114	+#define GPIO_32 32
	115	+#define GPIO_33 33
	116	+#define GPIO_34 34
	117	+#define GPIO_35 35
	118	+#define GPIO_36 36
	119	+#define GPIO_37 37
	120	+#define GPIO_38 38
	121	+#define GPIO_39 39
	122	+#define GPIO_40 40
	123	+#define GPIO_41 41
	124	+#define GPIO_42 42
	125	+#define GPIO_43 43
	126	+#define GPIO_44 44
	127	+#define GPIO_45 45
	128	+#define GPIO_46 46
	129	+#define GPIO_47 47
	130	+#define GPIO_48 48
	131	+#define GPIO_49 49
	132	+#define GPIO_62 50
	133	+#define GPIO_63 51
	134	+#define GPIO_64 52
	135	+#define GPIO_65 53
	136	+#define GPIO_66 54
	137	+#define GPIO_67 55
	138	+#define GPIO_68 56
	139	+#define GPIO_69 57
	140	+#define GPIO_70 58
	141	+#define GPIO_71 59
	142	+#define GPIO_72 60
	143	+#define GPIO_73 61
	144	+#define JTAG_TCK 62
	145	+#define JTAG_TRST_B 63
	146	+#define JTAG_TMS 64
	147	+#define JTAG_TDI 65
	148	+#define JTAG_CX_PMODE 66
	149	+#define JTAG_CX_PREQ_B 67
	150	+#define JTAGX 68
	151	+#define JTAG_CX_PRDY_B 69
	152	+#define JTAG_TDO 70
	153	+#define CNV_BRI_DT 71
	154	+#define CNV_BRI_RSP 72
	155	+#define CNV_RGI_DT 73
	156	+#define CNV_RGI_RSP 74
	157	+#define SVID0_ALERT_B 75
	158	+#define SVID0_DATA 76
	159	+#define SVID0_CLK 77
	160	+
	161	+/* Northwest community pads */
	162	+#define GPIO_187 78
	163	+#define GPIO_188 79
	164	+#define GPIO_189 80
	165	+#define GPIO_190 81
	166	+#define GPIO_191 82
	167	+#define GPIO_192 83
	168	+#define GPIO_193 84
	169	+#define GPIO_194 85
	170	+#define GPIO_195 86
	171	+#define GPIO_196 87
	172	+#define GPIO_197 88
	173	+#define GPIO_198 89
	174	+#define GPIO_199 90
	175	+#define GPIO_200 91
	176	+#define GPIO_201 92
	177	+#define GPIO_202 93
	178	+#define GPIO_203 94
	179	+#define GPIO_204 95
	180	+#define PMC_SPI_FS0 96
	181	+#define PMC_SPI_FS1 97
	182	+#define PMC_SPI_FS2 98
	183	+#define PMC_SPI_RXD 99
	184	+#define PMC_SPI_TXD 100
	185	+#define PMC_SPI_CLK 101
	186	+#define PMIC_PWRGOOD 102
	187	+#define PMIC_RESET_B 103
	188	+#define GPIO_213 104
	189	+#define GPIO_214 105
	190	+#define GPIO_215 106
	191	+#define PMIC_THERMTRIP_B 107
	192	+#define PMIC_STDBY 108
	193	+#define PROCHOT_B 109
	194	+#define PMIC_I2C_SCL 110
	195	+#define PMIC_I2C_SDA 111
	196	+#define GPIO_74 112
	197	+#define GPIO_75 113
	198	+#define GPIO_76 114
	199	+#define GPIO_77 115
	200	+#define GPIO_78 116
	201	+#define GPIO_79 117
	202	+#define GPIO_80 118
	203	+#define GPIO_81 119
	204	+#define GPIO_82 120
	205	+#define GPIO_83 121
	206	+#define GPIO_84 122
	207	+#define GPIO_85 123
	208	+#define GPIO_86 124
	209	+#define GPIO_87 125
	210	+#define GPIO_88 126
	211	+#define GPIO_89 127
	212	+#define GPIO_90 128
	213	+#define GPIO_91 129
	214	+#define GPIO_92 130
	215	+#define GPIO_97 131
	216	+#define GPIO_98 132
	217	+#define GPIO_99 133
	218	+#define GPIO_100 134
	219	+#define GPIO_101 135
	220	+#define GPIO_102 136
	221	+#define GPIO_103 137
	222	+#define FST_SPI_CLK_FB 138
	223	+#define GPIO_104 139
	224	+#define GPIO_105 140
	225	+#define GPIO_106 141
	226	+#define GPIO_109 142
	227	+#define GPIO_110 143
	228	+#define GPIO_111 144
	229	+#define GPIO_112 145
	230	+#define GPIO_113 146
	231	+#define GPIO_116 147
	232	+#define GPIO_117 148
	233	+#define GPIO_118 149
	234	+#define GPIO_119 150
	235	+#define GPIO_120 151
	236	+#define GPIO_121 152
	237	+#define GPIO_122 153
	238	+#define GPIO_123 154
	239	+
	240	+/* West community pads */
	241	+#define GPIO_124 155
	242	+#define GPIO_125 156
	243	+#define GPIO_126 157
	244	+#define GPIO_127 158
	245	+#define GPIO_128 159
	246	+#define GPIO_129 160
	247	+#define GPIO_130 161
	248	+#define GPIO_131 162
	249	+#define GPIO_132 163
	250	+#define GPIO_133 164
	251	+#define GPIO_134 165
	252	+#define GPIO_135 166
	253	+#define GPIO_136 167
	254	+#define GPIO_137 168
	255	+#define GPIO_138 169
	256	+#define GPIO_139 170
	257	+#define GPIO_146 171
	258	+#define GPIO_147 172
	259	+#define GPIO_148 173
	260	+#define GPIO_149 174
	261	+#define GPIO_150 175
	262	+#define GPIO_151 176
	263	+#define GPIO_152 177
	264	+#define GPIO_153 178
	265	+#define GPIO_154 179
	266	+#define GPIO_155 180
	267	+#define GPIO_209 181
	268	+#define GPIO_210 182
	269	+#define GPIO_211 183
	270	+#define GPIO_212 184
	271	+#define OSC_CLK_OUT_0 185
	272	+#define OSC_CLK_OUT_1 186
	273	+#define OSC_CLK_OUT_2 187
	274	+#define OSC_CLK_OUT_3 188
	275	+#define OSC_CLK_OUT_4 189
	276	+#define PMU_AC_PRESENT 190
	277	+#define PMU_BATLOW_B 191
	278	+#define PMU_PLTRST_B 192
	279	+#define PMU_PWRBTN_B 193
	280	+#define PMU_RESETBUTTON_B 194
	281	+#define PMU_SLP_S0_B 195
	282	+#define PMU_SLP_S3_B 196
	283	+#define PMU_SLP_S4_B 197
	284	+#define PMU_SUSCLK 198
	285	+#define PMU_WAKE_B 199
	286	+#define SUS_STAT_B 200
	287	+#define SUSPWRDNACK 201
	288	+
	289	+/* Southwest community pads */
	290	+#define GPIO_205 202
	291	+#define GPIO_206 203
	292	+#define GPIO_207 204
	293	+#define GPIO_208 205
	294	+#define GPIO_156 206
	295	+#define GPIO_157 207
	296	+#define GPIO_158 208
	297	+#define GPIO_159 209
	298	+#define GPIO_160 210
	299	+#define GPIO_161 211
	300	+#define GPIO_162 212
	301	+#define GPIO_163 213
	302	+#define GPIO_164 214
	303	+#define GPIO_165 215
	304	+#define GPIO_166 216
	305	+#define GPIO_167 217
	306	+#define GPIO_168 218
	307	+#define GPIO_169 219
	308	+#define GPIO_170 220
	309	+#define GPIO_171 221
	310	+#define GPIO_172 222
	311	+#define GPIO_179 223
	312	+#define GPIO_173 224
	313	+#define GPIO_174 225
	314	+#define GPIO_175 226
	315	+#define GPIO_176 227
	316	+#define GPIO_177 228
	317	+#define GPIO_178 229
	318	+#define GPIO_186 230
	319	+#define GPIO_182 231
	320	+#define GPIO_183 232
	321	+#define SMB_ALERTB 233
	322	+#define SMB_CLK 234
	323	+#define SMB_DATA 235
	324	+#define LPC_ILB_SERIRQ 236
	325	+#define LPC_CLKOUT0 237
	326	+#define LPC_CLKOUT1 238
	327	+#define LPC_AD0 239
	328	+#define LPC_AD1 240
	329	+#define LPC_AD2 241
	330	+#define LPC_AD3 242
	331	+#define LPC_CLKRUNB 243
	332	+#define LPC_FRAMEB 244
	333	+
	334	+/* PERST_0 not defined */
	335	+#define GPIO_PRT0_UDEF 0xFF
	336	+
	337	+#define TOTAL_PADS 245
	338	+#define N_OFFSET GPIO_0
	339	+#define NW_OFFSET GPIO_187
	340	+#define W_OFFSET GPIO_124
	341	+#define SW_OFFSET GPIO_205
	342	+
	343	+/* Macros for translating a global pad offset to a local offset */
	344	+#define PAD_N(pad) (pad - N_OFFSET)
	345	+#define PAD_NW(pad) (pad - NW_OFFSET)
	346	+#define PAD_W(pad) (pad - W_OFFSET)
	347	+#define PAD_SW(pad) (pad - SW_OFFSET)
	348	+
	349	+/* Linux names of the GPIO devices */
	350	+#define GPIO_COMM_N_NAME "INT3452:00"
	351	+#define GPIO_COMM_NW_NAME "INT3452:01"
	352	+#define GPIO_COMM_W_NAME "INT3452:02"
	353	+#define GPIO_COMM_SW_NAME "INT3452:03"
	354	+
	355	+/* Following is used in gpio asl */
	356	+#define GPIO_COMM_NAME "INT3452"
	357	+#define GPIO_COMM_0_DESC \
	358	+ "General Purpose Input/Output (GPIO) Controller - North"
	359	+#define GPIO_COMM_1_DESC \
	360	+ "General Purpose Input/Output (GPIO) Controller - Northwest"
	361	+#define GPIO_COMM_2_DESC \
	362	+ "General Purpose Input/Output (GPIO) Controller - West"
	363	+#define GPIO_COMM_3_DESC \
	364	+ "General Purpose Input/Output (GPIO) Controller - Southwest"
	365	+
	366	+#define GPIO_COMM0_PID PID_GPIO_N
	367	+#define GPIO_COMM1_PID PID_GPIO_NW
	368	+#define GPIO_COMM2_PID PID_GPIO_W
	369	+#define GPIO_COMM3_PID PID_GPIO_SW
	370	+
	371	+/*
	372	+ * IOxAPIC IRQs for the GPIOs, overlap is expected as we encourage to use
	373	+ * shared IRQ instead of direct IRQ, in case of overlapping, we can easily
	374	+ * program one of the overlap to shared IRQ to avoid the conflict.
	375	+ */
	376	+
	377	+/* NorthWest community pads */
	378	+#define PMIC_I2C_SDA_IRQ 0x32
	379	+#define GPIO_74_IRQ 0x33
	380	+#define GPIO_75_IRQ 0x34
	381	+#define GPIO_76_IRQ 0x35
	382	+#define GPIO_77_IRQ 0x36
	383	+#define GPIO_78_IRQ 0x37
	384	+#define GPIO_79_IRQ 0x38
	385	+#define GPIO_80_IRQ 0x39
	386	+#define GPIO_81_IRQ 0x3A
	387	+#define GPIO_82_IRQ 0x3B
	388	+#define GPIO_83_IRQ 0x3C
	389	+#define GPIO_84_IRQ 0x3D
	390	+#define GPIO_85_IRQ 0x3E
	391	+#define GPIO_86_IRQ 0x3F
	392	+#define GPIO_87_IRQ 0x40
	393	+#define GPIO_88_IRQ 0x41
	394	+#define GPIO_89_IRQ 0x42
	395	+#define GPIO_90_IRQ 0x43
	396	+#define GPIO_91_IRQ 0x44
	397	+#define GPIO_97_IRQ 0x49
	398	+#define GPIO_98_IRQ 0x4A
	399	+#define GPIO_99_IRQ 0x4B
	400	+#define GPIO_100_IRQ 0x4C
	401	+#define GPIO_101_IRQ 0x4D
	402	+#define GPIO_102_IRQ 0x4E
	403	+#define GPIO_103_IRQ 0x4F
	404	+#define GPIO_104_IRQ 0x50
	405	+#define GPIO_105_IRQ 0x51
	406	+#define GPIO_106_IRQ 0x52
	407	+#define GPIO_109_IRQ 0x54
	408	+#define GPIO_110_IRQ 0x55
	409	+#define GPIO_111_IRQ 0x56
	410	+#define GPIO_112_IRQ 0x57
	411	+#define GPIO_113_IRQ 0x58
	412	+#define GPIO_116_IRQ 0x5B
	413	+#define GPIO_117_IRQ 0x5C
	414	+#define GPIO_118_IRQ 0x5D
	415	+#define GPIO_119_IRQ 0x5E
	416	+#define GPIO_120_IRQ 0x5F
	417	+#define GPIO_121_IRQ 0x60
	418	+#define GPIO_122_IRQ 0x61
	419	+#define GPIO_123_IRQ 0x62
	420	+
	421	+/* North community pads */
	422	+#define GPIO_0_IRQ 0x63
	423	+#define GPIO_1_IRQ 0x64
	424	+#define GPIO_2_IRQ 0x65
	425	+#define GPIO_3_IRQ 0x66
	426	+#define GPIO_4_IRQ 0x67
	427	+#define GPIO_5_IRQ 0x68
	428	+#define GPIO_6_IRQ 0x69
	429	+#define GPIO_7_IRQ 0x6A
	430	+#define GPIO_8_IRQ 0x6B
	431	+#define GPIO_9_IRQ 0x6C
	432	+#define GPIO_10_IRQ 0x6D
	433	+#define GPIO_11_IRQ 0x6E
	434	+#define GPIO_12_IRQ 0x6F
	435	+#define GPIO_13_IRQ 0x70
	436	+#define GPIO_14_IRQ 0x71
	437	+#define GPIO_15_IRQ 0x72
	438	+#define GPIO_16_IRQ 0x73
	439	+#define GPIO_17_IRQ 0x74
	440	+#define GPIO_18_IRQ 0x75
	441	+#define GPIO_19_IRQ 0x76
	442	+#define GPIO_20_IRQ 0x77
	443	+#define GPIO_21_IRQ 0x32
	444	+#define GPIO_22_IRQ 0x33
	445	+#define GPIO_23_IRQ 0x34
	446	+#define GPIO_24_IRQ 0x35
	447	+#define GPIO_25_IRQ 0x36
	448	+#define GPIO_26_IRQ 0x37
	449	+#define GPIO_27_IRQ 0x38
	450	+#define GPIO_28_IRQ 0x39
	451	+#define GPIO_29_IRQ 0x3A
	452	+#define GPIO_30_IRQ 0x3B
	453	+#define GPIO_31_IRQ 0x3C
	454	+#define GPIO_32_IRQ 0x3D
	455	+#define GPIO_33_IRQ 0x3E
	456	+#define GPIO_34_IRQ 0x3F
	457	+#define GPIO_35_IRQ 0x40
	458	+#define GPIO_36_IRQ 0x41
	459	+#define GPIO_37_IRQ 0x42
	460	+#define GPIO_38_IRQ 0x43
	461	+#define GPIO_39_IRQ 0x44
	462	+#define GPIO_40_IRQ 0x45
	463	+#define GPIO_41_IRQ 0x46
	464	+#define GPIO_42_IRQ 0x47
	465	+#define GPIO_43_IRQ 0x48
	466	+#define GPIO_44_IRQ 0x49
	467	+#define GPIO_45_IRQ 0x4A
	468	+#define GPIO_46_IRQ 0x4B
	469	+#define GPIO_47_IRQ 0x4C
	470	+#define GPIO_48_IRQ 0x4D
	471	+#define GPIO_49_IRQ 0x4E
	472	+#define GPIO_62_IRQ 0x5B
	473	+#define GPIO_63_IRQ 0x5C
	474	+#define GPIO_64_IRQ 0x5D
	475	+#define GPIO_65_IRQ 0x5E
	476	+#define GPIO_66_IRQ 0x5F
	477	+#define GPIO_67_IRQ 0x60
	478	+#define GPIO_68_IRQ 0x61
	479	+#define GPIO_69_IRQ 0x62
	480	+#define GPIO_70_IRQ 0x63
	481	+#define GPIO_71_IRQ 0x64
	482	+#define GPIO_72_IRQ 0x65
	483	+#define GPIO_73_IRQ 0x66
	484	+
	485	+#endif /* _ASM_ARCH_GPIO_H_ */
...	...	@@ -5,13 +5,23 @@
5	5	if PINCTRL_INTEL
6	6
7	7	config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
8		- def_bool y
	8	+ bool
	9	+ default y
9	10
10	11	config INTEL_PINCTRL_PADCFG_PADTOL
11		- def_bool n
	12	+ bool n
12	13
13	14	config INTEL_PINCTRL_IOSTANDBY
14		- def_bool y
	15	+ bool
	16	+ default y
	17	+
	18	+config PINCTRL_INTEL_APL
	19	+ bool "Support Intel Apollo Lake (APL)"
	20	+ help
	21	+ Add support for Intel Apollo Lake pin-control and pin-mux settings.
	22	+ These are mostly read from the device tree, with the early-pads
	23	+ property in the host bridge and the pads property in the fsp-s
	24	+ subnode of the host bridge.
15	25
16	26	endif
...	...	@@ -3,4 +3,5 @@
3	3	# Copyright 2019 Google LLC
4	4
5	5	obj-y += pinctrl.o
	6	+obj-$(CONFIG_PINCTRL_INTEL_APL) += pinctrl_apl.o
	1	+// SPDX-License-Identifier: GPL-2.0
	2	+/*
	3	+ * Copyright (C) 2017 Intel Corp.
	4	+ * Copyright 2019 Google LLC
	5	+ *
	6	+ * Taken partly from coreboot gpio.c
	7	+ */
	8	+
	9	+#define LOG_CATEGORY UCLASS_GPIO
	10	+
	11	+#include <common.h>
	12	+#include <dm.h>
	13	+#include <dt-structs.h>
	14	+#include <p2sb.h>
	15	+#include <asm/intel_pinctrl.h>
	16	+#include <asm-generic/gpio.h>
	17	+#include <asm/intel_pinctrl_defs.h>
	18	+
	19	+/**
	20	+ * struct apl_gpio_platdata - platform data for each device
	21	+ *
	22	+ * @dtplat: of-platdata data from C struct
	23	+ */
	24	+struct apl_gpio_platdata {
	25	+#if CONFIG_IS_ENABLED(OF_PLATDATA)
	26	+ /* Put this first since driver model will copy the data here */
	27	+ struct dtd_intel_apl_pinctrl dtplat;
	28	+#endif
	29	+};
	30	+
	31	+static const struct reset_mapping rst_map[] = {
	32	+ { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
	33	+ { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
	34	+ { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
	35	+};
	36	+
	37	+/* Groups for each community */
	38	+static const struct pad_group apl_community_n_groups[] = {
	39	+ INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
	40	+ INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
	41	+ INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
	42	+};
	43	+
	44	+static const struct pad_group apl_community_w_groups[] = {
	45	+ INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */
	46	+ INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
	47	+};
	48	+
	49	+static const struct pad_group apl_community_sw_groups[] = {
	50	+ INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */
	51	+ INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
	52	+};
	53	+
	54	+static const struct pad_group apl_community_nw_groups[] = {
	55	+ INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
	56	+ INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */
	57	+ INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
	58	+};
	59	+
	60	+/* TODO(sjg@chromium.org): Consider moving this to device tree */
	61	+static const struct pad_community apl_gpio_communities[] = {
	62	+ {
	63	+ .port = PID_GPIO_N,
	64	+ .first_pad = N_OFFSET,
	65	+ .last_pad = SVID0_CLK,
	66	+ .num_gpi_regs = NUM_N_GPI_REGS,
	67	+ .gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
	68	+ + NUM_SW_GPI_REGS,
	69	+ .pad_cfg_base = PAD_CFG_BASE,
	70	+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
	71	+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
	72	+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
	73	+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
	74	+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
	75	+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
	76	+ .name = "GPIO_GPE_N",
	77	+ .acpi_path = "\\_SB.GPO0",
	78	+ .reset_map = rst_map,
	79	+ .num_reset_vals = ARRAY_SIZE(rst_map),
	80	+ .groups = apl_community_n_groups,
	81	+ .num_groups = ARRAY_SIZE(apl_community_n_groups),
	82	+ }, {
	83	+ .port = PID_GPIO_NW,
	84	+ .first_pad = NW_OFFSET,
	85	+ .last_pad = GPIO_123,
	86	+ .num_gpi_regs = NUM_NW_GPI_REGS,
	87	+ .gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
	88	+ .pad_cfg_base = PAD_CFG_BASE,
	89	+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
	90	+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
	91	+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
	92	+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
	93	+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
	94	+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
	95	+ .name = "GPIO_GPE_NW",
	96	+ .acpi_path = "\\_SB.GPO1",
	97	+ .reset_map = rst_map,
	98	+ .num_reset_vals = ARRAY_SIZE(rst_map),
	99	+ .groups = apl_community_nw_groups,
	100	+ .num_groups = ARRAY_SIZE(apl_community_nw_groups),
	101	+ }, {
	102	+ .port = PID_GPIO_W,
	103	+ .first_pad = W_OFFSET,
	104	+ .last_pad = SUSPWRDNACK,
	105	+ .num_gpi_regs = NUM_W_GPI_REGS,
	106	+ .gpi_status_offset = NUM_SW_GPI_REGS,
	107	+ .pad_cfg_base = PAD_CFG_BASE,
	108	+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
	109	+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
	110	+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
	111	+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
	112	+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
	113	+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
	114	+ .name = "GPIO_GPE_W",
	115	+ .acpi_path = "\\_SB.GPO2",
	116	+ .reset_map = rst_map,
	117	+ .num_reset_vals = ARRAY_SIZE(rst_map),
	118	+ .groups = apl_community_w_groups,
	119	+ .num_groups = ARRAY_SIZE(apl_community_w_groups),
	120	+ }, {
	121	+ .port = PID_GPIO_SW,
	122	+ .first_pad = SW_OFFSET,
	123	+ .last_pad = LPC_FRAMEB,
	124	+ .num_gpi_regs = NUM_SW_GPI_REGS,
	125	+ .gpi_status_offset = 0,
	126	+ .pad_cfg_base = PAD_CFG_BASE,
	127	+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
	128	+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
	129	+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
	130	+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
	131	+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
	132	+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
	133	+ .name = "GPIO_GPE_SW",
	134	+ .acpi_path = "\\_SB.GPO3",
	135	+ .reset_map = rst_map,
	136	+ .num_reset_vals = ARRAY_SIZE(rst_map),
	137	+ .groups = apl_community_sw_groups,
	138	+ .num_groups = ARRAY_SIZE(apl_community_sw_groups),
	139	+ },
	140	+};
	141	+
	142	+static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev)
	143	+{
	144	+ struct p2sb_child_platdata *pplat;
	145	+ const struct pad_community *comm = NULL;
	146	+ int i;
	147	+
	148	+#if CONFIG_IS_ENABLED(OF_PLATDATA)
	149	+ struct apl_gpio_platdata *plat = dev_get_platdata(dev);
	150	+ int ret;
	151	+
	152	+ /*
	153	+ * It would be nice to do this in the bind() method, but with
	154	+ * of-platdata binding happens in the order that DM finds things in the
	155	+ * linker list (i.e. alphabetical order by driver name). So the GPIO
	156	+ * device may well be bound before its parent (p2sb), and this call
	157	+ * will fail if p2sb is not bound yet.
	158	+ *
	159	+ * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
	160	+ */
	161	+ ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
	162	+ if (ret)
	163	+ return log_msg_ret("Could not set port id", ret);
	164	+#endif
	165	+ /* Attach this device to its community structure */
	166	+ pplat = dev_get_parent_platdata(dev);
	167	+ for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
	168	+ if (apl_gpio_communities[i].port == pplat->pid)
	169	+ comm = &apl_gpio_communities[i];
	170	+ }
	171	+
	172	+ return intel_pinctrl_ofdata_to_platdata(dev, comm, 2);
	173	+}
	174	+
	175	+static const struct udevice_id apl_gpio_ids[] = {
	176	+ { .compatible = "intel,apl-pinctrl"},
	177	+ { }
	178	+};
	179	+
	180	+U_BOOT_DRIVER(apl_pinctrl_drv) = {
	181	+ .name = "intel_apl_pinctrl",
	182	+ .id = UCLASS_PINCTRL,
	183	+ .of_match = apl_gpio_ids,
	184	+ .probe = intel_pinctrl_probe,
	185	+ .ops = &intel_pinctrl_ops,
	186	+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	187	+ .bind = dm_scan_fdt_dev,
	188	+#endif
	189	+ .ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata,
	190	+ .priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv),
	191	+ .platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata),
	192	+};