Eric Lee / smarc-uboot

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Commit 0abddf82d54c704cf066524235b6414333e8d087

Authored by Macpaul Lin
Committed by Wolfgang Denk
1 parent dea6386b71
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

cmd_ide: enhance new feature "CONFIG_IDE_AHB" 

Although most IDE controller is designed to be connected to PCI bridge,
there are still some IDE controller support AHB interface for SoC design.

The driver implementation of these IDE-AHB controllers differ from other
IDE-PCI controller, some additional registers and commands access is required
during CMD/DATA I/O. Hence a configuration "CONFIG_IDE_AHB" in cmd_ide.c is
required to be defined to support these kinds of SoC controllers. Such as
Faraday's FTIDE020 series and Global Unichip's UINF-0301.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

Showing 3 changed files with 43 additions and 1 deletions Side-by-side Diff

... ... @@ -2751,6 +2751,14 @@
2751 2751 source code. It is used to make hardware dependant
2752 2752 initializations.
2753 2753  
  2754 +- CONFIG_IDE_AHB:
  2755 + Most IDE controllers were designed to be connected with PCI
  2756 + interface. Only few of them were designed for AHB interface.
  2757 + When software is doing ATA command and data transfer to
  2758 + IDE devices through IDE-AHB controller, some additional
  2759 + registers accessing to these kind of IDE-AHB controller
  2760 + is requierd.
  2761 +
2754 2762 - CONFIG_SYS_IMMR: Physical address of the Internal Memory.
2755 2763 DO NOT CHANGE unless you know exactly what you're
2756 2764 doing! (11-4) [MPC8xx/82xx systems only]
... ... @@ -517,8 +517,20 @@
517 517 {
518 518 debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
519 519 dev, port, val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
  520 +
  521 +#if defined(CONFIG_IDE_AHB)
  522 + if (port) {
  523 + /* write command */
  524 + ide_write_register(dev, port, val);
  525 + } else {
  526 + /* write data */
  527 + outb(val, (ATA_CURR_BASE(dev)));
  528 + }
  529 +#else
520 530 outb(val, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
  531 +#endif
521 532 }
  533 +
522 534 void ide_outb (int dev, int port, unsigned char val)
523 535 __attribute__((weak, alias("__ide_outb")));
524 536  
525 537  
... ... @@ -526,7 +538,13 @@
526 538 __ide_inb(int dev, int port)
527 539 {
528 540 uchar val;
  541 +
  542 +#if defined(CONFIG_IDE_AHB)
  543 + val = ide_read_register(dev, port);
  544 +#else
529 545 val = inb((ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)));
  546 +#endif
  547 +
530 548 debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n",
531 549 dev, port, (ATA_CURR_BASE(dev)+CONFIG_SYS_ATA_PORT_ADDR(port)), val);
532 550 return val;
... ... @@ -695,6 +713,7 @@
695 713 ide_dev_desc[i].blksz=0;
696 714 ide_dev_desc[i].lba=0;
697 715 ide_dev_desc[i].block_read=ide_read;
  716 + ide_dev_desc[i].block_write = ide_write;
698 717 if (!ide_bus_ok[IDE_BUS(i)])
699 718 continue;
700 719 ide_led (led, 1); /* LED on */
... ... @@ -902,7 +921,11 @@
902 921 static void
903 922 output_data(int dev, ulong *sect_buf, int words)
904 923 {
905   - outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words<<1);
  924 +#if defined(CONFIG_IDE_AHB)
  925 + ide_write_data(dev, sect_buf, words);
  926 +#else
  927 + outsw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1);
  928 +#endif
906 929 }
907 930 #endif /* CONFIG_IDE_SWAP_IO */
908 931  
909 932  
... ... @@ -960,7 +983,11 @@
960 983 static void
961 984 input_data(int dev, ulong *sect_buf, int words)
962 985 {
  986 +#if defined(CONFIG_IDE_AHB)
  987 + ide_read_data(dev, sect_buf, words);
  988 +#else
963 989 insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1);
  990 +#endif
964 991 }
965 992  
966 993 #endif /* CONFIG_IDE_SWAP_IO */
... ... @@ -57,5 +57,12 @@
57 57 #if defined(CONFIG_OF_IDE_FIXUP)
58 58 int ide_device_present(int dev);
59 59 #endif
  60 +
  61 +#if defined(CONFIG_IDE_AHB)
  62 +unsigned char ide_read_register(int dev, unsigned int port);
  63 +void ide_write_register(int dev, unsigned int port, unsigned char val);
  64 +void ide_read_data(int dev, ulong *sect_buf, int words);
  65 +void ide_write_data(int dev, ulong *sect_buf, int words);
  66 +#endif
60 67 #endif /* _IDE_H */