Eric Lee / smarc-uboot

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Commit 0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2

Authored by wdenk
1 parent 262381329b
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Patch by Jon Loeliger, 17 June 2004: 

Completion of the 8540ADS/8560ADS updates:
Fix some PCI and Rapid I/O memory maps,
Initialize both TSEC 1 and 2,
Initialize SDRAM
Update MAINTAINER for 85xx boards and README.mpc85xxads

Showing 20 changed files with 1260 additions and 750 deletions Side-by-side Diff

... ... @@ -2,6 +2,13 @@
2 2 Changes since U-Boot 1.1.1:
3 3 ======================================================================
4 4  
  5 +* Patch by Jon Loeliger, 17 June 2004:
  6 + Completion of the 8540ADS/8560ADS updates:
  7 + Fix some PCI and Rapid I/O memory maps,
  8 + Initialize both TSEC 1 and 2,
  9 + Initialize SDRAM
  10 + Update MAINTAINER for 85xx boards and README.mpc85xxads
  11 +
5 12 * Patch by Yuli Barcohen, 16 Jun 2004:
6 13 Remove obsolete AdderII port which was superseded by unified
7 14 AdderII/Adder87x port
... ... @@ -184,7 +184,7 @@
184 184 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
185 185  
186 186 PPChameleonEVB PPC405EP
187   -
  187 +
188 188 Reinhard Meyer <r.meyer@emk-elektronik.de>
189 189  
190 190 TOP860 MPC860T
... ... @@ -270,7 +270,7 @@
270 270  
271 271 svm_sc8xx MPC8xx
272 272  
273   -Xianghua Xiao <x.xiao@motorola.com>
  273 +Jon Loeliger <jdl@freescale.com>
274 274  
275 275 MPC8540ADS MPC8540
276 276 MPC8560ADS MPC8560
... ... @@ -376,7 +376,7 @@
376 376 Andrea Scian <andrea.scian@dave-tech.it>
377 377  
378 378 B2 ARM7TDMI (S3C44B0X)
379   -
  379 +
380 380 Alex Züpke <azu@sysgo.de>
381 381  
382 382 lart SA1100
... ... @@ -1001,13 +1001,13 @@
1001 1001 ## MPC85xx Systems
1002 1002 #########################################################################
1003 1003  
1004   -MPC8540ADS_config: unconfig
  1004 +MPC8540ADS_config: unconfig
1005 1005 @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
1006 1006  
1007   -MPC8560ADS_config: unconfig
  1007 +MPC8560ADS_config: unconfig
1008 1008 @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
1009 1009  
1010   -stxgp3_config: unconfig
  1010 +stxgp3_config: unconfig
1011 1011 @./mkconfig $(@:_config=) ppc mpc85xx stxgp3
1012 1012  
1013 1013 #########################################################################
board/dave/PPChameleonEVB/PPChameleonEVB.c
Diff comments   View file @ 0ac6f8b
... ... @@ -29,15 +29,11 @@
29 29 #include <command.h>
30 30 #include <malloc.h>
31 31  
32   -
33 32 /* ------------------------------------------------------------------------- */
34 33  
35   -
36   -
37 34 /* Prototypes */
38 35 int gunzip(void *, int, unsigned char *, int *);
39 36  
40   -
41 37 int board_early_init_f (void)
42 38 {
43 39 out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
44 40  
... ... @@ -71,11 +67,9 @@
71 67 #else
72 68 mtebc (epcr, 0x28400000); /* ebc in high-z */
73 69 #endif
74   -
75 70 return 0;
76 71 }
77 72  
78   -
79 73 /* ------------------------------------------------------------------------- */
80 74  
81 75 int misc_init_f (void)
... ... @@ -168,7 +162,6 @@
168 162 udelay(1000); /* wait 1ms */
169 163 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
170 164 udelay(1000); /* wait 1ms */
171   -
172 165 #endif
173 166  
174 167 #if 0
... ... @@ -185,7 +178,6 @@
185 178 #endif
186 179 return (0);
187 180 }
188   -
189 181  
190 182 /*
191 183 * Check Board Identity:
board/mpc8540ads/init.S
Diff comments   View file @ 0ac6f8b
... ... @@ -45,7 +45,8 @@
45 45 tlb1_entry:
46 46 entry_start
47 47  
48   - .long 0x0a /* the following data table uses a few of 16 TLB entries */
  48 + /* Number of entries in the following table */
  49 + .long 0x0c
49 50  
50 51 .long TLB1_MAS0(1,1,0)
51 52 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
52 53  
53 54  
54 55  
55 56  
56 57  
57 58  
... ... @@ -116,40 +117,57 @@
116 117  
117 118 .long TLB1_MAS0(1,8,0)
118 119 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
119   - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
120   - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  120 + .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  121 + .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
121 122  
122 123 .long TLB1_MAS0(1,9,0)
123 124 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
124 125 .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
125 126 .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
126 127  
127   - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  128 + /*
  129 + * RapidIO MMU for 512M
  130 + * Two entries, 10 and 11
  131 + */
  132 + .long TLB1_MAS0(1,10,0)
  133 + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  134 + .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  135 + .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  136 +
  137 + .long TLB1_MAS0(1,11,0)
  138 + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  139 + .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  140 + .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  141 +
  142 +
  143 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
128 144 .long TLB1_MAS0(1,15,0)
129 145 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
130 146 .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
131 147 .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
132   - #else
  148 +#else
133 149 .long TLB1_MAS0(1,15,0)
134 150 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
135 151 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
136 152 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
137   - #endif
  153 +#endif
138 154 entry_end
139 155  
140 156 /*
141 157 * LAW(Local Access Window) configuration:
142 158 *
143 159 * 0x0000_0000 0x7fff_ffff DDR 2G
144   - * 0x8000_0000 0x9fff_ffff PCI MEM 512M
  160 + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  161 + * 0xc000_0000 0xdfff_ffff RapidIO 512M
145 162 * 0xe000_0000 0xe000_ffff CCSR 1M
146   - * 0xe200_0000 0xe2ff_ffff PCI IO 16M
  163 + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
147 164 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
148 165 * 0xf800_0000 0xf80f_ffff BCSR 1M
149 166 * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
150 167 *
151   - * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
152   - * Note: If flash is 8M at default position(last 8M),no LAW needed.
  168 + * Notes:
  169 + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  170 + * If flash is 8M at default position (last 8M), no LAW needed.
153 171 */
154 172  
155 173 #if !defined(CONFIG_SPD_EEPROM)
... ... @@ -160,7 +178,7 @@
160 178 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
161 179 #endif
162 180  
163   -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
  181 +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
164 182 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
165 183  
166 184 /*
167 185  
... ... @@ -174,14 +192,14 @@
174 192 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
175 193 #endif
176 194  
177   -#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff)
  195 +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
178 196 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
179 197  
180 198 /*
181 199 * Rapid IO at 0xc000_0000 for 512 M
182 200 */
183   -#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff)
184   -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
  201 +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
  202 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
185 203  
186 204  
187 205 .section .bootpg, "ax"
board/mpc8540ads/mpc8540ads.c
Diff comments   View file @ 0ac6f8b
1 1 /*
  2 + * Copyright 2004 Freescale Semiconductor.
2 3 * (C) Copyright 2002,2003, Motorola Inc.
3 4 * Xianghua Xiao, (X.Xiao@motorola.com)
4 5 *
5 6  
6 7  
7 8  
8 9  
9 10  
10 11  
11 12  
12 13  
13 14  
14 15  
15 16  
16 17  
17 18  
18 19  
... ... @@ -24,75 +25,69 @@
24 25 */
25 26  
26 27  
27   -extern long int spd_sdram (void);
28   -
29 28 #include <common.h>
30 29 #include <asm/processor.h>
31 30 #include <asm/immap_85xx.h>
32 31 #include <spd.h>
33 32  
34   -long int fixed_sdram (void);
35   -
36 33 #if defined(CONFIG_DDR_ECC)
37   -void dma_init(void);
38   -uint dma_check(void);
39   -int dma_xfer(void *dest, uint count, void *src);
  34 +extern void ddr_enable_ecc(unsigned int dram_size);
40 35 #endif
41 36  
  37 +extern long int spd_sdram(void);
42 38  
43   -/* MPC8540ADS Board Status & Control Registers */
44   -#if 0
45   -typedef struct bscr_ {
46   - unsigned long bcsr0;
47   - unsigned long bcsr1;
48   - unsigned long bcsr2;
49   - unsigned long bcsr3;
50   - unsigned long bcsr4;
51   - unsigned long bcsr5;
52   - unsigned long bcsr6;
53   - unsigned long bcsr7;
54   -} bcsr_t;
55   -#endif
  39 +void sdram_init(void);
  40 +long int fixed_sdram(void);
56 41  
  42 +
57 43 int board_early_init_f (void)
58 44 {
59 45 #if defined(CONFIG_PCI)
60   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
61   - volatile ccsr_pcix_t *pci = &immr->im_pcix;
  46 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  47 + volatile ccsr_pcix_t *pci = &immr->im_pcix;
62 48  
63   - pci->peer &= 0xffffffdf; /* disable master abort */
  49 + pci->peer &= 0xffffffdf; /* disable master abort */
64 50 #endif
  51 +
65 52 return 0;
66 53 }
67 54  
68 55 int checkboard (void)
69 56 {
70 57 puts("Board: ADS\n");
  58 +
  59 +#ifdef CONFIG_PCI
  60 + printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  61 + CONFIG_SYS_CLK_FREQ / 1000000);
  62 +#else
  63 + printf(" PCI1: disabled\n");
  64 +#endif
  65 +
71 66 return 0;
72 67 }
73 68  
74 69  
75   -long int initdram (int board_type)
  70 +long int
  71 +initdram(int board_type)
76 72 {
77 73 long dram_size = 0;
78 74 extern long spd_sdram (void);
79 75 volatile immap_t *immap = (immap_t *)CFG_IMMR;
80   -#if !defined(CONFIG_RAM_AS_FLASH)
81   - volatile ccsr_lbc_t *lbc= &immap->im_lbc;
82   - sys_info_t sysinfo;
83   - uint temp_lbcdll = 0;
84   -#endif
85   -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
86   - volatile ccsr_gur_t *gur= &immap->im_gur;
87   -#endif
88 76  
  77 + puts("Initializing\n");
  78 +
89 79 #if defined(CONFIG_DDR_DLL)
90   - uint temp_ddrdll = 0;
  80 + {
  81 + volatile ccsr_gur_t *gur= &immap->im_gur;
  82 + uint temp_ddrdll = 0;
91 83  
92   - /* Work around to stabilize DDR DLL */
93   - temp_ddrdll = gur->ddrdllcr;
94   - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
95   - asm("sync;isync;msync");
  84 + /*
  85 + * Work around to stabilize DDR DLL
  86 + */
  87 + temp_ddrdll = gur->ddrdllcr;
  88 + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  89 + asm("sync;isync;msync");
  90 + }
96 91 #endif
97 92  
98 93 #if defined(CONFIG_SPD_EEPROM)
99 94  
100 95  
101 96  
102 97  
103 98  
104 99  
105 100  
106 101  
107 102  
108 103  
109 104  
110 105  
111 106  
112 107  
... ... @@ -101,98 +96,120 @@
101 96 dram_size = fixed_sdram ();
102 97 #endif
103 98  
104   -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
105   - get_sys_info(&sysinfo);
106   - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
107   - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
108   - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
  99 +#if defined(CONFIG_DDR_ECC)
  100 + /*
  101 + * Initialize and enable DDR ECC.
  102 + */
  103 + ddr_enable_ecc(dram_size);
  104 +#endif
  105 +
  106 + /*
  107 + * Initialize SDRAM.
  108 + */
  109 + sdram_init();
  110 +
  111 + puts(" DDR: ");
  112 + return dram_size;
  113 +}
  114 +
  115 +
  116 +/*
  117 + * Initialize SDRAM memory on the Local Bus.
  118 + */
  119 +
  120 +void sdram_init (void)
  121 +{
  122 +#if !defined(CONFIG_RAM_AS_FLASH)
  123 + sys_info_t sysinfo;
  124 + volatile immap_t *immap = (immap_t *) CFG_IMMR;
  125 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  126 + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
  127 +
  128 + puts (" SDRAM: ");
  129 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  130 +
  131 + /*
  132 + * LocalBus SDRAM is not emulating flash.
  133 + */
  134 +
  135 + /*
  136 + * Fix Local Bus clock glitch. Errata LBC11.
  137 + *
  138 + * If localbus freq is less than 66Mhz, use bypass mode,
  139 + * otherwise use DLL.
  140 + * lcrr is the local-bus clock ratio register.
  141 + */
  142 + get_sys_info (&sysinfo);
  143 + if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
  144 + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
  145 +
109 146 } else {
110   - uint pvr = get_pvr();
  147 + /*
  148 + * On REV1 boards, need to change CLKDIV before enable DLL.
  149 + * Default CLKDIV is 8, change it to 4 temporarily.
  150 + */
  151 + volatile ccsr_gur_t *gur = &immap->im_gur;
  152 + uint pvr = get_pvr ();
  153 + uint temp_lbcdll = 0;
111 154  
112 155 if (pvr == PVR_85xx_REV1) {
113   - /*
114   - * Need change CLKDIV before enable DLL.
115   - * Default CLKDIV is 8, change it to 4
116   - * temporarily.
117   - */
118   - lbc->lcrr = 0x10000004;
  156 + lbc->lcrr = 0x10000004;
119 157 }
  158 +
  159 + /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
120 160 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
121   - udelay(200);
  161 + udelay (200);
122 162 temp_lbcdll = gur->lbcdllcr;
123   - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
124   - asm("sync;isync;msync");
  163 + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
  164 + asm ("sync;isync;msync");
125 165 }
126   - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
  166 +
  167 + /*
  168 + * Setup SDRAM Base and Option Registers
  169 + */
  170 + lbc->or2 = CFG_OR2_PRELIM;
127 171 lbc->br2 = CFG_BR2_PRELIM;
128 172 lbc->lbcr = CFG_LBC_LBCR;
129   - lbc->lsdmr = CFG_LBC_LSDMR_1;
130   - asm("sync");
131   - (unsigned int) * (ulong *)0 = 0x000000ff;
132   - lbc->lsdmr = CFG_LBC_LSDMR_2;
133   - asm("sync");
134   - (unsigned int) * (ulong *)0 = 0x000000ff;
135   - lbc->lsdmr = CFG_LBC_LSDMR_3;
136   - asm("sync");
137   - (unsigned int) * (ulong *)0 = 0x000000ff;
138   - lbc->lsdmr = CFG_LBC_LSDMR_4;
139   - asm("sync");
140   - (unsigned int) * (ulong *)0 = 0x000000ff;
141   - lbc->lsdmr = CFG_LBC_LSDMR_5;
142   - asm("sync");
  173 + asm ("msync");
  174 +
143 175 lbc->lsrt = CFG_LBC_LSRT;
144   - asm("sync");
145 176 lbc->mrtpr = CFG_LBC_MRTPR;
146   - asm("sync");
147   -#endif
  177 + asm ("sync");
148 178  
149   -#if defined(CONFIG_DDR_ECC)
150   - {
151   - /* Initialize all of memory for ECC, then
152   - * enable errors */
153   - uint *p = 0;
154   - uint i = 0;
155   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
156   - volatile ccsr_ddr_t *ddr= &immap->im_ddr;
157   - dma_init();
158   - for (*p = 0; p < (uint *)(8 * 1024); p++) {
159   - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
160   - *p = (unsigned int)0xdeadbeef;
161   - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
162   - }
  179 + /*
  180 + * Configure the SDRAM controller.
  181 + */
  182 + lbc->lsdmr = CFG_LBC_LSDMR_1;
  183 + asm ("sync");
  184 + *sdram_addr = 0xff;
  185 + ppcDcbf ((unsigned long) sdram_addr);
  186 + udelay (100);
163 187  
164   - /* 8K */
165   - dma_xfer((uint *)0x2000,0x2000,(uint *)0);
166   - /* 16K */
167   - dma_xfer((uint *)0x4000,0x4000,(uint *)0);
168   - /* 32K */
169   - dma_xfer((uint *)0x8000,0x8000,(uint *)0);
170   - /* 64K */
171   - dma_xfer((uint *)0x10000,0x10000,(uint *)0);
172   - /* 128k */
173   - dma_xfer((uint *)0x20000,0x20000,(uint *)0);
174   - /* 256k */
175   - dma_xfer((uint *)0x40000,0x40000,(uint *)0);
176   - /* 512k */
177   - dma_xfer((uint *)0x80000,0x80000,(uint *)0);
178   - /* 1M */
179   - dma_xfer((uint *)0x100000,0x100000,(uint *)0);
180   - /* 2M */
181   - dma_xfer((uint *)0x200000,0x200000,(uint *)0);
182   - /* 4M */
183   - dma_xfer((uint *)0x400000,0x400000,(uint *)0);
  188 + lbc->lsdmr = CFG_LBC_LSDMR_2;
  189 + asm ("sync");
  190 + *sdram_addr = 0xff;
  191 + ppcDcbf ((unsigned long) sdram_addr);
  192 + udelay (100);
184 193  
185   - for (i = 1; i < dram_size / 0x800000; i++) {
186   - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
187   - }
  194 + lbc->lsdmr = CFG_LBC_LSDMR_3;
  195 + asm ("sync");
  196 + *sdram_addr = 0xff;
  197 + ppcDcbf ((unsigned long) sdram_addr);
  198 + udelay (100);
188 199  
189   - /* Enable errors for ECC */
190   - ddr->err_disable = 0x00000000;
191   - asm("sync;isync;msync");
192   - }
193   -#endif
  200 + lbc->lsdmr = CFG_LBC_LSDMR_4;
  201 + asm ("sync");
  202 + *sdram_addr = 0xff;
  203 + ppcDcbf ((unsigned long) sdram_addr);
  204 + udelay (100);
194 205  
195   - return dram_size;
  206 + lbc->lsdmr = CFG_LBC_LSDMR_5;
  207 + asm ("sync");
  208 + *sdram_addr = 0xff;
  209 + ppcDcbf ((unsigned long) sdram_addr);
  210 + udelay (100);
  211 +
  212 +#endif
196 213 }
197 214  
198 215  
... ... @@ -262,7 +279,7 @@
262 279 asm("sync; isync; msync");
263 280 udelay(500);
264 281 #endif
265   - return (CFG_SDRAM_SIZE * 1024 * 1024);
  282 + return CFG_SDRAM_SIZE * 1024 * 1024;
266 283 }
267 284 #endif /* !defined(CONFIG_SPD_EEPROM) */
board/mpc8560ads/init.S
Diff comments   View file @ 0ac6f8b
... ... @@ -45,7 +45,8 @@
45 45 tlb1_entry:
46 46 entry_start
47 47  
48   - .long 0x0a /* the following data table uses a few of 16 TLB entries */
  48 + /* Number of entries in the following table */
  49 + .long 0x0c
49 50  
50 51 .long TLB1_MAS0(1,1,0)
51 52 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
52 53  
53 54  
54 55  
55 56  
56 57  
57 58  
... ... @@ -116,40 +117,57 @@
116 117  
117 118 .long TLB1_MAS0(1,8,0)
118 119 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
119   - .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
120   - .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  120 + .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  121 + .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
121 122  
122 123 .long TLB1_MAS0(1,9,0)
123 124 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
124 125 .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
125 126 .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
126 127  
127   - #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
  128 + /*
  129 + * RapidIO MMU for 512M
  130 + * Two entries, 10 and 11
  131 + */
  132 + .long TLB1_MAS0(1,10,0)
  133 + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  134 + .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  135 + .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  136 +
  137 + .long TLB1_MAS0(1,11,0)
  138 + .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
  139 + .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
  140 + .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
  141 +
  142 +
  143 +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
128 144 .long TLB1_MAS0(1,15,0)
129 145 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
130 146 .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
131 147 .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
132   - #else
  148 +#else
133 149 .long TLB1_MAS0(1,15,0)
134 150 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
135 151 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
136 152 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
137   - #endif
  153 +#endif
138 154 entry_end
139 155  
140 156 /*
141 157 * LAW(Local Access Window) configuration:
142 158 *
143 159 * 0x0000_0000 0x7fff_ffff DDR 2G
144   - * 0x8000_0000 0x9fff_ffff PCI MEM 512M
  160 + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
  161 + * 0xc000_0000 0xdfff_ffff RapidIO 512M
145 162 * 0xe000_0000 0xe000_ffff CCSR 1M
146   - * 0xe200_0000 0xe2ff_ffff PCI IO 16M
  163 + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
147 164 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
148 165 * 0xf800_0000 0xf80f_ffff BCSR 1M
149 166 * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
150 167 *
151   - * Note: CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
152   - * Note: If flash is 8M at default position(last 8M),no LAW needed.
  168 + * Notes:
  169 + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  170 + * If flash is 8M at default position (last 8M), no LAW needed.
153 171 */
154 172  
155 173 #if !defined(CONFIG_SPD_EEPROM)
... ... @@ -160,7 +178,7 @@
160 178 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
161 179 #endif
162 180  
163   -#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
  181 +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
164 182 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
165 183  
166 184 /*
167 185  
... ... @@ -174,14 +192,14 @@
174 192 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
175 193 #endif
176 194  
177   -#define LAWBAR3 ((CFG_PCI_IO_BASE>>12) & 0xfffff)
  195 +#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
178 196 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
179 197  
180 198 /*
181 199 * Rapid IO at 0xc000_0000 for 512 M
182 200 */
183   -#define LAWBAR4 ((CFG_RAPID_IO_BASE>>12) & 0xfffff)
184   -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
  201 +#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
  202 +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
185 203  
186 204  
187 205 .section .bootpg, "ax"
board/mpc8560ads/mpc8560ads.c
Diff comments   View file @ 0ac6f8b
... ... @@ -25,8 +25,6 @@
25 25 */
26 26  
27 27  
28   -extern long int spd_sdram (void);
29   -
30 28 #include <common.h>
31 29 #include <asm/processor.h>
32 30 #include <asm/immap_85xx.h>
33 31  
... ... @@ -34,8 +32,16 @@
34 32 #include <spd.h>
35 33 #include <miiphy.h>
36 34  
37   -long int fixed_sdram (void);
  35 +#if defined(CONFIG_DDR_ECC)
  36 +extern void ddr_enable_ecc(unsigned int dram_size);
  37 +#endif
38 38  
  39 +extern long int spd_sdram(void);
  40 +
  41 +void sdram_init(void);
  42 +long int fixed_sdram(void);
  43 +
  44 +
39 45 /*
40 46 * I/O Port configuration table
41 47 *
... ... @@ -190,8 +196,11 @@
190 196 }
191 197 };
192 198  
193   -/* MPC8560ADS Board Status & Control Registers */
194   -typedef struct bscr_ {
  199 +
  200 +/*
  201 + * MPC8560ADS Board Status & Control Registers
  202 + */
  203 +typedef struct bcsr_ {
195 204 volatile unsigned char bcsr0;
196 205 volatile unsigned char bcsr1;
197 206 volatile unsigned char bcsr2;
198 207  
199 208  
... ... @@ -203,11 +212,12 @@
203 212 int board_early_init_f (void)
204 213 {
205 214 #if defined(CONFIG_PCI)
206   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
207   - volatile ccsr_pcix_t *pci = &immr->im_pcix;
  215 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  216 + volatile ccsr_pcix_t *pci = &immr->im_pcix;
208 217  
209   - pci->peer &= 0xfffffffdf; /* disable master abort */
  218 + pci->peer &= 0xffffffdf; /* disable master abort */
210 219 #endif
  220 +
211 221 return 0;
212 222 }
213 223  
214 224  
215 225  
216 226  
217 227  
218 228  
219 229  
... ... @@ -237,35 +247,41 @@
237 247 #endif /* CONFIG_MII */
238 248 }
239 249  
240   -
241 250 int checkboard (void)
242 251 {
243 252 puts("Board: ADS\n");
  253 +
  254 +#ifdef CONFIG_PCI
  255 + printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  256 + CONFIG_SYS_CLK_FREQ / 1000000);
  257 +#else
  258 + printf(" PCI1: disabled\n");
  259 +#endif
244 260 return 0;
245 261 }
246 262  
247 263  
248   -long int initdram (int board_type)
  264 +long int
  265 +initdram(int board_type)
249 266 {
250 267 long dram_size = 0;
251 268 extern long spd_sdram (void);
252 269 volatile immap_t *immap = (immap_t *)CFG_IMMR;
253   -#if !defined(CONFIG_RAM_AS_FLASH)
254   - volatile ccsr_lbc_t *lbc= &immap->im_lbc;
255   - sys_info_t sysinfo;
256   - uint temp_lbcdll = 0;
257   -#endif
258   -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
259   - volatile ccsr_gur_t *gur= &immap->im_gur;
260   -#endif
261 270  
  271 + puts("Initializing\n");
  272 +
262 273 #if defined(CONFIG_DDR_DLL)
263   - uint temp_ddrdll = 0;
  274 + {
  275 + volatile ccsr_gur_t *gur= &immap->im_gur;
  276 + uint temp_ddrdll = 0;
264 277  
265   - /* Work around to stabilize DDR DLL */
266   - temp_ddrdll = gur->ddrdllcr;
267   - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
268   - asm("sync;isync;msync");
  278 + /*
  279 + * Work around to stabilize DDR DLL
  280 + */
  281 + temp_ddrdll = gur->ddrdllcr;
  282 + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  283 + asm("sync;isync;msync");
  284 + }
269 285 #endif
270 286  
271 287 #if defined(CONFIG_SPD_EEPROM)
272 288  
273 289  
274 290  
275 291  
276 292  
277 293  
278 294  
279 295  
280 296  
281 297  
282 298  
283 299  
284 300  
285 301  
... ... @@ -274,98 +290,120 @@
274 290 dram_size = fixed_sdram ();
275 291 #endif
276 292  
277   -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
278   - get_sys_info(&sysinfo);
279   - /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
280   - if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
281   - lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
  293 +#if defined(CONFIG_DDR_ECC)
  294 + /*
  295 + * Initialize and enable DDR ECC.
  296 + */
  297 + ddr_enable_ecc(dram_size);
  298 +#endif
  299 +
  300 + /*
  301 + * Initialize SDRAM.
  302 + */
  303 + sdram_init();
  304 +
  305 + puts(" DDR: ");
  306 + return dram_size;
  307 +}
  308 +
  309 +
  310 +/*
  311 + * Initialize SDRAM memory on the Local Bus.
  312 + */
  313 +
  314 +void sdram_init (void)
  315 +{
  316 +#if !defined(CONFIG_RAM_AS_FLASH)
  317 + sys_info_t sysinfo;
  318 + volatile immap_t *immap = (immap_t *) CFG_IMMR;
  319 + volatile ccsr_lbc_t *lbc = &immap->im_lbc;
  320 + uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
  321 +
  322 + puts (" SDRAM: ");
  323 + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
  324 +
  325 + /*
  326 + * LocalBus SDRAM is not emulating flash.
  327 + */
  328 +
  329 + /*
  330 + * Fix Local Bus clock glitch. Errata LBC11.
  331 + *
  332 + * If localbus freq is less than 66Mhz, use bypass mode,
  333 + * otherwise use DLL.
  334 + * lcrr is the local-bus clock ratio register.
  335 + */
  336 + get_sys_info (&sysinfo);
  337 + if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
  338 + lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
  339 +
282 340 } else {
283   - uint pvr = get_pvr();
  341 + /*
  342 + * On REV1 boards, need to change CLKDIV before enable DLL.
  343 + * Default CLKDIV is 8, change it to 4 temporarily.
  344 + */
  345 + volatile ccsr_gur_t *gur = &immap->im_gur;
  346 + uint pvr = get_pvr ();
  347 + uint temp_lbcdll = 0;
284 348  
285 349 if (pvr == PVR_85xx_REV1) {
286   - /*
287   - * Need change CLKDIV before enable DLL.
288   - * Default CLKDIV is 8, change it to 4
289   - * temporarily.
290   - */
291   - lbc->lcrr = 0x10000004;
  350 + lbc->lcrr = 0x10000004;
292 351 }
  352 +
  353 + /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
293 354 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
294   - udelay(200);
  355 + udelay (200);
295 356 temp_lbcdll = gur->lbcdllcr;
296   - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
297   - asm("sync;isync;msync");
  357 + gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
  358 + asm ("sync;isync;msync");
298 359 }
299   - lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
  360 +
  361 + /*
  362 + * Setup SDRAM Base and Option Registers
  363 + */
  364 + lbc->or2 = CFG_OR2_PRELIM;
300 365 lbc->br2 = CFG_BR2_PRELIM;
301 366 lbc->lbcr = CFG_LBC_LBCR;
302   - lbc->lsdmr = CFG_LBC_LSDMR_1;
303   - asm("sync");
304   - (unsigned int) * (ulong *)0 = 0x000000ff;
305   - lbc->lsdmr = CFG_LBC_LSDMR_2;
306   - asm("sync");
307   - (unsigned int) * (ulong *)0 = 0x000000ff;
308   - lbc->lsdmr = CFG_LBC_LSDMR_3;
309   - asm("sync");
310   - (unsigned int) * (ulong *)0 = 0x000000ff;
311   - lbc->lsdmr = CFG_LBC_LSDMR_4;
312   - asm("sync");
313   - (unsigned int) * (ulong *)0 = 0x000000ff;
314   - lbc->lsdmr = CFG_LBC_LSDMR_5;
315   - asm("sync");
  367 + asm ("msync");
  368 +
316 369 lbc->lsrt = CFG_LBC_LSRT;
317   - asm("sync");
318 370 lbc->mrtpr = CFG_LBC_MRTPR;
319   - asm("sync");
320   -#endif
  371 + asm ("sync");
321 372  
322   -#if defined(CONFIG_DDR_ECC)
323   - {
324   - /* Initialize all of memory for ECC, then
325   - * enable errors */
326   - uint *p = 0;
327   - uint i = 0;
328   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
329   - volatile ccsr_ddr_t *ddr= &immap->im_ddr;
330   - dma_init();
331   - for (*p = 0; p < (uint *)(8 * 1024); p++) {
332   - if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
333   - *p = (unsigned int)0xdeadbeef;
334   - if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
335   - }
  373 + /*
  374 + * Configure the SDRAM controller.
  375 + */
  376 + lbc->lsdmr = CFG_LBC_LSDMR_1;
  377 + asm ("sync");
  378 + *sdram_addr = 0xff;
  379 + ppcDcbf ((unsigned long) sdram_addr);
  380 + udelay (100);
336 381  
337   - /* 8K */
338   - dma_xfer((uint *)0x2000,0x2000,(uint *)0);
339   - /* 16K */
340   - dma_xfer((uint *)0x4000,0x4000,(uint *)0);
341   - /* 32K */
342   - dma_xfer((uint *)0x8000,0x8000,(uint *)0);
343   - /* 64K */
344   - dma_xfer((uint *)0x10000,0x10000,(uint *)0);
345   - /* 128k */
346   - dma_xfer((uint *)0x20000,0x20000,(uint *)0);
347   - /* 256k */
348   - dma_xfer((uint *)0x40000,0x40000,(uint *)0);
349   - /* 512k */
350   - dma_xfer((uint *)0x80000,0x80000,(uint *)0);
351   - /* 1M */
352   - dma_xfer((uint *)0x100000,0x100000,(uint *)0);
353   - /* 2M */
354   - dma_xfer((uint *)0x200000,0x200000,(uint *)0);
355   - /* 4M */
356   - dma_xfer((uint *)0x400000,0x400000,(uint *)0);
  382 + lbc->lsdmr = CFG_LBC_LSDMR_2;
  383 + asm ("sync");
  384 + *sdram_addr = 0xff;
  385 + ppcDcbf ((unsigned long) sdram_addr);
  386 + udelay (100);
357 387  
358   - for (i = 1; i < dram_size / 0x800000; i++) {
359   - dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
360   - }
  388 + lbc->lsdmr = CFG_LBC_LSDMR_3;
  389 + asm ("sync");
  390 + *sdram_addr = 0xff;
  391 + ppcDcbf ((unsigned long) sdram_addr);
  392 + udelay (100);
361 393  
362   - /* Enable errors for ECC */
363   - ddr->err_disable = 0x00000000;
364   - asm("sync;isync;msync");
365   - }
366   -#endif
  394 + lbc->lsdmr = CFG_LBC_LSDMR_4;
  395 + asm ("sync");
  396 + *sdram_addr = 0xff;
  397 + ppcDcbf ((unsigned long) sdram_addr);
  398 + udelay (100);
367 399  
368   - return dram_size;
  400 + lbc->lsdmr = CFG_LBC_LSDMR_5;
  401 + asm ("sync");
  402 + *sdram_addr = 0xff;
  403 + ppcDcbf ((unsigned long) sdram_addr);
  404 + udelay (100);
  405 +
  406 +#endif
369 407 }
370 408  
371 409  
... ... @@ -403,6 +441,7 @@
403 441 }
404 442 #endif
405 443  
  444 +
406 445 #if !defined(CONFIG_SPD_EEPROM)
407 446 /*************************************************************************
408 447 * fixed sdram init -- doesn't use serial presence detect.
... ... @@ -434,7 +473,7 @@
434 473 asm("sync; isync; msync");
435 474 udelay(500);
436 475 #endif
437   - return ( CFG_SDRAM_SIZE * 1024 * 1024);
  476 + return CFG_SDRAM_SIZE * 1024 * 1024;
438 477 }
439 478 #endif /* !defined(CONFIG_SPD_EEPROM) */
... ... @@ -174,16 +174,6 @@
174 174 #endif /* CONFIG_WATCHDOG */
175 175  
176 176 #if defined(CONFIG_DDR_ECC)
177   -__inline__ void dcbz(const void* addr)
178   -{
179   - __asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
180   -}
181   -
182   -__inline__ void dcbf(const void* addr)
183   -{
184   - __asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
185   -}
186   -
187 177 void dma_init(void) {
188 178 volatile immap_t *immap = (immap_t *)CFG_IMMR;
189 179 volatile ccsr_dma_t *dma = &immap->im_dma;
1 1 /*
  2 + * Copyright 2004 Freescale Semiconductor.
2 3 * Copyright (C) 2003 Motorola Inc.
3 4 * Xianghua Xiao (x.xiao@motorola.com)
4 5 *
5 6  
6 7  
7 8  
... ... @@ -28,17 +29,23 @@
28 29 #include <asm/cpm_85xx.h>
29 30 #include <pci.h>
30 31  
  32 +
31 33 #if defined(CONFIG_PCI)
  34 +
  35 +
32 36 /*
33 37 * Initialize PCI Devices, report devices found.
34 38 */
  39 +
35 40 #ifndef CONFIG_PCI_PNP
36 41 static struct pci_config_table pci_mpc85xxads_config_table[] = {
37   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID,
38   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
39   - PCI_ENET0_MEMADDR,
40   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
41   - { }
  42 + {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  43 + PCI_IDSEL_NUMBER, PCI_ANY_ID,
  44 + pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
  45 + PCI_ENET0_MEMADDR,
  46 + PCI_COMMAND_MEMORY |
  47 + PCI_COMMAND_MASTER}},
  48 + {}
42 49 };
43 50 #endif
44 51  
45 52  
46 53  
47 54  
48 55  
49 56  
50 57  
51 58  
52 59  
53 60  
54 61  
55 62  
56 63  
57 64  
58 65  
... ... @@ -48,61 +55,62 @@
48 55 #endif
49 56 };
50 57  
51   -void pci_init_board(void)
  58 +
  59 +void pci_init_board (void)
52 60 {
53   - struct pci_controller* hose = (struct pci_controller *)&local_hose;
54   - volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
55   - volatile ccsr_pcix_t *pcix = &immap->im_pcix;
  61 + struct pci_controller *hose = (struct pci_controller *) &local_hose;
  62 + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
  63 + volatile ccsr_pcix_t *pcix = &immap->im_pcix;
56 64  
57   - u16 reg16;
  65 + u16 reg16;
58 66  
59   - hose->first_busno = 0;
60   - hose->last_busno = 0xff;
  67 + hose->first_busno = 0;
  68 + hose->last_busno = 0xff;
61 69  
62   - pci_set_region(hose->regions + 0,
63   - CFG_PCI_MEM_BASE,
64   - CFG_PCI_MEM_PHYS,
65   - (CFG_PCI_MEM_SIZE/2),
66   - PCI_REGION_MEM);
  70 + pci_set_region (hose->regions + 0,
  71 + CFG_PCI1_MEM_BASE,
  72 + CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
67 73  
68   - pci_set_region(hose->regions + 1,
69   - (CFG_PCI_MEM_BASE+0x08000000),
70   - (CFG_PCI_MEM_PHYS+0x08000000),
71   - 0x1000000, /* 16M */
72   - PCI_REGION_IO);
  74 + pci_set_region (hose->regions + 1,
  75 + CFG_PCI1_IO_BASE,
  76 + CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
73 77  
74   - hose->region_count = 2;
  78 + hose->region_count = 2;
75 79  
76   - pci_setup_indirect(hose,
77   - (CFG_IMMR+0x8000),
78   - (CFG_IMMR+0x8004));
  80 + pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
79 81  
80   - pci_register_hose(hose);
  82 + pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, &reg16);
  83 + reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  84 + pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
81 85  
82   - hose->last_busno = pci_hose_scan(hose);
  86 + /*
  87 + * Clear non-reserved bits in status register.
  88 + */
  89 + pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
  90 + pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
83 91  
84   - pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
85   - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
86   - pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
  92 + pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  93 + pcix->potear1 = 0x00000000;
  94 + pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  95 + pcix->powbear1 = 0x00000000;
  96 + pcix->powar1 = 0x8004401c; /* 512M MEM space */
87 97  
88   - /* Clear non-reserved bits in status register */
89   - pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
90   - pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
  98 + pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  99 + pcix->potear2 = 0x00000000;
  100 + pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  101 + pcix->powbear2 = 0x00000000;
  102 + pcix->powar2 = 0x80088017; /* 16M IO space */
91 103  
92   - pcix->potar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
93   - pcix->potear1 = 0x00000000;
94   - pcix->powbar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
95   - pcix->powbear1 = 0x00000000;
96   - pcix->powar1 = 0x8004401a; /* 128M MEM space */
97   - pcix->potar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) & 0x000fffff;
98   - pcix->potear2 = 0x00000000;
99   - pcix->powbar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff;
100   - pcix->powbear2 = 0x00000000;
101   - pcix->powar2 = 0x80088017; /* 16M IO space */
102   - pcix->pitar1 = 0x00000000;
103   - pcix->piwbar1 = 0x00000000;
104   - pcix->piwar1 = 0xa0F5501f;
  104 + pcix->pitar1 = 0x00000000;
  105 + pcix->piwbar1 = 0x00000000;
  106 + pcix->piwar1 = 0xa0F5501f;
105 107  
  108 + /*
  109 + * Hose scan.
  110 + */
  111 + pci_register_hose (hose);
  112 + hose->last_busno = pci_hose_scan (hose);
106 113 }
  114 +
107 115 #endif /* CONFIG_PCI */
... ... @@ -130,7 +130,6 @@
130 130 /* disable d-cache */
131 131 li r0,0x0
132 132 mtspr L1CSR0,r0
133   - isync
134 133  
135 134 /* invalidate i-cache */
136 135 mfspr r0,L1CSR1
... ... @@ -144,7 +143,6 @@
144 143 isync
145 144  
146 145 /* clear registers */
147   - sync
148 146 li r0,0
149 147 mtspr SRR0,r0
150 148 mtspr SRR1,r0
151 149  
152 150  
... ... @@ -158,11 +156,8 @@
158 156 mtspr DEAR,r0
159 157  
160 158 mtspr DBCR0,r0
161   - isync
162 159 mtspr DBCR1,r0
163   - isync
164 160 mtspr DBCR2,r0
165   - isync
166 161 mtspr IAC1,r0
167 162 mtspr IAC2,r0
168 163 mtspr DAC1,r0
169 164  
170 165  
171 166  
172 167  
173 168  
... ... @@ -171,26 +166,13 @@
171 166 mfspr r1,DBSR
172 167 mtspr DBSR,r1 /* Clear all valid bits */
173 168  
174   - isync
175 169 mtspr PID0,r0
176   - isync
177 170 mtspr PID1,r0
178   - isync
179 171 mtspr PID2,r0
180   - isync
181   -
182 172 mtspr TCR,r0
183 173  
184 174 mtspr BUCSR,r0 /* disable branch prediction */
185   - isync
186   -
187   - mtspr HID0,r0
188   - isync
189   - mtspr HID1,r0
190   - isync
191   -
192 175 mtspr MAS4,r0
193   - isync
194 176 mtspr MAS6,r0
195 177 isync
196 178  
197 179  
... ... @@ -376,9 +358,9 @@
376 358 isync
377 359  
378 360 /* Enable Time Base and Select Time Base Clock */
379   - li r0,0x4000 /* time base is processor clock */
  361 + lis r0,HID0_EMCP@h /* Enable machine check */
  362 + ori r0,r0,0x4000 /* time base is processor clock */
380 363 mtspr HID0,r0
381   - isync
382 364  
383 365 #if defined(CONFIG_ADDR_STREAMING)
384 366 li r0,0x3000
385 367  
386 368  
387 369  
388 370  
... ... @@ -386,31 +368,26 @@
386 368 li r0,0x1000
387 369 #endif
388 370 mtspr HID1,r0
389   - isync
390 371  
391 372 /* Enable Branch Prediction */
392 373 #if defined(CONFIG_BTB)
393 374 li r0,0x201 /* BBFI = 1, BPEN = 1 */
394 375 mtspr BUCSR,r0
395   - isync
396 376 #endif
397 377  
398 378 #if defined(CFG_INIT_DBCR)
399 379 lis r1,0xffff
400 380 ori r1,r1,0xffff
401   - mtspr dbsr,r1 /* Clear all status bits */
  381 + mtspr DBSR,r1 /* Clear all status bits */
402 382 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
403 383 ori r0,r0,CFG_INIT_DBCR@l
404   - mtspr dbcr0,r0
405   - isync
  384 + mtspr DBCR0,r0
406 385 #endif
407 386  
408 387 /* L1 DCache is used for initial RAM */
409 388 mfspr r2, L1CSR0
410 389 ori r2, r2, 0x0003
411 390 oris r2, r2, 0x0001
412   - msync
413   - isync
414 391 mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
415 392 isync
416 393  
417 394  
... ... @@ -457,9 +434,8 @@
457 434 bl cpu_init_f
458 435 bl icache_enable
459 436 bl board_init_f
460   - sync
  437 + isync
461 438  
462   -
463 439 /* --FIXME-- machine check with MCSRRn and rfmci */
464 440  
465 441 .globl _start_of_vectors
... ... @@ -920,6 +896,18 @@
920 896 .globl ppcDcbi
921 897 ppcDcbi:
922 898 dcbi r0,r3
  899 + blr
  900 +
  901 +/*--------------------------------------------------------------------------
  902 + * Function: ppcDcbz
  903 + * Description: Data Cache block zero.
  904 + * Input: r3 = effective address
  905 + * Output: none.
  906 + *-------------------------------------------------------------------------- */
  907 +
  908 + .globl ppcDcbz
  909 +ppcDcbz:
  910 + dcbz r0,r3
923 911 blr
924 912  
925 913 /*------------------------------------------------------------------------------- */
doc/README.mpc85xxads
Diff comments   View file @ 0ac6f8b
... ... @@ -15,7 +15,7 @@
15 15 shipped with your board. Then apply the following changes:
16 16 SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
17 17 SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
18   - SW11[2]='OFF for 8560, ON for 8540' (single switch to toggle 8540.8560 mode)
  18 + SW11[2]='OFF for 8560, ON for 8540' (toggle 8540.8560 mode)
19 19 SW11[7]='ON' (rev2), 'OFF' (rev1)
20 20 SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
21 21 SW22[1-4]="OFF OFF ON OFF"
... ... @@ -26,7 +26,8 @@
26 26 have to change the system clock from the default 66Mhz to 33Mhz by
27 27 setting SW15[1]="OFF" and SW17[8]="OFF". After that you may also need
28 28 double your platform clock(SW6) because the system clock is now only
29   - half of its original value.
  29 + half of its original value. For example, if at 66MHz your system
  30 + clock showed SW6[0:1] = 01, then at 33MHz SW6[0:1] it should be 10.
30 31  
31 32 1.3 SW6 is a very important switch, it decides your platform clock and CPU
32 33 clock based on the on-board system clock(default 66MHz). Check the
... ... @@ -42,7 +43,7 @@
42 43 0x0000_0000 0x7fff_ffff DDR 2G
43 44 0x8000_0000 0x9fff_ffff PCI MEM 512M
44 45 0xc000_0000 0xdfff_ffff Rapid IO 512M
45   - 0xe000_0000 0xe000_ffff CCSR 1M
  46 + 0xe000_0000 0xe00f_ffff CCSR 1M
46 47 0xe200_0000 0xe2ff_ffff PCI IO 16M
47 48 0xf000_0000 0xf7ff_ffff SDRAM 128M
48 49 0xf800_0000 0xf80f_ffff BCSR 1M
49 50  
... ... @@ -56,11 +57,12 @@
56 57 arch/ppc/configs/mpc8540_ads_defconfig
57 58 arch/ppc/configs/mpc8560_ads_defconfig
58 59  
59   -
60 60 3. DEFINITIONS AND COMPILATION
61 61  
62   -3.1 Explanation on NEW definitions in include/configs/MPC8540ADS.h and include/
63   - configs/MPC8560ADS.h
  62 +3.1 Explanation on NEW definitions in:
  63 + include/configs/MPC8540ADS.h
  64 + include/configs/MPC8560ADS.h
  65 +
64 66 CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
65 67 CONFIG_E500 BOOKE e500 family(Motorola)
66 68 CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
67 69  
68 70  
69 71  
70 72  
71 73  
72 74  
73 75  
74 76  
75 77  
76 78  
... ... @@ -69,50 +71,64 @@
69 71 CONFIG_MPC8540ADS MPC8540ADS board specific
70 72 CONFIG_MPC8560ADS MPC8560ADS board specific
71 73 CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
72   - CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also
73   - manual config the DDR after undef this definition.
  74 + CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can
  75 + also manual config the DDR after undef this
  76 + definition.
74 77 CONFIG_DDR_ECC only for ECC DDR module
75   - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more stability.
76   - CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into localbus
77   - SDRAM and treat localbus SDRAM as a flash. We use this
78   - memory based U-Boot before flash is working while Metrowerks
79   - and Windriver are still working on their flash/JTAG tools.
80   - if you can program the flash directly, undef this.
81   - Other than the above definitions, the rest in the config files are straightforward.
  78 + CONFIG_DDR_DLL DLL fix on some ADS boards needed for more
  79 + stability.
  80 + CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into
  81 + localbus SDRAM and treat localbus SDRAM as a
  82 + flash. We use this memory based U-Boot
  83 + before flash is working while Metrowerks and
  84 + Windriver are still working on their
  85 + flash/JTAG tools. if you can program the
  86 + flash directly, undef this.
82 87  
  88 +Other than the above definitions, the rest in the config files are
  89 +straightforward.
  90 +
  91 +
83 92 3.2 Compilation
84   - export CROSS_COMPILE=your-cross-compile-prefix(assuming you're using BASH shell)
85   - cd u-boot
86   - make distclean
87   - make MPC8560ADS_config (or make MPC8540ADS_config)
88   - make
89 93  
  94 + Assuming you're using BASH shell:
90 95  
  96 + export CROSS_COMPILE=your-cross-compile-prefix
  97 + cd u-boot
  98 + make distclean
  99 + make MPC8560ADS_config (or make MPC8540ADS_config)
  100 + make
  101 +
91 102 4. Notes:
92 103  
93 104 4.1 When connecting with kermit, the following commands must be present.in
94   - your .kermrc file. These are especially important when booting as
95   - MPC8560, as the serial console will not work without them:
  105 + your .kermrc file. These are especially important when booting as
  106 + MPC8560, as the serial console will not work without them:
96 107  
97   -set speed 115200
98   -set carrier-watch off
99   -set handshake none
100   -set flow-control none
101   -robust
  108 + set speed 115200
  109 + set carrier-watch off
  110 + set handshake none
  111 + set flow-control none
  112 + robust
102 113  
103   -4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC ethernet. If that
104   - happens, you can try the following steps to make network work:
105   - MPC8560ADS>tftp 1000000 pImage
106   - (if it hangs, use Ctrl-C to quit)
107   - MPC8560ADS>nm fdf24524
108   - >0
109   - >1
110   - >. (to quit this memory operation)
111   - MPC8560ADS>tftp 1000000 pImage
112 114  
113   -4.3 If you're one of the early developers using the Rev1 8540/8560 chips, please use U-Boot
114   - 1.0.0, as the newer silicon will only support Rev2 and future revisions of 8540/8560.
  115 +4.2 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC
  116 + ethernet. If that happens, you can try the following steps to make
  117 + network work:
115 118  
  119 + MPC8560ADS>tftp 1000000 pImage
  120 + (if it hangs, use Ctrl-C to quit)
  121 + MPC8560ADS>nm fdf24524
  122 + >0
  123 + >1
  124 + >. (to quit this memory operation)
  125 + MPC8560ADS>tftp 1000000 pImage
  126 +
  127 +4.3 If you're one of the early developers using the Rev1 8540/8560 chips,
  128 + please use U-Boot 1.0.0, as the newer silicon will only support Rev2
  129 + and future revisions of 8540/8560.
  130 +
  131 +
116 132 4.4 Reflash U-boot Image using U-boot
117 133  
118 134 => tftp 0 u-boot.bin
119 135  
... ... @@ -121,8 +137,14 @@
121 137 => cp.b 0 fff80000 80000
122 138  
123 139  
124   -5. Screen dump:
  140 +4.5 Reflash U-Boot with a BDI-2000
125 141  
  142 + BDI> erase 0xFFF80000 0x2000 0x40
  143 + BDI> prog 0xfff80000 u-boot.bin.8560ads
  144 + BDI> verify
  145 +
  146 +
  147 +5. Screen dump:
126 148 5.1 MPC8540ADS board
127 149 U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
128 150  
include/asm-ppc/mmu.h
Diff comments   View file @ 0ac6f8b
... ... @@ -440,7 +440,9 @@
440 440 #define LAWAR_SIZE 0x0000003F
441 441  
442 442 #define LAWAR_TRGT_IF_PCI 0x00000000
  443 +#define LAWAR_TRGT_IF_PCI1 0x00000000
443 444 #define LAWAR_TRGT_IF_PCIX 0x00000000
  445 +#define LAWAR_TRGT_IF_PCI2 0x00100000
444 446 #define LAWAR_TRGT_IF_LBC 0x00400000
445 447 #define LAWAR_TRGT_IF_CCSR 0x00800000
446 448 #define LAWAR_TRGT_IF_RIO 0x00c00000
include/asm-ppc/processor.h
Diff comments   View file @ 0ac6f8b
... ... @@ -280,7 +280,6 @@
280 280 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
281 281 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
282 282 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
283   -#define SPRN_SVR 0x11E /* System-On-Chip Version Register */
284 283 #define SPRN_PVR 0x11F /* Processor Version Register */
285 284 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
286 285 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
... ... @@ -297,6 +296,11 @@
297 296 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
298 297 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
299 298 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
  299 +#ifdef CONFIG_BOOKE
  300 +#define SPRN_SVR 0x3FF /* System Version Register */
  301 +#else
  302 +#define SPRN_SVR 0x11E /* System Version Register */
  303 +#endif
300 304 #define SPRN_TBHI 0x3DC /* Time Base High */
301 305 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
302 306 #define SPRN_TBLO 0x3DD /* Time Base Low */
... ... @@ -511,6 +515,7 @@
511 515 #define SPRG3 SPRN_SPRG3
512 516 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
513 517 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
  518 +#define SVR SPRN_SVR /* System Version Register */
514 519 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
515 520 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
516 521 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
517 522  
... ... @@ -731,9 +736,12 @@
731 736 #define PVR_7400 0x000C0000
732 737 #define PVR_7410 0x800C0000
733 738 #define PVR_7450 0x80000000
734   -#define PVR_8540 0x80200010
735   -#define PVR_8560 0x80200010
736 739  
  740 +#define PVR_85xx 0x80200000
  741 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
  742 +#define PVR_85xx_REV2 (PVR_85xx | 0x0020)
  743 +
  744 +
737 745 /*
738 746 * For the 8xx processors, all of them report the same PVR family for
739 747 * the PowerPC core. The various versions of these processors must be
... ... @@ -756,6 +764,33 @@
756 764 #define PVR_8260_HIP4 0x80811014
757 765 #define PVR_8260_HIP7 0x80822011
758 766 #define PVR_8260_HIP7R1 0x80822013
  767 +
  768 +
  769 +/*
  770 + * System Version Register
  771 + */
  772 +
  773 +/* System Version Register (SVR) field extraction */
  774 +
  775 +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
  776 +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */
  777 +
  778 +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
  779 +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
  780 +
  781 +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
  782 +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
  783 +
  784 +
  785 +/*
  786 + * SVR_VER() Version Values
  787 + */
  788 +
  789 +#define SVR_8540 0x8030
  790 +#define SVR_8560 0x8070
  791 +#define SVR_8555 0x8079
  792 +#define SVR_8541 0x807A
  793 +
759 794  
760 795 /* I am just adding a single entry for 8260 boards. I think we may be
761 796 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
... ... @@ -342,7 +342,8 @@
342 342 defined (CONFIG_74xx_7xx) || \
343 343 defined (CONFIG_74x) || \
344 344 defined (CONFIG_75x) || \
345   - defined (CONFIG_74xx)
  345 + defined (CONFIG_74xx) || \
  346 + defined(CONFIG_MPC85xx)
346 347 unsigned char in8(unsigned int);
347 348 void out8(unsigned int, unsigned char);
348 349 unsigned short in16(unsigned int);
... ... @@ -356,6 +357,7 @@
356 357 void ppcDcbf(unsigned long value);
357 358 void ppcDcbi(unsigned long value);
358 359 void ppcSync(void);
  360 +void ppcDcbz(unsigned long value);
359 361 #endif
360 362  
361 363 /* $(CPU)/cpu.c */
include/configs/MPC8540ADS.h
Diff comments   View file @ 0ac6f8b
1 1 /*
  2 + * Copyright 2004 Freescale Semiconductor.
2 3 * (C) Copyright 2002,2003 Motorola,Inc.
3 4 * Xianghua Xiao <X.Xiao@motorola.com>
4 5 *
5 6  
6 7  
7 8  
8 9  
9 10  
10 11  
11 12  
12 13  
13 14  
14 15  
15 16  
16 17  
17 18  
18 19  
19 20  
20 21  
21 22  
22 23  
23 24  
24 25  
25 26  
26 27  
27 28  
28 29  
29 30  
30 31  
31 32  
32 33  
33 34  
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
44 45  
45 46  
46 47  
47 48  
48 49  
49 50  
50 51  
51 52  
... ... @@ -21,209 +22,346 @@
21 22 * MA 02111-1307 USA
22 23 */
23 24  
24   -/* mpc8540ads board configuration file */
25   -/* please refer to doc/README.mpc85xxads for more info */
26   -/* make sure you change the MAC address and other network params first,
27   - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  25 +/*
  26 + * mpc8540ads board configuration file
  27 + *
  28 + * Please refer to doc/README.mpc85xx for more info.
  29 + *
  30 + * Make sure you change the MAC address and other network params first,
  31 + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
28 32 */
29 33  
30 34 #ifndef __CONFIG_H
31 35 #define __CONFIG_H
32 36  
33 37 /* High Level Configuration Options */
34   -#define CONFIG_BOOKE 1 /* BOOKE */
35   -#define CONFIG_E500 1 /* BOOKE e500 family */
36   -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
37   -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1 Chip */
38   -#define CONFIG_MPC8540 1 /* MPC8540 specific */
39   -#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific*/
  38 +#define CONFIG_BOOKE 1 /* BOOKE */
  39 +#define CONFIG_E500 1 /* BOOKE e500 family */
  40 +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
  41 +#define CONFIG_MPC8540 1 /* MPC8540 specific */
  42 +#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
40 43  
41   -#undef CONFIG_PCI /* pci ethernet support */
42   -#define CONFIG_TSEC_ENET /* tsec ethernet support */
  44 +#define CONFIG_PCI
  45 +#define CONFIG_TSEC_ENET /* tsec ethernet support */
43 46 #define CONFIG_ENV_OVERWRITE
44   -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45   -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
  47 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  48 +#define CONFIG_DDR_ECC /* only for ECC DDR module */
  49 +#define CONFIG_DDR_DLL /* possible DLL fix needed */
  50 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
46 51  
47   -#if defined(CONFIG_MPC85xx_REV1)
48   -#define CONFIG_DDR_DLL /* possible DLL fix needed */
49   -#endif
50   -
51   -/* Using Localbus SDRAM to emulate flash before we can program the flash,
52   - * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
  52 +/*
  53 + * Use Localbus SDRAM to emulate flash before we can program the flash.
  54 + * Normally you need a flash-boot image(u-boot.bin).
  55 + * If unsure #undef this.
53 56 */
54 57 #undef CONFIG_RAM_AS_FLASH
55 58  
56   -#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
57   -#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
58   -#else
59   -#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
60   -#endif
  59 +/*
  60 + * sysclk for MPC85xx
  61 + *
  62 + * Two valid values are:
  63 + * 33000000
  64 + * 66000000
  65 + *
  66 + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  67 + * is likely the desired value here. The board, however, can run and
  68 + * defaults to 66Mhz. In any event, this value must match the settings
  69 + * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
  70 + *
  71 + * SW17[8] ------+ SW6
  72 + * SW15[1] ----+ | [0:1]
  73 + * V V V V
  74 + * 33MHz 1 1 1 0
  75 + * 66MHz 0 0 0 1
  76 + */
61 77  
62   -#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
63   -#define CONFIG_DDR_SETTING
  78 +#define CONFIG_SYS_CLK_FREQ 66000000
  79 +
  80 +
  81 +#if !defined(CONFIG_SPD_EEPROM)
  82 +#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
64 83 #endif
65 84  
66   -/* below can be toggled for performance analysis. otherwise use default */
67   -#define CONFIG_L2_CACHE /* toggle L2 cache */
68   -#undef CONFIG_BTB /* toggle branch predition */
69   -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
  85 +/*
  86 + * These can be toggled for performance analysis, otherwise use default.
  87 + */
  88 +#define CONFIG_L2_CACHE /* toggle L2 cache */
  89 +#define CONFIG_BTB /* toggle branch predition */
  90 +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
70 91  
71   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  92 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
72 93  
73   -#undef CFG_DRAM_TEST /* memory test, takes time */
74   -#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
  94 +#undef CFG_DRAM_TEST /* memory test, takes time */
  95 +#define CFG_MEMTEST_START 0x00200000 /* memtest region */
75 96 #define CFG_MEMTEST_END 0x00400000
76 97  
77   -#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
78   -#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
79   -#endif
80 98  
81 99 /*
82 100 * Base addresses -- Note these are effective addresses where the
83 101 * actual resources get mapped (not physical addresses)
84 102 */
85   -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
86   -#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
87   -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
  103 +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  104 +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  105 +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
88 106  
89   -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  107 +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
90 108 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
91   -#define CFG_SDRAM_SIZE 128 /* DDR is now 128MB */
  109 +#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
92 110  
  111 +/*
  112 + * SDRAM on the Local Bus
  113 + */
93 114 #if defined(CONFIG_RAM_AS_FLASH)
94 115 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
95 116 #else
96   -#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
  117 +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
97 118 #endif
98   -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  119 +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
99 120  
100 121 #if defined(CONFIG_RAM_AS_FLASH)
101   -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
  122 +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
102 123 #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
103 124 #else /* Boot from real Flash */
104   -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
105   -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
  125 +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  126 +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
106 127 #endif
107 128  
108   -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
109   -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
110   -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
  129 +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  130 +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  131 +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
111 132 #undef CFG_FLASH_CHECKSUM
112   -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
113   -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
  133 +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  134 +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
114 135  
115   -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  136 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
116 137  
  138 +
117 139 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
118 140 #define CFG_RAMBOOT
119 141 #else
120   -#undef CFG_RAMBOOT
  142 +#undef CFG_RAMBOOT
121 143 #endif
122 144  
123 145 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
124 146  
  147 +#undef CONFIG_CLOCKS_IN_MHZ
  148 +
125 149 #if defined(CONFIG_DDR_SETTING)
126   -#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  150 +#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
127 151 #define CFG_DDR_CS0_CONFIG 0x80000002
128 152 #define CFG_DDR_TIMING_1 0x37344321
129   -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
130   -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
131   -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
132   -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
  153 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  154 +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  155 +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  156 +#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
133 157 #endif
134 158  
135   -#undef CONFIG_CLOCKS_IN_MHZ
136 159  
137   -/* local bus definitions */
138   -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
  160 +/*
  161 + * Local Bus Definitions
  162 + */
  163 +
  164 +/*
  165 + * Base Register 2 and Option Register 2 configure SDRAM.
  166 + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  167 + *
  168 + * For BR2, need:
  169 + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  170 + * port-size = 32-bits = BR2[19:20] = 11
  171 + * no parity checking = BR2[21:22] = 00
  172 + * SDRAM for MSEL = BR2[24:26] = 011
  173 + * Valid = BR[31] = 1
  174 + *
  175 + * 0 4 8 12 16 20 24 28
  176 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  177 + *
  178 + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  179 + * FIXME: the top 17 bits of BR2.
  180 + */
  181 +
  182 +#define CFG_BR2_PRELIM 0xf0001861
  183 +
  184 +/*
  185 + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
  186 + *
  187 + * For OR2, need:
  188 + * 64MB mask for AM, OR2[0:7] = 1111 1100
  189 + * XAM, OR2[17:18] = 11
  190 + * 9 columns OR2[19-21] = 010
  191 + * 13 rows OR2[23-25] = 100
  192 + * EAD set for extra time OR[31] = 1
  193 + *
  194 + * 0 4 8 12 16 20 24 28
  195 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  196 + */
  197 +
139 198 #define CFG_OR2_PRELIM 0xfc006901
140   -#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
141   -#define CFG_LBC_LBCR 0x00000000
142   -#define CFG_LBC_LSRT 0x20000000
143   -#define CFG_LBC_MRTPR 0x20000000
144   -#define CFG_LBC_LSDMR_1 0x2861b723
145   -#define CFG_LBC_LSDMR_2 0x0861b723
146   -#define CFG_LBC_LSDMR_3 0x0861b723
147   -#define CFG_LBC_LSDMR_4 0x1861b723
148   -#define CFG_LBC_LSDMR_5 0x4061b723
149 199  
  200 +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  201 +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
  202 +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  203 +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  204 +
  205 +/*
  206 + * LSDMR masks
  207 + */
  208 +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
  209 +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
  210 +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
  211 +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
  212 +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
  213 +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
  214 +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
  215 +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
  216 +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
  217 +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
  218 +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
  219 +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
  220 +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
  221 +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
  222 +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
  223 +
  224 +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
  225 +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
  226 +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
  227 +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
  228 +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
  229 +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
  230 +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
  231 +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
  232 +
  233 +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
  234 + | CFG_LBC_LSDMR_RFCR5 \
  235 + | CFG_LBC_LSDMR_PRETOACT3 \
  236 + | CFG_LBC_LSDMR_ACTTORW3 \
  237 + | CFG_LBC_LSDMR_BL8 \
  238 + | CFG_LBC_LSDMR_WRC2 \
  239 + | CFG_LBC_LSDMR_CL3 \
  240 + | CFG_LBC_LSDMR_RFEN \
  241 + )
  242 +
  243 +/*
  244 + * SDRAM Controller configuration sequence.
  245 + */
  246 +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
  247 + | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
  248 +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
  249 + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  250 +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
  251 + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  252 +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
  253 + | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
  254 +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
  255 + | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
  256 +
  257 +
150 258 #if defined(CONFIG_RAM_AS_FLASH)
151   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
  259 +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
152 260 #else
153   -#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
  261 +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
154 262 #endif
155 263 #define CFG_OR4_PRELIM 0xffffe1f1
156 264 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
157 265  
158 266 #define CONFIG_L1_INIT_RAM
159   -#define CFG_INIT_RAM_LOCK 1
160   -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
161   -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
  267 +#define CFG_INIT_RAM_LOCK 1
  268 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
  269 +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
162 270  
163   -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  271 +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
164 272 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
165 273 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
166 274  
167   -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
168   -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  275 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  276 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
169 277  
170 278 /* Serial Port */
171 279 #define CONFIG_CONS_INDEX 1
172 280 #undef CONFIG_SERIAL_SOFTWARE_FIFO
173 281 #define CFG_NS16550
174 282 #define CFG_NS16550_SERIAL
175   -#define CFG_NS16550_REG_SIZE 1
  283 +#define CFG_NS16550_REG_SIZE 1
176 284 #define CFG_NS16550_CLK get_bus_freq(0)
177   -#define CONFIG_BAUDRATE 115200
178 285  
179 286 #define CFG_BAUDRATE_TABLE \
180 287 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
181 288  
182   -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
183   -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
  289 +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
  290 +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
184 291  
185 292 /* Use the HUSH parser */
186 293 #define CFG_HUSH_PARSER
187   -#ifdef CFG_HUSH_PARSER
  294 +#ifdef CFG_HUSH_PARSER
188 295 #define CFG_PROMPT_HUSH_PS2 "> "
189 296 #endif
190 297  
191 298 /* I2C */
192   -#define CONFIG_HARD_I2C /* I2C with hardware support*/
193   -#undef CONFIG_SOFT_I2C /* I2C bit-banged */
194   -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  299 +#define CONFIG_HARD_I2C /* I2C with hardware support*/
  300 +#undef CONFIG_SOFT_I2C /* I2C bit-banged */
  301 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
195 302 #define CFG_I2C_SLAVE 0x7F
196   -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  303 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
197 304  
198   -/* General PCI */
199   -#define CFG_PCI_MEM_BASE 0xe0000000
200   -#define CFG_PCI_MEM_PHYS 0xe0000000
201   -#define CFG_PCI_MEM_SIZE 0x10000000
  305 +/* RapidIO MMU */
  306 +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
  307 +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
  308 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
  309 +
  310 +/*
  311 + * General PCI
  312 + * Addresses are mapped 1-1.
  313 + */
  314 +#define CFG_PCI1_MEM_BASE 0x80000000
  315 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  316 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  317 +#define CFG_PCI1_IO_BASE 0xe2000000
  318 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
  319 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  320 +
202 321 #if defined(CONFIG_PCI)
  322 +
203 323 #define CONFIG_NET_MULTI
  324 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  325 +
204 326 #undef CONFIG_EEPRO100
205   -#define CONFIG_TULIP
206   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
207   - #if !defined(CONFIG_PCI_PNP)
208   - #define PCI_ENET0_IOADDR 0xe0000000
209   - #define PCI_ENET0_MEMADDR 0xe0000000
210   - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
211   - #endif
212   -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
213   -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
214   -#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 8 */
215   - #define CFG_PCI_SUBSYS_DEVICEID 0x0003
216   -#else
217   - #define CFG_PCI_SUBSYS_DEVICEID 0x0008
  327 +#undef CONFIG_TULIP
  328 +
  329 +#if !defined(CONFIG_PCI_PNP)
  330 + #define PCI_ENET0_IOADDR 0xe0000000
  331 + #define PCI_ENET0_MEMADDR 0xe0000000
  332 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
218 333 #endif
219   -#elif defined(CONFIG_TSEC_ENET)
220   -#define CONFIG_NET_MULTI 1
221   -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
222   -#define CONFIG_MII 1 /* MII PHY management */
223   -#define CONFIG_PHY_ADDR 8 /* PHY address */
  334 +
  335 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  336 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  337 +
  338 +#endif /* CONFIG_PCI */
  339 +
  340 +
  341 +#if defined(CONFIG_TSEC_ENET)
  342 +
  343 +#ifndef CONFIG_NET_MULTI
  344 +#define CONFIG_NET_MULTI 1
224 345 #endif
225 346  
226   -/* Environment */
  347 +#define CONFIG_MII 1 /* MII PHY management */
  348 +#define CONFIG_MPC85XX_TSEC1 1
  349 +#define CONFIG_MPC85XX_TSEC2 1
  350 +#define CONFIG_MPC85XX_FEC 1
  351 +#define TSEC1_PHY_ADDR 0
  352 +#define TSEC2_PHY_ADDR 1
  353 +#define FEC_PHY_ADDR 3
  354 +#define TSEC1_PHYIDX 0
  355 +#define TSEC2_PHYIDX 0
  356 +#define FEC_PHYIDX 0
  357 +#define CONFIG_ETHPRIME "MOTO ENET0"
  358 +
  359 +#endif /* CONFIG_TSEC_ENET */
  360 +
  361 +
  362 +/*
  363 + * Environment
  364 + */
227 365 #ifndef CFG_RAMBOOT
228 366 #if defined(CONFIG_RAM_AS_FLASH)
229 367 #define CFG_ENV_IS_NOWHERE
230 368  
231 369  
232 370  
233 371  
234 372  
235 373  
236 374  
237 375  
238 376  
239 377  
240 378  
241 379  
242 380  
243 381  
244 382  
245 383  
246 384  
... ... @@ -232,72 +370,83 @@
232 370 #else
233 371 #define CFG_ENV_IS_IN_FLASH 1
234 372 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
235   - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  373 + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
236 374 #endif
237 375 #define CFG_ENV_SIZE 0x2000
238 376 #else
239   -#define CFG_NO_FLASH 1 /* Flash is not usable now */
240   -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  377 +#define CFG_NO_FLASH 1 /* Flash is not usable now */
  378 +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
241 379 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
242 380 #define CFG_ENV_SIZE 0x2000
243 381 #endif
244 382  
245   -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
246   -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
247   -#define CONFIG_BOOTCOMMAND "bootm 0xff300000 0xff700000"
248   -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
  383 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  384 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
249 385  
250   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
251   -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
252   -
253 386 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
254 387 #if defined(CONFIG_PCI)
255   - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \
256   - ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
  388 + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  389 + | CFG_CMD_PING \
  390 + | CFG_CMD_PCI \
  391 + | CFG_CMD_I2C) \
  392 + & \
  393 + ~(CFG_CMD_ENV \
  394 + | CFG_CMD_LOADS))
257 395 #else
258   - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
259   - ~(CFG_CMD_ENV | \
260   - CFG_CMD_LOADS ))
  396 + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  397 + | CFG_CMD_PING \
  398 + | CFG_CMD_I2C) \
  399 + & \
  400 + ~(CFG_CMD_ENV \
  401 + | CFG_CMD_LOADS))
261 402 #endif
262 403 #else
263 404 #if defined(CONFIG_PCI)
264   - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C )
  405 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  406 + | CFG_CMD_PCI \
  407 + | CFG_CMD_PING \
  408 + | CFG_CMD_I2C)
265 409 #else
266   - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
  410 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  411 + | CFG_CMD_PING \
  412 + | CFG_CMD_I2C)
267 413 #endif
268 414 #endif
  415 +
269 416 #include <cmd_confdefs.h>
270 417  
271   -#undef CONFIG_WATCHDOG /* watchdog disabled */
  418 +#undef CONFIG_WATCHDOG /* watchdog disabled */
272 419  
273 420 /*
274 421 * Miscellaneous configurable options
275 422 */
276   -#define CFG_LONGHELP /* undef to save memory */
277   -#define CFG_PROMPT "MPC8540ADS=> " /* Monitor Command Prompt */
  423 +#define CFG_LONGHELP /* undef to save memory */
  424 +#define CFG_LOAD_ADDR 0x2000000 /* default load address */
  425 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  426 +
278 427 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
279   -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  428 + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
280 429 #else
281   -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  430 + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
282 431 #endif
  432 +
283 433 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
284   -#define CFG_MAXARGS 16 /* max number of command args */
285   -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
286   -#define CFG_LOAD_ADDR 0x1000000 /* default load address */
287   -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  434 +#define CFG_MAXARGS 16 /* max number of command args */
  435 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  436 +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
288 437  
289 438 /*
290 439 * For booting Linux, the board info and command line data
291 440 * have to be in the first 8 MB of memory, since this is
292 441 * the maximum mapped by the Linux kernel during initialization.
293 442 */
294   -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  443 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
295 444  
296 445 /* Cache Configuration */
297   -#define CFG_DCACHE_SIZE 32768
  446 +#define CFG_DCACHE_SIZE 32768
298 447 #define CFG_CACHELINE_SIZE 32
299 448 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
300   -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  449 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
301 450 #endif
302 451  
303 452 /*
304 453  
305 454  
306 455  
... ... @@ -306,27 +455,63 @@
306 455 * Boot Flags
307 456 */
308 457 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
309   -#define BOOTFLAG_WARM 0x02 /* Software reboot */
  458 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
310 459  
311 460 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
312 461 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
313 462 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
314 463 #endif
315 464  
316   -/* NOTE: change below for your network setting!!! */
  465 +/*****************************/
  466 +/* Environment Configuration */
  467 +/*****************************/
  468 +
  469 +/* The mac addresses for all ethernet interface */
317 470 #if defined(CONFIG_TSEC_ENET)
318   -#define CONFIG_ETHADDR 00:01:af:07:9b:8a
319   -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
320   -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
  471 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  472 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  473 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
321 474 #endif
322 475  
323   -#define CONFIG_SERVERIP 163.12.64.52
324   -#define CONFIG_IPADDR 10.82.0.105
325   -#define CONFIG_GATEWAYIP 10.82.1.254
326   -#define CONFIG_NETMASK 255.255.254.0
327   -#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
328   -#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
329   -#define CONFIG_BOOTFILE pImage
  476 +#define CONFIG_IPADDR 192.168.1.253
  477 +
  478 +#define CONFIG_HOSTNAME unknown
  479 +#define CONFIG_ROOTPATH /nfsroot
  480 +#define CONFIG_BOOTFILE your.uImage
  481 +
  482 +#define CONFIG_SERVERIP 192.168.1.1
  483 +#define CONFIG_GATEWAYIP 192.168.1.1
  484 +#define CONFIG_NETMASK 255.255.255.0
  485 +
  486 +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  487 +
  488 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  489 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  490 +
  491 +#define CONFIG_BAUDRATE 115200
  492 +
  493 +#define CONFIG_EXTRA_ENV_SETTINGS \
  494 + "netdev=eth0\0" \
  495 + "consoledev=ttyS0\0" \
  496 + "ramdiskaddr=400000\0" \
  497 + "ramdiskfile=your.ramdisk.u-boot\0"
  498 +
  499 +#define CONFIG_NFSBOOTCOMMAND \
  500 + "setenv bootargs root=/dev/nfs rw " \
  501 + "nfsroot=$serverip:$rootpath " \
  502 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  503 + "console=$consoledev,$baudrate $othbootargs;" \
  504 + "tftp $loadaddr $bootfile;" \
  505 + "bootm $loadaddr"
  506 +
  507 +#define CONFIG_RAMBOOTCOMMAND \
  508 + "setenv bootargs root=/dev/ram rw " \
  509 + "console=$consoledev,$baudrate $othbootargs;" \
  510 + "tftp $ramdiskaddr $ramdiskfile;" \
  511 + "tftp $loadaddr $bootfile;" \
  512 + "bootm $loadaddr $ramdiskaddr"
  513 +
  514 +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
330 515  
331 516 #endif /* __CONFIG_H */
include/configs/MPC8560ADS.h
Diff comments   View file @ 0ac6f8b
1 1 /*
  2 + * Copyright 2004 Freescale Semiconductor.
2 3 * (C) Copyright 2002,2003 Motorola,Inc.
3 4 * Xianghua Xiao <X.Xiao@motorola.com>
4 5 *
5 6  
6 7  
7 8  
8 9  
9 10  
10 11  
11 12  
12 13  
13 14  
14 15  
15 16  
16 17  
17 18  
18 19  
19 20  
20 21  
21 22  
22 23  
23 24  
24 25  
25 26  
26 27  
27 28  
28 29  
29 30  
30 31  
31 32  
32 33  
33 34  
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
44 45  
45 46  
46 47  
47 48  
48 49  
49 50  
50 51  
51 52  
52 53  
53 54  
54 55  
55 56  
... ... @@ -21,226 +22,363 @@
21 22 * MA 02111-1307 USA
22 23 */
23 24  
24   -/* mpc8560ads board configuration file */
25   -/* please refer to doc/README.mpc85xx for more info */
26   -/* make sure you change the MAC address and other network params first,
27   - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
  25 +/*
  26 + * mpc8560ads board configuration file
  27 + *
  28 + * Please refer to doc/README.mpc85xx for more info.
  29 + *
  30 + * Make sure you change the MAC address and other network params first,
  31 + * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
28 32 */
29 33  
30 34 #ifndef __CONFIG_H
31 35 #define __CONFIG_H
32 36  
33 37 /* High Level Configuration Options */
34   -#define CONFIG_BOOKE 1 /* BOOKE */
35   -#define CONFIG_E500 1 /* BOOKE e500 family */
36   -#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
37   -#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
38   -#define CONFIG_MPC8560 1 /* MPC8560 specific */
39   -#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
  38 +#define CONFIG_BOOKE 1 /* BOOKE */
  39 +#define CONFIG_E500 1 /* BOOKE e500 family */
  40 +#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
  41 +#define CONFIG_MPC8560 1 /* MPC8560 specific */
  42 +#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
40 43  
41   -#undef CONFIG_PCI /* pci ethernet support */
42   -#define CONFIG_TSEC_ENET /* tsec ethernet support */
43   -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  44 +#define CONFIG_PCI
  45 +#define CONFIG_TSEC_ENET /* tsec ethernet support */
  46 +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
44 47 #define CONFIG_ENV_OVERWRITE
45   -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
46   -#undef CONFIG_DDR_ECC /* only for ECC DDR module */
  48 +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  49 +#define CONFIG_DDR_ECC /* only for ECC DDR module */
  50 +#define CONFIG_DDR_DLL /* possible DLL fix needed */
  51 +#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
47 52  
48   -#if defined(CONFIG_MPC85xx_REV1)
49   -#define CONFIG_DDR_DLL /* possible DLL fix needed */
50   -#endif
51   -
52   -/* Using Localbus SDRAM to emulate flash before we can program the flash,
53   - * normally you need a flash-boot image(u-boot.bin), if so undef this.
  53 +/*
  54 + * Use Localbus SDRAM to emulate flash before we can program the flash.
  55 + * Normally you need a flash-boot image(u-boot.bin).
  56 + * If unsure #undef this.
54 57 */
55 58 #undef CONFIG_RAM_AS_FLASH
56 59  
57   -#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
58   -#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
59   -#else
60   -#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
61   -#endif
  60 +/*
  61 + * sysclk for MPC85xx
  62 + *
  63 + * Two valid values are:
  64 + * 33000000
  65 + * 66000000
  66 + *
  67 + * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  68 + * is likely the desired value here. The board, however, can run and
  69 + * defaults to 66Mhz. In any event, this value must match the settings
  70 + * of SW15[1] and SW17[8], and likely SW6[0:1], the SYSCLK as well.
  71 + *
  72 + * SW17[8] ------+ SW6
  73 + * SW15[1] ----+ | [0:1]
  74 + * V V V V
  75 + * 33MHz 1 1 1 0
  76 + * 66MHz 0 0 0 1
  77 + */
62 78  
63   -#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
64   -#define CONFIG_DDR_SETTING
  79 +#define CONFIG_SYS_CLK_FREQ 66000000
  80 +
  81 +
  82 +#if !defined(CONFIG_SPD_EEPROM)
  83 +#define CONFIG_DDR_SETTING /* manually set up DDR parameters */
65 84 #endif
66 85  
67   -/* below can be toggled for performance analysis. otherwise use default */
68   -#define CONFIG_L2_CACHE /* toggle L2 cache */
69   -#undef CONFIG_BTB /* toggle branch predition */
70   -#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
  86 +/*
  87 + * These can be toggled for performance analysis, otherwise use default.
  88 + */
  89 +#define CONFIG_L2_CACHE /* toggle L2 cache */
  90 +#define CONFIG_BTB /* toggle branch predition */
  91 +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71 92  
72   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  93 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
73 94  
74   -#undef CFG_DRAM_TEST /* memory test, takes time */
75   -#define CFG_MEMTEST_START 0x00200000 /* memtest region */
  95 +#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  96 +
  97 +#undef CFG_DRAM_TEST /* memory test, takes time */
  98 +#define CFG_MEMTEST_START 0x00200000 /* memtest region */
76 99 #define CFG_MEMTEST_END 0x00400000
77 100  
78   -#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
79   - defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
80   - defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
81   -#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
82   -#endif
83 101  
84 102 /*
85 103 * Base addresses -- Note these are effective addresses where the
86 104 * actual resources get mapped (not physical addresses)
87 105 */
88   -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
89   -#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
90   -#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
  106 +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  107 +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  108 +#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
91 109  
92   -#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
  110 +#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
93 111 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
94   -#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
  112 +#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
95 113  
  114 +/*
  115 + * SDRAM on the Local Bus
  116 + */
96 117 #if defined(CONFIG_RAM_AS_FLASH)
97 118 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
98 119 #else
99   -#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
  120 +#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
100 121 #endif
101   -#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  122 +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
102 123  
103 124 #if defined(CONFIG_RAM_AS_FLASH)
104   -#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
105   -#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
  125 +#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
  126 +#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
106 127 #else /* Boot from real Flash */
107   -#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
108   -#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
  128 +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  129 +#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
109 130 #endif
110 131  
111   -#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
112   -#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
113   -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
  132 +#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  133 +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
  134 +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
114 135 #undef CFG_FLASH_CHECKSUM
115   -#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
116   -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  136 +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  137 +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
117 138  
118   -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
  139 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
119 140  
  141 +
120 142 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
121 143 #define CFG_RAMBOOT
122 144 #else
123   -#undef CFG_RAMBOOT
  145 +#undef CFG_RAMBOOT
124 146 #endif
125 147  
126   -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  148 +#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
127 149  
  150 +#undef CONFIG_CLOCKS_IN_MHZ
  151 +
128 152 #if defined(CONFIG_DDR_SETTING)
129 153 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
130 154 #define CFG_DDR_CS0_CONFIG 0x80000002
131 155 #define CFG_DDR_TIMING_1 0x37344321
132   -#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
133   -#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
134   -#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
135   -#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
  156 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  157 +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  158 +#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  159 +#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
136 160 #endif
137 161  
138   -#undef CONFIG_CLOCKS_IN_MHZ
139 162  
140   -/* local bus definitions */
141   -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
  163 +/*
  164 + * Local Bus Definitions
  165 + */
  166 +
  167 +/*
  168 + * Base Register 2 and Option Register 2 configure SDRAM.
  169 + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
  170 + *
  171 + * For BR2, need:
  172 + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  173 + * port-size = 32-bits = BR2[19:20] = 11
  174 + * no parity checking = BR2[21:22] = 00
  175 + * SDRAM for MSEL = BR2[24:26] = 011
  176 + * Valid = BR[31] = 1
  177 + *
  178 + * 0 4 8 12 16 20 24 28
  179 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  180 + *
  181 + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
  182 + * FIXME: the top 17 bits of BR2.
  183 + */
  184 +
  185 +#define CFG_BR2_PRELIM 0xf0001861
  186 +
  187 +/*
  188 + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
  189 + *
  190 + * For OR2, need:
  191 + * 64MB mask for AM, OR2[0:7] = 1111 1100
  192 + * XAM, OR2[17:18] = 11
  193 + * 9 columns OR2[19-21] = 010
  194 + * 13 rows OR2[23-25] = 100
  195 + * EAD set for extra time OR[31] = 1
  196 + *
  197 + * 0 4 8 12 16 20 24 28
  198 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  199 + */
  200 +
142 201 #define CFG_OR2_PRELIM 0xfc006901
143   -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
144   -#define CFG_LBC_LBCR 0x00000000
145   -#define CFG_LBC_LSRT 0x20000000
146   -#define CFG_LBC_MRTPR 0x20000000
147   -#define CFG_LBC_LSDMR_1 0x2861b723
148   -#define CFG_LBC_LSDMR_2 0x0861b723
149   -#define CFG_LBC_LSDMR_3 0x0861b723
150   -#define CFG_LBC_LSDMR_4 0x1861b723
151   -#define CFG_LBC_LSDMR_5 0x4061b723
152 202  
  203 +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  204 +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
  205 +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  206 +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  207 +
  208 +/*
  209 + * LSDMR masks
  210 + */
  211 +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
  212 +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
  213 +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
  214 +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
  215 +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
  216 +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
  217 +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
  218 +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
  219 +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
  220 +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
  221 +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
  222 +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
  223 +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
  224 +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
  225 +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
  226 +
  227 +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
  228 +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
  229 +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
  230 +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
  231 +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
  232 +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
  233 +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
  234 +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
  235 +
  236 +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
  237 + | CFG_LBC_LSDMR_RFCR5 \
  238 + | CFG_LBC_LSDMR_PRETOACT3 \
  239 + | CFG_LBC_LSDMR_ACTTORW3 \
  240 + | CFG_LBC_LSDMR_BL8 \
  241 + | CFG_LBC_LSDMR_WRC2 \
  242 + | CFG_LBC_LSDMR_CL3 \
  243 + | CFG_LBC_LSDMR_RFEN \
  244 + )
  245 +
  246 +/*
  247 + * SDRAM Controller configuration sequence.
  248 + */
  249 +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
  250 + | CFG_LBC_LSDMR_OP_PCHALL) /*0x2861b723*/
  251 +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
  252 + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  253 +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
  254 + | CFG_LBC_LSDMR_OP_ARFRSH) /*0x0861b723*/
  255 +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
  256 + | CFG_LBC_LSDMR_OP_MRW) /*0x1861b723*/
  257 +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
  258 + | CFG_LBC_LSDMR_OP_NORMAL) /*0x4061b723*/
  259 +
  260 +
153 261 #if defined(CONFIG_RAM_AS_FLASH)
154   -#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
  262 +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
155 263 #else
156   -#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
  264 +#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
157 265 #endif
158 266 #define CFG_OR4_PRELIM 0xffffe1f1
159 267 #define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
160 268  
161 269 #define CONFIG_L1_INIT_RAM
162   -#define CFG_INIT_RAM_LOCK 1
163   -#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
164   -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
  270 +#define CFG_INIT_RAM_LOCK 1
  271 +#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
  272 +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
165 273  
166   -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
  274 +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
167 275 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
168 276 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
169 277  
170   -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
171   -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  278 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  279 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
172 280  
173 281 /* Serial Port */
174   -#define CONFIG_CONS_ON_SCC /* define if console on SCC */
175   -#undef CONFIG_CONS_NONE /* define if console on something else */
176   -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  282 +#define CONFIG_CONS_ON_SCC /* define if console on SCC */
  283 +#undef CONFIG_CONS_NONE /* define if console on something else */
  284 +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
177 285  
178   -#define CONFIG_BAUDRATE 115200
  286 +#define CONFIG_BAUDRATE 115200
179 287  
180 288 #define CFG_BAUDRATE_TABLE \
181 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
182 290  
183 291 /* Use the HUSH parser */
184 292 #define CFG_HUSH_PARSER
185   -#ifdef CFG_HUSH_PARSER
  293 +#ifdef CFG_HUSH_PARSER
186 294 #define CFG_PROMPT_HUSH_PS2 "> "
187 295 #endif
188 296  
189 297 /* I2C */
190   -#define CONFIG_HARD_I2C /* I2C with hardware support*/
  298 +#define CONFIG_HARD_I2C /* I2C with hardware support*/
191 299 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
192   -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  300 +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
193 301 #define CFG_I2C_SLAVE 0x7F
194   -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  302 +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
195 303  
196   -#define CFG_PCI_MEM_BASE 0xe0000000
197   -#define CFG_PCI_MEM_PHYS 0xe0000000
198   -#define CFG_PCI_MEM_SIZE 0x10000000
  304 +/* RapidIO MMU */
  305 +#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
  306 +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
  307 +#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
199 308  
200   -#if defined(CONFIG_PCI) /* PCI Ethernet card */
  309 +/*
  310 + * General PCI
  311 + * Addresses are mapped 1-1.
  312 + */
  313 +#define CFG_PCI1_MEM_BASE 0x80000000
  314 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
  315 +#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
  316 +#define CFG_PCI1_IO_BASE 0xe2000000
  317 +#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
  318 +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
  319 +
  320 +#if defined(CONFIG_PCI)
  321 +
201 322 #define CONFIG_NET_MULTI
202   -#define CONFIG_EEPRO100
  323 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  324 +
  325 +#undef CONFIG_EEPRO100
203 326 #undef CONFIG_TULIP
204   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
205   - #if !defined(CONFIG_PCI_PNP)
206   - #define PCI_ENET0_IOADDR 0xe0000000
207   - #define PCI_ENET0_MEMADDR 0xe0000000
208   - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
209   - #endif
210   -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
211   -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
212   -#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
213   - #define CFG_PCI_SUBSYS_DEVICEID 0x0003
214   -#else
215   - #define CFG_PCI_SUBSYS_DEVICEID 0x0009
  327 +
  328 +#if !defined(CONFIG_PCI_PNP)
  329 + #define PCI_ENET0_IOADDR 0xe0000000
  330 + #define PCI_ENET0_MEMADDR 0xe0000000
  331 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
216 332 #endif
217   -#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
218   -#define CONFIG_NET_MULTI 1
219   -#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
220   -#define CONFIG_MII 1 /* MII PHY management */
221   -#define CONFIG_PHY_ADDR 8 /* PHY address */
  333 +
  334 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  335 +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  336 +
  337 +#endif /* CONFIG_PCI */
  338 +
  339 +
  340 +#if defined(CONFIG_TSEC_ENET)
  341 +
  342 +#ifndef CONFIG_NET_MULTI
  343 +#define CONFIG_NET_MULTI 1
  344 +#endif
  345 +
  346 +#define CONFIG_MII 1 /* MII PHY management */
  347 +#define CONFIG_MPC85XX_TSEC1 1
  348 +#define CONFIG_MPC85XX_TSEC2 1
  349 +#undef CONFIG_MPC85XX_FEC
  350 +#define TSEC1_PHY_ADDR 0
  351 +#define TSEC2_PHY_ADDR 1
  352 +#define TSEC1_PHYIDX 0
  353 +#define TSEC2_PHYIDX 0
  354 +#define CONFIG_ETHPRIME "MOTO ENET0"
  355 +
222 356 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
223   -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
224   -#undef CONFIG_ETHER_NONE /* define if ether on something else */
225   -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
226   - #if (CONFIG_ETHER_INDEX == 2)
  357 +
  358 +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  359 +#undef CONFIG_ETHER_NONE /* define if ether on something else */
  360 +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  361 +
  362 +#if (CONFIG_ETHER_INDEX == 2)
227 363 /*
228 364 * - Rx-CLK is CLK13
229 365 * - Tx-CLK is CLK14
230 366 * - Select bus for bd/buffers
231 367 * - Full duplex
232 368 */
233   - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
234   - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
235   - #define CFG_CPMFCR_RAMTYPE 0
236   - #define CFG_FCC_PSMR (FCC_PSMR_FDE)
  369 + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  370 + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  371 + #define CFG_CPMFCR_RAMTYPE 0
  372 + #define CFG_FCC_PSMR (FCC_PSMR_FDE)
237 373 #define FETH2_RST 0x01
238   - #elif (CONFIG_ETHER_INDEX == 3)
  374 +#elif (CONFIG_ETHER_INDEX == 3)
239 375 /* need more definitions here for FE3 */
240 376 #define FETH3_RST 0x80
241   - #endif /* CONFIG_ETHER_INDEX */
  377 +#endif /* CONFIG_ETHER_INDEX */
  378 +
242 379 #define CONFIG_MII /* MII PHY management */
243   -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  380 +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  381 +
244 382 /*
245 383 * GPIO pins used for bit-banged MII communications
246 384 */
247 385  
... ... @@ -256,9 +394,13 @@
256 394 else iop->pdat &= ~0x00200000
257 395  
258 396 #define MIIDELAY udelay(1)
  397 +
259 398 #endif
260 399  
261   -/* Environment */
  400 +
  401 +/*
  402 + * Environment
  403 + */
262 404 #ifndef CFG_RAMBOOT
263 405 #if defined(CONFIG_RAM_AS_FLASH)
264 406 #define CFG_ENV_IS_NOWHERE
265 407  
266 408  
267 409  
268 410  
269 411  
270 412  
271 413  
272 414  
273 415  
274 416  
275 417  
276 418  
277 419  
278 420  
279 421  
280 422  
281 423  
282 424  
... ... @@ -267,83 +409,92 @@
267 409 #else
268 410 #define CFG_ENV_IS_IN_FLASH 1
269 411 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
270   - #define CFG_ENV_SECT_SIZE 0x40000 /* 128K(one sector) for env */
  412 + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
271 413 #endif
272 414 #define CFG_ENV_SIZE 0x2000
273 415 #else
274   -#define CFG_NO_FLASH 1 /* Flash is not usable now */
275   -#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  416 +#define CFG_NO_FLASH 1 /* Flash is not usable now */
  417 +#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
276 418 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
277 419 #define CFG_ENV_SIZE 0x2000
278 420 #endif
279 421  
280   -#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200"
281   -/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
282   -#define CONFIG_BOOTCOMMAND "bootm 0xff400000 0xff700000"
283   -#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
  422 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  423 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
284 424  
285   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
286   -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
287   -
288 425 #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
289 426 #if defined(CONFIG_PCI)
290   - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
291   - CFG_CMD_PING | CFG_CMD_I2C) & \
292   - ~(CFG_CMD_ENV | \
293   - CFG_CMD_LOADS ))
  427 + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  428 + | CFG_CMD_PCI \
  429 + | CFG_CMD_PING \
  430 + | CFG_CMD_I2C) \
  431 + & \
  432 + ~(CFG_CMD_ENV \
  433 + | CFG_CMD_LOADS))
294 434 #elif defined(CONFIG_TSEC_ENET)
295   - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
296   - CFG_CMD_I2C ) & \
297   - ~(CFG_CMD_ENV))
  435 + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  436 + | CFG_CMD_PING \
  437 + | CFG_CMD_I2C) \
  438 + & ~(CFG_CMD_ENV))
298 439 #elif defined(CONFIG_ETHER_ON_FCC)
299   - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
300   - CFG_CMD_PING | CFG_CMD_I2C) & \
301   - ~(CFG_CMD_ENV))
  440 + #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
  441 + | CFG_CMD_MII \
  442 + | CFG_CMD_PING \
  443 + | CFG_CMD_I2C) \
  444 + & ~(CFG_CMD_ENV))
302 445 #endif
303 446 #else
304 447 #if defined(CONFIG_PCI)
305   - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
306   - CFG_CMD_PING | CFG_CMD_I2C)
  448 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  449 + | CFG_CMD_PCI \
  450 + | CFG_CMD_PING \
  451 + | CFG_CMD_I2C)
307 452 #elif defined(CONFIG_TSEC_ENET)
308   - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
309   - CFG_CMD_I2C)
  453 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  454 + | CFG_CMD_PING \
  455 + | CFG_CMD_I2C)
310 456 #elif defined(CONFIG_ETHER_ON_FCC)
311   - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
312   - CFG_CMD_PING | CFG_CMD_I2C)
  457 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  458 + | CFG_CMD_MII \
  459 + | CFG_CMD_PING \
  460 + | CFG_CMD_I2C)
313 461 #endif
314 462 #endif
  463 +
315 464 #include <cmd_confdefs.h>
316 465  
317   -#undef CONFIG_WATCHDOG /* watchdog disabled */
  466 +#undef CONFIG_WATCHDOG /* watchdog disabled */
318 467  
319 468 /*
320 469 * Miscellaneous configurable options
321 470 */
322   -#define CFG_LONGHELP /* undef to save memory */
323   -#define CFG_PROMPT "MPC8560ADS=> " /* Monitor Command Prompt */
  471 +#define CFG_LONGHELP /* undef to save memory */
  472 +#define CFG_LOAD_ADDR 0x1000000 /* default load address */
  473 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  474 +
324 475 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
325   -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  476 + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
326 477 #else
327   -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  478 + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
328 479 #endif
  480 +
329 481 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
330   -#define CFG_MAXARGS 16 /* max number of command args */
331   -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
332   -#define CFG_LOAD_ADDR 0x1000000 /* default load address */
333   -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  482 +#define CFG_MAXARGS 16 /* max number of command args */
  483 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  484 +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
334 485  
335 486 /*
336 487 * For booting Linux, the board info and command line data
337 488 * have to be in the first 8 MB of memory, since this is
338 489 * the maximum mapped by the Linux kernel during initialization.
339 490 */
340   -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  491 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
341 492  
342 493 /* Cache Configuration */
343 494 #define CFG_DCACHE_SIZE 32768
344 495 #define CFG_CACHELINE_SIZE 32
345 496 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
346   -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  497 +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
347 498 #endif
348 499  
349 500 /*
350 501  
351 502  
352 503  
... ... @@ -352,27 +503,59 @@
352 503 * Boot Flags
353 504 */
354 505 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
355   -#define BOOTFLAG_WARM 0x02 /* Software reboot */
  506 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
356 507  
357 508 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
358 509 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
359 510 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
360 511 #endif
361 512  
362   -/*Note: change below for your network setting!!! */
  513 +/* The mac addresses for all ethernet interface */
363 514 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
364   -#define CONFIG_ETHADDR 00:01:af:07:9b:8a
365   -#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
366   -#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
  515 +#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  516 +#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  517 +#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
367 518 #endif
368 519  
369   -#define CONFIG_SERVERIP 163.12.64.52
370   -#define CONFIG_IPADDR 10.82.0.105
371   -#define CONFIG_GATEWAYIP 10.82.1.254
372   -#define CONFIG_NETMASK 255.255.254.0
373   -#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
374   -#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
375   -#define CONFIG_BOOTFILE pImage
  520 +#define CONFIG_IPADDR 192.168.1.253
  521 +
  522 +#define CONFIG_HOSTNAME unknown
  523 +#define CONFIG_ROOTPATH /nfsroot
  524 +#define CONFIG_BOOTFILE your.uImage
  525 +
  526 +#define CONFIG_SERVERIP 192.168.1.1
  527 +#define CONFIG_GATEWAYIP 192.168.1.1
  528 +#define CONFIG_NETMASK 255.255.255.0
  529 +
  530 +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  531 +
  532 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  533 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  534 +
  535 +#define CONFIG_BAUDRATE 115200
  536 +
  537 +#define CONFIG_EXTRA_ENV_SETTINGS \
  538 + "netdev=eth0\0" \
  539 + "consoledev=ttyS0\0" \
  540 + "ramdiskaddr=400000\0" \
  541 + "ramdiskfile=your.ramdisk.u-boot\0"
  542 +
  543 +#define CONFIG_NFSBOOTCOMMAND \
  544 + "setenv bootargs root=/dev/nfs rw " \
  545 + "nfsroot=$serverip:$rootpath " \
  546 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  547 + "console=$consoledev,$baudrate $othbootargs;" \
  548 + "tftp $loadaddr $bootfile;" \
  549 + "bootm $loadaddr"
  550 +
  551 +#define CONFIG_RAMBOOTCOMMAND \
  552 + "setenv bootargs root=/dev/ram rw " \
  553 + "console=$consoledev,$baudrate $othbootargs;" \
  554 + "tftp $ramdiskaddr $ramdiskfile;" \
  555 + "tftp $loadaddr $bootfile;" \
  556 + "bootm $loadaddr $ramdiskaddr"
  557 +
  558 +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
376 559  
377 560 #endif /* __CONFIG_H */
1 1 /*
  2 + * Copyright 2004 Freescale Semiconductor.
2 3 * Copyright(c) 2003 Motorola Inc.
3 4 * Xianghua Xiao (x.xiao@motorola.com)
4 5 */
5 6  
6 7  
7 8  
... ... @@ -6,28 +7,23 @@
6 7 #ifndef __MPC85xx_H__
7 8 #define __MPC85xx_H__
8 9  
9   -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
  10 +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
10 11  
11 12 #if defined(CONFIG_E500)
12 13 #include <e500.h>
13 14 #endif
14 15  
15   -#if defined(CONFIG_DDR_ECC)
16   -void dma_init(void);
17   -uint dma_check(void);
18   -int dma_xfer(void *dest, uint count, void *src);
19   -#endif
20   -/*-----------------------------------------------------------------------
21   - * SCCR - System Clock Control Register 9-8
  16 +/*
  17 + * SCCR - System Clock Control Register, 9-8
22 18 */
23   -#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
24   -#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
  19 +#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
  20 +#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
25 21 #define SCCR_DFBRG_SHIFT 0
26 22  
27   -#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
28   -#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
29   -#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
30   -#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
  23 +#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
  24 +#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
  25 +#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
  26 +#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
31 27  
32 28 #endif /* __MPC85xx_H__ */
... ... @@ -775,7 +775,8 @@
775 775 #endif
776 776  
777 777 #if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
778   - defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX)
  778 + defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8555CDS) || \
  779 + defined(CONFIG_MPC8560ADS) || defined(CONFIG_440_GX)
779 780 /* handle the 2nd ethernet address */
780 781  
781 782 s = getenv ("eth1addr");
... ... @@ -786,8 +787,9 @@
786 787 s = (*e) ? e + 1 : e;
787 788 }
788 789 #endif
789   -#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS) || \
790   - defined(CONFIG_440_GX)
  790 +#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || \
  791 + defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8560ADS) || \
  792 + defined(CONFIG_440_GX)
791 793 /* handle the 3rd ethernet address */
792 794  
793 795 s = getenv ("eth2addr");
... ... @@ -51,7 +51,7 @@
51 51 extern int rtl8169_initialize(bd_t*);
52 52 extern int scc_initialize(bd_t*);
53 53 extern int skge_initialize(bd_t*);
54   -extern int tsec_initialize(bd_t*);
  54 +extern int tsec_initialize(bd_t*, int);
55 55  
56 56 static struct eth_device *eth_devices, *eth_current;
57 57  
... ... @@ -147,8 +147,14 @@
147 147 #if defined(CONFIG_SK98)
148 148 skge_initialize(bis);
149 149 #endif
150   -#ifdef CONFIG_TSEC_ENET
151   - tsec_initialize(bis);
  150 +#if defined(CONFIG_MPC85XX_TSEC1)
  151 + tsec_initialize(bis, 0);
  152 +#endif
  153 +#if defined(CONFIG_MPC85XX_TSEC2)
  154 + tsec_initialize(bis, 1);
  155 +#endif
  156 +#if defined(CONFIG_MPC85XX_FEC)
  157 + tsec_initialize(bis, 2);
152 158 #endif
153 159 #if defined(CONFIG_AU1X00)
154 160 au1x00_enet_initialize(bis);