Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 0ace4d9d8f33c54611af9f9b786696305aef97c3

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 62d636aa2a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: mpc8xx: remove stxxtc board support 

This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 13 changed files with 2 additions and 1383 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ 0ace4d9
... ... @@ -74,9 +74,6 @@
74 74 config TARGET_UC100
75 75 bool "Support uc100"
76 76  
77   -config TARGET_STXXTC
78   - bool "Support stxxtc"
79   -
80 77 config TARGET_FPS850L
81 78 bool "Support FPS850L"
82 79  
... ... @@ -153,7 +150,6 @@
153 150 source "board/r360mpi/Kconfig"
154 151 source "board/sixnet/Kconfig"
155 152 source "board/spd8xx/Kconfig"
156   -source "board/stx/stxxtc/Kconfig"
157 153 source "board/svm_sc8xx/Kconfig"
158 154 source "board/tqc/tqm8xx/Kconfig"
159 155  
board/stx/stxxtc/Kconfig
View file @ 0ace4d9
1   -if TARGET_STXXTC
2   -
3   -config SYS_BOARD
4   - string
5   - default "stxxtc"
6   -
7   -config SYS_VENDOR
8   - string
9   - default "stx"
10   -
11   -config SYS_CONFIG_NAME
12   - string
13   - default "stxxtc"
14   -
15   -endif
board/stx/stxxtc/MAINTAINERS
View file @ 0ace4d9
1   -STXXTC BOARD
2   -M: Dan Malek <dan@embeddedalley.com>
3   -S: Orphan (since 2014-06)
4   -F: board/stx/stxxtc/
5   -F: include/configs/stxxtc.h
6   -F: configs/stxxtc_defconfig
board/stx/stxxtc/Makefile
View file @ 0ace4d9
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = stxxtc.o
board/stx/stxxtc/README.stxxtc
View file @ 0ace4d9
1   -
2   -
3   -First, some build notes on the Silicon Turnkey eXpress XTc.
4   -
5   -This board has both 87x/88x procesor options at various
6   -frequencies. The configuration file has some macros for setting
7   -the clock speed, not all have been tested. They all have
8   -a 10MHz input clock. Please do not check in a configuration
9   -file that selects a high speed not available on all processors.
10   -We chose the 66MHz core and bus speed, which should be OK on
11   -all boards. If you have a processor, lucky you! :-)
12   -Just build a new configuration with that speed, check
13   -the macro configuration to ensure it's correct. If the
14   -macro is updated, please check that in, but keep default
15   -processor speed.
16   -
17   -The board is likely to have more than 1Mbyte of NOR boot flash.
18   -It was also configured with a high boot vector (Dan's fault)
19   -so the standard 8xx mapping doesn't work well. We had to move
20   -the addresses around a little bit so one copy would work. The
21   -flash got fragmented, and we are working on a better solution.
22   -There is an "xtc.cfg" floating around for the BDI2000, use
23   -that for programming a new version of U-Boot. You can probably
24   -find it on the Silicon Turnkey eXpress (www.silicontkx.com),
25   -Embedded Alley Solutions (embeddedalley.com), or Denx (denx.de)
26   -servers.
27   -
28   -The board will also have various SDRAM sizes, but the code
29   -should automatically determine the amount of memory.
30   -
31   -There are a couple of different board versions, visually
32   -they use different BGA or surface mount memory parts. However,
33   -they are logically the same board.
34   -
35   -Now, some operational notes.
36   -
37   -The board has the option of sporting two FEC Ethernet ports.
38   -The second port isn't configured to be automatically available
39   -because it would cause U-Boot to generate a board data structure
40   -(the bd_t) with multiple MAC addresses and be incompatible with
41   -standard 8xx kernel builds. You can use/test the second FEC
42   -in U-Boot by assigning an 'eth1addr' and selecting the second
43   -FEC as the port to use.
44   -
45   -Since this is just a development board and not a product, STx
46   -does not assign unique MAC addresses. We just pilfer the
47   -"default" ones used by Wolfgang on some other boards. Please
48   -ensure you assign unique MAC addresses when using these boards.
49   -
50   -The serial port baud rate is 38400, because that's the way
51   -I like it :-)
52   -
53   -Thanks to Pantelis for lots of the work on this board port.
54   -
55   -Have Fun!
56   -
57   - -- Dan
58   -
59   -15 August 2005
board/stx/stxxtc/stxxtc.c
View file @ 0ace4d9
1   -/*
2   - * (C) Copyright 2000-2004
3   - * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5   - * (C) Copyright 2005
6   - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - * U-Boot port on STx XTc board
13   - * Mostly copied from Netta
14   - */
15   -
16   -#include <common.h>
17   -#include <miiphy.h>
18   -
19   -#include "mpc8xx.h"
20   -
21   -#ifdef CONFIG_HW_WATCHDOG
22   -#include <watchdog.h>
23   -#endif
24   -
25   -/****************************************************************/
26   -
27   -/* some sane bit macros */
28   -#define _BD(_b) (1U << (31-(_b)))
29   -#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
30   -
31   -#define _BW(_b) (1U << (15-(_b)))
32   -#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
33   -
34   -#define _BB(_b) (1U << (7-(_b)))
35   -#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
36   -
37   -#define _B(_b) _BD(_b)
38   -#define _BR(_l, _h) _BDR(_l, _h)
39   -
40   -/****************************************************************/
41   -
42   -/*
43   - * Check Board Identity:
44   - *
45   - * Return 1 always.
46   - */
47   -
48   -int checkboard(void)
49   -{
50   - printf ("Silicon Turnkey eXpress XTc\n");
51   - return (0);
52   -}
53   -
54   -/****************************************************************/
55   -
56   -#define _NOT_USED_ 0xFFFFFFFF
57   -
58   -/****************************************************************/
59   -
60   -#define CS_0000 0x00000000
61   -#define CS_0001 0x10000000
62   -#define CS_0010 0x20000000
63   -#define CS_0011 0x30000000
64   -#define CS_0100 0x40000000
65   -#define CS_0101 0x50000000
66   -#define CS_0110 0x60000000
67   -#define CS_0111 0x70000000
68   -#define CS_1000 0x80000000
69   -#define CS_1001 0x90000000
70   -#define CS_1010 0xA0000000
71   -#define CS_1011 0xB0000000
72   -#define CS_1100 0xC0000000
73   -#define CS_1101 0xD0000000
74   -#define CS_1110 0xE0000000
75   -#define CS_1111 0xF0000000
76   -
77   -#define BS_0000 0x00000000
78   -#define BS_0001 0x01000000
79   -#define BS_0010 0x02000000
80   -#define BS_0011 0x03000000
81   -#define BS_0100 0x04000000
82   -#define BS_0101 0x05000000
83   -#define BS_0110 0x06000000
84   -#define BS_0111 0x07000000
85   -#define BS_1000 0x08000000
86   -#define BS_1001 0x09000000
87   -#define BS_1010 0x0A000000
88   -#define BS_1011 0x0B000000
89   -#define BS_1100 0x0C000000
90   -#define BS_1101 0x0D000000
91   -#define BS_1110 0x0E000000
92   -#define BS_1111 0x0F000000
93   -
94   -#define GPL0_AAAA 0x00000000
95   -#define GPL0_AAA0 0x00200000
96   -#define GPL0_AAA1 0x00300000
97   -#define GPL0_000A 0x00800000
98   -#define GPL0_0000 0x00A00000
99   -#define GPL0_0001 0x00B00000
100   -#define GPL0_111A 0x00C00000
101   -#define GPL0_1110 0x00E00000
102   -#define GPL0_1111 0x00F00000
103   -
104   -#define GPL1_0000 0x00000000
105   -#define GPL1_0001 0x00040000
106   -#define GPL1_1110 0x00080000
107   -#define GPL1_1111 0x000C0000
108   -
109   -#define GPL2_0000 0x00000000
110   -#define GPL2_0001 0x00010000
111   -#define GPL2_1110 0x00020000
112   -#define GPL2_1111 0x00030000
113   -
114   -#define GPL3_0000 0x00000000
115   -#define GPL3_0001 0x00004000
116   -#define GPL3_1110 0x00008000
117   -#define GPL3_1111 0x0000C000
118   -
119   -#define GPL4_0000 0x00000000
120   -#define GPL4_0001 0x00001000
121   -#define GPL4_1110 0x00002000
122   -#define GPL4_1111 0x00003000
123   -
124   -#define GPL5_0000 0x00000000
125   -#define GPL5_0001 0x00000400
126   -#define GPL5_1110 0x00000800
127   -#define GPL5_1111 0x00000C00
128   -#define LOOP 0x00000080
129   -
130   -#define EXEN 0x00000040
131   -
132   -#define AMX_COL 0x00000000
133   -#define AMX_ROW 0x00000020
134   -#define AMX_MAR 0x00000030
135   -
136   -#define NA 0x00000008
137   -
138   -#define UTA 0x00000004
139   -
140   -#define TODT 0x00000002
141   -
142   -#define LAST 0x00000001
143   -
144   -#define A10_AAAA GPL0_AAAA
145   -#define A10_AAA0 GPL0_AAA0
146   -#define A10_AAA1 GPL0_AAA1
147   -#define A10_000A GPL0_000A
148   -#define A10_0000 GPL0_0000
149   -#define A10_0001 GPL0_0001
150   -#define A10_111A GPL0_111A
151   -#define A10_1110 GPL0_1110
152   -#define A10_1111 GPL0_1111
153   -
154   -#define RAS_0000 GPL1_0000
155   -#define RAS_0001 GPL1_0001
156   -#define RAS_1110 GPL1_1110
157   -#define RAS_1111 GPL1_1111
158   -
159   -#define CAS_0000 GPL2_0000
160   -#define CAS_0001 GPL2_0001
161   -#define CAS_1110 GPL2_1110
162   -#define CAS_1111 GPL2_1111
163   -
164   -#define WE_0000 GPL3_0000
165   -#define WE_0001 GPL3_0001
166   -#define WE_1110 GPL3_1110
167   -#define WE_1111 GPL3_1111
168   -
169   -/* #define CAS_LATENCY 3 */
170   -#define CAS_LATENCY 2
171   -
172   -const uint sdram_table[0x40] = {
173   -
174   -#if CAS_LATENCY == 3
175   - /* RSS */
176   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
177   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
178   - CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
179   - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
180   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
181   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
182   - _NOT_USED_, _NOT_USED_,
183   -
184   - /* RBS */
185   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
186   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
187   - CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
188   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
189   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
190   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
191   - CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
192   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
193   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
194   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
195   -
196   - /* WSS */
197   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
198   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
199   - CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
200   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
201   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
202   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
203   -
204   - /* WBS */
205   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
206   - CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
207   - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
208   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
209   - CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
210   - CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
211   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
212   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
213   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
214   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
215   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
216   -#endif
217   -
218   -#if CAS_LATENCY == 2
219   - /* RSS */
220   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
221   - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
222   - CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
223   - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
224   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
225   - _NOT_USED_,
226   - _NOT_USED_, _NOT_USED_,
227   -
228   - /* RBS */
229   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
230   - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
231   - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
232   - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
233   - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
234   - CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
235   - CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
236   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
237   - _NOT_USED_,
238   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
239   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
240   -
241   - /* WSS */
242   - CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
243   - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
244   - CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
245   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
246   - _NOT_USED_,
247   - _NOT_USED_, _NOT_USED_,
248   - _NOT_USED_,
249   -
250   - /* WBS */
251   - CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
252   - CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
253   - CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
254   - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
255   - CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
256   - CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
257   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
258   - _NOT_USED_,
259   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
260   - _NOT_USED_, _NOT_USED_, _NOT_USED_,
261   - _NOT_USED_, _NOT_USED_,
262   -
263   -#endif
264   -
265   - /* UPT */
266   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
267   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
268   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
269   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
270   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
271   - CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
272   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
273   - _NOT_USED_, _NOT_USED_,
274   -
275   - /* EXC */
276   - CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
277   - _NOT_USED_,
278   -
279   - /* REG */
280   - CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
281   - CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
282   -};
283   -
284   -static const uint nandcs_table[0x40] = {
285   - /* RSS */
286   - CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
287   - CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
288   - CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
289   - CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
290   - CS_0000 | GPL4_0000 | GPL5_1111,
291   - CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
292   - CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
293   - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
294   -
295   - /* RBS */
296   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
297   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
298   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
299   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
300   -
301   - /* WSS */
302   - CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
303   - CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
304   - CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
305   - CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
306   - CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
307   - CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
308   - CS_0000 | GPL4_1111 | GPL5_1111,
309   - CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
310   -
311   - /* WBS */
312   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
313   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
316   -
317   - /* UPT */
318   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
319   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
321   -
322   - /* EXC */
323   - CS_0001 | LAST,
324   - _NOT_USED_,
325   -
326   - /* REG */
327   - CS_1110 ,
328   - CS_0001 | LAST,
329   -};
330   -
331   -/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
332   -/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
333   -#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
334   -
335   -/* 9 */
336   -#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
337   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
338   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
339   -
340   -void check_ram(unsigned int addr, unsigned int size)
341   -{
342   - unsigned int i, j, v, vv;
343   - volatile unsigned int *p;
344   - unsigned int pv;
345   -
346   - p = (unsigned int *)addr;
347   - pv = (unsigned int)p;
348   - for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
349   - *p++ = pv;
350   -
351   - p = (unsigned int *)addr;
352   - for (i = 0; i < size / sizeof(unsigned int); i++) {
353   - v = (unsigned int)p;
354   - vv = *p;
355   - if (vv != v) {
356   - printf("%p: read %08x instead of %08x\n", p, vv, v);
357   - hang();
358   - }
359   - p++;
360   - }
361   -
362   - for (j = 0; j < 5; j++) {
363   - switch (j) {
364   - case 0: v = 0x00000000; break;
365   - case 1: v = 0xffffffff; break;
366   - case 2: v = 0x55555555; break;
367   - case 3: v = 0xaaaaaaaa; break;
368   - default:v = 0xdeadbeef; break;
369   - }
370   - p = (unsigned int *)addr;
371   - for (i = 0; i < size / sizeof(unsigned int); i++) {
372   - *p = v;
373   - vv = *p;
374   - if (vv != v) {
375   - printf("%p: read %08x instead of %08x\n", p, vv, v);
376   - hang();
377   - }
378   - *p = ~v;
379   - p++;
380   - }
381   - }
382   -}
383   -
384   -#define DO_LOOP do { for (;;) asm volatile ("nop" : : : "memory"); } while(0)
385   -
386   -phys_size_t initdram(int board_type)
387   -{
388   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
389   - volatile memctl8xx_t *memctl = &immap->im_memctl;
390   - long int size;
391   - u32 d1, d2;
392   -
393   - upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
394   -
395   - /*
396   - * Preliminary prescaler for refresh
397   - */
398   - memctl->memc_mptpr = MPTPR_PTP_DIV8;
399   -
400   - memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
401   -
402   - /*
403   - * Map controller bank 3 to the SDRAM bank at preliminary address.
404   - */
405   - memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
406   - memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
407   -
408   - memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
409   -
410   - udelay(200);
411   -
412   - /* perform SDRAM initialisation sequence */
413   - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
414   - udelay(1);
415   -
416   - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
417   - udelay(1);
418   -
419   - memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS4 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
420   - udelay(1);
421   -
422   - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
423   -
424   - udelay(10000);
425   -
426   -
427   - d1 = 0xAA55AA55;
428   - *(volatile u32 *)0 = d1;
429   - d2 = *(volatile u32 *)0;
430   - if (d1 != d2) {
431   - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
432   - DO_LOOP;
433   - }
434   -
435   - d1 = 0x55AA55AA;
436   - *(volatile u32 *)0 = d1;
437   - d2 = *(volatile u32 *)0;
438   - if (d1 != d2) {
439   - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
440   - DO_LOOP;
441   - }
442   -
443   - d1 = 0x12345678;
444   - *(volatile u32 *)0 = d1;
445   - d2 = *(volatile u32 *)0;
446   - if (d1 != d2) {
447   - printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
448   - DO_LOOP;
449   - }
450   -
451   - size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
452   -
453   - return size;
454   -}
455   -
456   -/* ------------------------------------------------------------------------- */
457   -
458   -void reset_phys(void)
459   -{
460   - int phyno;
461   - unsigned short v;
462   -
463   - udelay(10000);
464   - /* reset the damn phys */
465   - mii_init();
466   -
467   - for (phyno = 0; phyno < 32; ++phyno) {
468   - miiphy_read("FEC", phyno, MII_PHYSID1, &v);
469   - if (v == 0xFFFF)
470   - continue;
471   - miiphy_write("FEC", phyno, MII_BMCR, BMCR_PDOWN);
472   - udelay(10000);
473   - miiphy_write("FEC", phyno, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
474   - udelay(10000);
475   - }
476   -}
477   -
478   -/* ------------------------------------------------------------------------- */
479   -
480   -/* GP = general purpose, SP = special purpose (on chip peripheral) */
481   -
482   -/* bits that can have a special purpose or can be configured as inputs/outputs */
483   -#define PA_GP_INMASK _BW(6)
484   -#define PA_GP_OUTMASK (_BW(7))
485   -#define PA_SP_MASK 0
486   -#define PA_ODR_VAL 0
487   -#define PA_GP_OUTVAL (_BW(7))
488   -#define PA_SP_DIRVAL 0
489   -
490   -#define PB_GP_INMASK 0
491   -#define PB_GP_OUTMASK (_B(23))
492   -#define PB_SP_MASK 0
493   -#define PB_ODR_VAL 0
494   -#define PB_GP_OUTVAL (_B(23))
495   -#define PB_SP_DIRVAL 0
496   -
497   -#define PC_GP_INMASK 0
498   -#define PC_GP_OUTMASK (_BW(15))
499   -
500   -#define PC_SP_MASK 0
501   -#define PC_SOVAL 0
502   -#define PC_INTVAL 0
503   -#define PC_GP_OUTVAL 0
504   -#define PC_SP_DIRVAL 0
505   -
506   -#define PE_GP_INMASK 0
507   -#define PE_GP_OUTMASK 0
508   -#define PE_GP_OUTVAL 0
509   -
510   -#define PE_SP_MASK 0
511   -#define PE_ODR_VAL 0
512   -#define PE_SP_DIRVAL 0
513   -
514   -int board_early_init_f(void)
515   -{
516   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
517   - volatile iop8xx_t *ioport = &immap->im_ioport;
518   - volatile cpm8xx_t *cpm = &immap->im_cpm;
519   - volatile memctl8xx_t *memctl = &immap->im_memctl;
520   -
521   - (void)ioport;
522   - (void)cpm;
523   -#if 1
524   - /* NAND chip select */
525   - upmconfig(UPMB, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
526   - memctl->memc_or2 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
527   - memctl->memc_br2 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMB);
528   - memctl->memc_mbmr = 0; /* all clear */
529   -#endif
530   -
531   - memctl->memc_br5 &= ~BR_V;
532   - memctl->memc_br6 &= ~BR_V;
533   - memctl->memc_br7 &= ~BR_V;
534   -
535   -#if 1
536   - ioport->iop_padat = PA_GP_OUTVAL;
537   - ioport->iop_paodr = PA_ODR_VAL;
538   - ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
539   - ioport->iop_papar = PA_SP_MASK;
540   -
541   - cpm->cp_pbdat = PB_GP_OUTVAL;
542   - cpm->cp_pbodr = PB_ODR_VAL;
543   - cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
544   - cpm->cp_pbpar = PB_SP_MASK;
545   -
546   - ioport->iop_pcdat = PC_GP_OUTVAL;
547   - ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
548   - ioport->iop_pcso = PC_SOVAL;
549   - ioport->iop_pcint = PC_INTVAL;
550   - ioport->iop_pcpar = PC_SP_MASK;
551   -
552   - cpm->cp_pedat = PE_GP_OUTVAL;
553   - cpm->cp_peodr = PE_ODR_VAL;
554   - cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
555   - cpm->cp_pepar = PE_SP_MASK;
556   -#endif
557   -
558   - return 0;
559   -}
560   -
561   -#ifdef CONFIG_HW_WATCHDOG
562   -
563   -void hw_watchdog_reset(void)
564   -{
565   - /* XXX add here the really funky stuff */
566   -}
567   -
568   -#endif
569   -
570   -#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
571   -int overwrite_console(void)
572   -{
573   - /* printf("overwrite_console called\n"); */
574   - return 0;
575   -}
576   -#endif
577   -
578   -extern int drv_phone_init(void);
579   -extern int drv_phone_use_me(void);
580   -extern int drv_phone_is_idle(void);
581   -
582   -int misc_init_r(void)
583   -{
584   - return 0;
585   -}
586   -
587   -int last_stage_init(void)
588   -{
589   - reset_phys();
590   -
591   - return 0;
592   -}
board/stx/stxxtc/u-boot.lds
View file @ 0ace4d9
1   -/*
2   - * (C) Copyright 2000-2010
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -
10   -SECTIONS
11   -{
12   - /* Read-only sections, merged into text segment: */
13   - . = + SIZEOF_HEADERS;
14   - .text :
15   - {
16   - arch/powerpc/cpu/mpc8xx/start.o (.text*)
17   - arch/powerpc/cpu/mpc8xx/traps.o (.text*)
18   -
19   - *(.text*)
20   - }
21   - _etext = .;
22   - PROVIDE (etext = .);
23   - .rodata :
24   - {
25   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
26   - }
27   -
28   - /* Read-write section, merged into data segment: */
29   - . = (. + 0x00FF) & 0xFFFFFF00;
30   - _erotext = .;
31   - PROVIDE (erotext = .);
32   - .reloc :
33   - {
34   - _GOT2_TABLE_ = .;
35   - KEEP(*(.got2))
36   - KEEP(*(.got))
37   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
38   - _FIXUP_TABLE_ = .;
39   - KEEP(*(.fixup))
40   - }
41   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
42   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
43   -
44   - .data :
45   - {
46   - *(.data*)
47   - *(.sdata*)
48   - }
49   - _edata = .;
50   - PROVIDE (edata = .);
51   -
52   - . = .;
53   -
54   - . = ALIGN(4);
55   - .u_boot_list : {
56   - KEEP(*(SORT(.u_boot_list*)));
57   - }
58   -
59   -
60   - . = .;
61   - __start___ex_table = .;
62   - __ex_table : { *(__ex_table) }
63   - __stop___ex_table = .;
64   -
65   - . = ALIGN(256);
66   - __init_begin = .;
67   - .text.init : { *(.text.init) }
68   - .data.init : { *(.data.init) }
69   - . = ALIGN(256);
70   - __init_end = .;
71   -
72   - __bss_start = .;
73   - .bss (NOLOAD) :
74   - {
75   - *(.bss*)
76   - *(.sbss*)
77   - *(COMMON)
78   - . = ALIGN(4);
79   - }
80   - __bss_end = . ;
81   - PROVIDE (end = .);
82   -}
board/stx/stxxtc/u-boot.lds.debug
View file @ 0ace4d9
1   -/*
2   - * (C) Copyright 2000-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - /* Read-only sections, merged into text segment: */
14   - . = + SIZEOF_HEADERS;
15   - .interp : { *(.interp) }
16   - .hash : { *(.hash) }
17   - .dynsym : { *(.dynsym) }
18   - .dynstr : { *(.dynstr) }
19   - .rel.text : { *(.rel.text) }
20   - .rela.text : { *(.rela.text) }
21   - .rel.data : { *(.rel.data) }
22   - .rela.data : { *(.rela.data) }
23   - .rel.rodata : { *(.rel.rodata) }
24   - .rela.rodata : { *(.rela.rodata) }
25   - .rel.got : { *(.rel.got) }
26   - .rela.got : { *(.rela.got) }
27   - .rel.ctors : { *(.rel.ctors) }
28   - .rela.ctors : { *(.rela.ctors) }
29   - .rel.dtors : { *(.rel.dtors) }
30   - .rela.dtors : { *(.rela.dtors) }
31   - .rel.bss : { *(.rel.bss) }
32   - .rela.bss : { *(.rela.bss) }
33   - .rel.plt : { *(.rel.plt) }
34   - .rela.plt : { *(.rela.plt) }
35   - .init : { *(.init) }
36   - .plt : { *(.plt) }
37   - .text :
38   - {
39   - /* WARNING - the following is hand-optimized to fit within */
40   - /* the sector layout of our flash chips! XXX FIXME XXX */
41   -
42   - arch/powerpc/cpu/mpc8xx/start.o (.text)
43   - common/dlmalloc.o (.text)
44   - lib/vsprintf.o (.text)
45   - lib/crc32.o (.text)
46   -
47   - . = env_offset;
48   - common/env_embedded.o(.text)
49   -
50   - *(.text)
51   - *(.got1)
52   - }
53   - _etext = .;
54   - PROVIDE (etext = .);
55   - .rodata :
56   - {
57   - *(.rodata)
58   - *(.rodata1)
59   - *(.rodata.str1.4)
60   - *(.eh_frame)
61   - }
62   - .fini : { *(.fini) } =0
63   - .ctors : { *(.ctors) }
64   - .dtors : { *(.dtors) }
65   -
66   - /* Read-write section, merged into data segment: */
67   - . = (. + 0x0FFF) & 0xFFFFF000;
68   - _erotext = .;
69   - PROVIDE (erotext = .);
70   - .reloc :
71   - {
72   - *(.got)
73   - _GOT2_TABLE_ = .;
74   - *(.got2)
75   - _FIXUP_TABLE_ = .;
76   - *(.fixup)
77   - }
78   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80   -
81   - .data :
82   - {
83   - *(.data)
84   - *(.data1)
85   - *(.sdata)
86   - *(.sdata2)
87   - *(.dynamic)
88   - CONSTRUCTORS
89   - }
90   - _edata = .;
91   - PROVIDE (edata = .);
92   -
93   -
94   - . = ALIGN(4);
95   - .u_boot_list : {
96   - KEEP(*(SORT(.u_boot_list*)));
97   - }
98   -
99   -
100   - __start___ex_table = .;
101   - __ex_table : { *(__ex_table) }
102   - __stop___ex_table = .;
103   -
104   - . = ALIGN(4096);
105   - __init_begin = .;
106   - .text.init : { *(.text.init) }
107   - .data.init : { *(.data.init) }
108   - . = ALIGN(4096);
109   - __init_end = .;
110   -
111   - __bss_start = .;
112   - .bss :
113   - {
114   - *(.sbss) *(.scommon)
115   - *(.dynbss)
116   - *(.bss)
117   - *(COMMON)
118   - }
119   - __bss_end = . ;
120   - PROVIDE (end = .);
121   -}
configs/stxxtc_defconfig
View file @ 0ace4d9
1   -CONFIG_PPC=y
2   -CONFIG_8xx=y
3   -CONFIG_TARGET_STXXTC=y
doc/README.scrapyard
Diff comments   View file @ 0ace4d9
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +stxxtc powerpc mpc8xx - - Dan Malek <dan@embeddedalley.com>
15 16 omap5912osk arm arm926ejs - - Rishi Bhattacharya <rishi@ti.com>
16 17 p1023rds powerpc mpc85xx d0bc5140 2014-07-22 Roy Zang <tie-fei.zang@freescale.com>
17 18 spc1920 powerpc mpc8xx 98ad54be 2014-07-07
... ... @@ -32,10 +32,7 @@
32 32 defined(CONFIG_MPC866) || \
33 33 defined(CONFIG_MPC866P)
34 34 # define CONFIG_MPC866_FAMILY 1
35   -#elif defined(CONFIG_MPC870) \
36   - || defined(CONFIG_MPC875) \
37   - || defined(CONFIG_MPC880) \
38   - || defined(CONFIG_MPC885)
  35 +#elif defined(CONFIG_MPC885)
39 36 # define CONFIG_MPC885_FAMILY 1
40 37 #endif
41 38 #if defined(CONFIG_MPC860) \
include/configs/stxxtc.h
View file @ 0ace4d9
1   -/*
2   - * (C) Copyright 2000-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
10   - * U-Boot port on STx XTc 8xx board
11   - * Mostly copied from Panto's NETTA2 board.
12   - */
13   -
14   -#ifndef __CONFIG_H
15   -#define __CONFIG_H
16   -
17   -/*
18   - * High Level Configuration Options
19   - * (easy to change)
20   - */
21   -
22   -#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
23   -#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
24   -
25   -#define CONFIG_SYS_TEXT_BASE 0x40F00000
26   -
27   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28   -#undef CONFIG_8xx_CONS_SMC2
29   -#undef CONFIG_8xx_CONS_NONE
30   -
31   -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
32   -
33   -#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
34   -
35   -/* Select one of few clock rates defined later in this file.
36   -*/
37   -/* #define MPC8XX_HZ 50000000 */
38   -#define MPC8XX_HZ 66666666
39   -
40   -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
41   -
42   -#if 0
43   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
44   -#else
45   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
46   -#endif
47   -
48   -#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
49   -
50   -#undef CONFIG_BOOTARGS
51   -#define CONFIG_BOOTCOMMAND \
52   - "tftpboot; " \
53   - "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
54   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
55   - "bootm"
56   -
57   -#define CONFIG_SOURCE
58   -#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
59   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
60   -
61   -#undef CONFIG_WATCHDOG /* watchdog disabled */
62   -
63   -#define CONFIG_STATUS_LED 1 /* Status LED enabled */
64   -#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
65   -
66   -/*
67   - * BOOTP options
68   - */
69   -#define CONFIG_BOOTP_SUBNETMASK
70   -#define CONFIG_BOOTP_GATEWAY
71   -#define CONFIG_BOOTP_HOSTNAME
72   -#define CONFIG_BOOTP_BOOTPATH
73   -#define CONFIG_BOOTP_BOOTFILESIZE
74   -#define CONFIG_BOOTP_NISDOMAIN
75   -
76   -
77   -#undef CONFIG_MAC_PARTITION
78   -#undef CONFIG_DOS_PARTITION
79   -
80   -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
81   -
82   -#define FEC_ENET 1 /* eth.c needs it that way... */
83   -#undef CONFIG_SYS_DISCOVER_PHY
84   -#define CONFIG_MII 1
85   -#define CONFIG_MII_INIT 1
86   -#undef CONFIG_RMII
87   -
88   -#define CONFIG_ETHER_ON_FEC1 1
89   -#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
90   -#undef CONFIG_FEC1_PHY_NORXERR
91   -
92   -#define CONFIG_ETHER_ON_FEC2 1
93   -#define CONFIG_FEC2_PHY 3
94   -#undef CONFIG_FEC2_PHY_NORXERR
95   -
96   -#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
97   -
98   -
99   -/*
100   - * Command line configuration.
101   - */
102   -#include <config_cmd_default.h>
103   -
104   -#define CONFIG_CMD_DHCP
105   -#define CONFIG_CMD_MII
106   -#define CONFIG_CMD_NFS
107   -#define CONFIG_CMD_PING
108   -
109   -
110   -#define CONFIG_BOARD_EARLY_INIT_F 1
111   -#define CONFIG_MISC_INIT_R
112   -
113   -/*
114   - * Miscellaneous configurable options
115   - */
116   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
117   -#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
118   -
119   -#define CONFIG_SYS_HUSH_PARSER 1
120   -
121   -#if defined(CONFIG_CMD_KGDB)
122   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
123   -#else
124   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
125   -#endif
126   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
129   -
130   -#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
131   -#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
132   -
133   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
134   -
135   -/*
136   - * Low Level Configuration Settings
137   - * (address mappings, register initial values, etc.)
138   - * You should know what you are doing if you make changes here.
139   - */
140   -/*-----------------------------------------------------------------------
141   - * Internal Memory Mapped Register
142   - */
143   -#define CONFIG_SYS_IMMR 0xFF000000
144   -
145   -/*-----------------------------------------------------------------------
146   - * Definitions for initial stack pointer and data area (in DPRAM)
147   - */
148   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
149   -#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
150   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
151   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
152   -
153   -/*-----------------------------------------------------------------------
154   - * Start addresses for the final memory configuration
155   - * (Set up by the startup code)
156   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
157   - */
158   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
159   -#define CONFIG_SYS_FLASH_BASE 0x40000000
160   -#if defined(DEBUG)
161   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
162   -#else
163   -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
164   -#endif
165   -
166   -/* yes this is weird, I know :) */
167   -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
168   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
169   -
170   -#define CONFIG_SYS_RESET_ADDRESS 0x80000000
171   -
172   -/*
173   - * For booting Linux, the board info and command line data
174   - * have to be in the first 8 MB of memory, since this is
175   - * the maximum mapped by the Linux kernel during initialization.
176   - */
177   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
178   -
179   -/*-----------------------------------------------------------------------
180   - * FLASH organization
181   - */
182   -#define CONFIG_ENV_IS_IN_FLASH 1
183   -#define CONFIG_ENV_SECT_SIZE 0x10000
184   -
185   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
186   -#define CONFIG_ENV_OFFSET 0
187   -#define CONFIG_ENV_SIZE 0x4000
188   -
189   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
190   -#define CONFIG_ENV_OFFSET_REDUND 0
191   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
192   -
193   -#define CONFIG_SYS_FLASH_CFI 1
194   -#define CONFIG_FLASH_CFI_DRIVER 1
195   -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
196   -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
197   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
198   -
199   -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
200   -
201   -#define CONFIG_SYS_FLASH_PROTECTION
202   -
203   -/*-----------------------------------------------------------------------
204   - * Cache Configuration
205   - */
206   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
207   -#if defined(CONFIG_CMD_KGDB)
208   -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
209   -#endif
210   -
211   -/*-----------------------------------------------------------------------
212   - * SYPCR - System Protection Control 11-9
213   - * SYPCR can only be written once after reset!
214   - *-----------------------------------------------------------------------
215   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
216   - */
217   -#if defined(CONFIG_WATCHDOG)
218   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
219   - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
220   -#else
221   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
222   -#endif
223   -
224   -/*-----------------------------------------------------------------------
225   - * SIUMCR - SIU Module Configuration 11-6
226   - *-----------------------------------------------------------------------
227   - * PCMCIA config., multi-function pin tri-state
228   - */
229   -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
230   -
231   -/*-----------------------------------------------------------------------
232   - * TBSCR - Time Base Status and Control 11-26
233   - *-----------------------------------------------------------------------
234   - * Clear Reference Interrupt Status, Timebase freezing enabled
235   - */
236   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
237   -
238   -/*-----------------------------------------------------------------------
239   - * RTCSC - Real-Time Clock Status and Control Register 11-27
240   - *-----------------------------------------------------------------------
241   - */
242   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
243   -
244   -/*-----------------------------------------------------------------------
245   - * PISCR - Periodic Interrupt Status and Control 11-31
246   - *-----------------------------------------------------------------------
247   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
248   - */
249   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
250   -
251   -/*-----------------------------------------------------------------------
252   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
253   - *-----------------------------------------------------------------------
254   - * Reset PLL lock status sticky bit, timer expired status bit and timer
255   - * interrupt status bit
256   - *
257   - */
258   -
259   -#if CONFIG_XIN == 10000000
260   -
261   -#if MPC8XX_HZ == 50000000
262   -#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
263   - (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
264   - PLPRCR_TEXPS)
265   -#elif MPC8XX_HZ == 66666666
266   -#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
267   - (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
268   - PLPRCR_TEXPS)
269   -#else
270   -#error unsupported CPU freq for XIN = 10MHz
271   -#endif
272   -#else
273   -#error unsupported freq for XIN (must be 10MHz)
274   -#endif
275   -
276   -
277   -/*
278   - *-----------------------------------------------------------------------
279   - * SCCR - System Clock and reset Control Register 15-27
280   - *-----------------------------------------------------------------------
281   - * Set clock output, timebase and RTC source and divider,
282   - * power management and some other internal clocks
283   - *
284   - * Note: When TBS == 0 the timebase is independent of current cpu clock.
285   - */
286   -
287   -#define SCCR_MASK SCCR_EBDF11
288   -#if MPC8XX_HZ > 66666666
289   -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
290   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
291   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
292   - SCCR_DFALCD00 | SCCR_EBDF01)
293   -#else
294   -#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
295   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
296   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
297   - SCCR_DFALCD00)
298   -#endif
299   -
300   -/*-----------------------------------------------------------------------
301   - *
302   - *-----------------------------------------------------------------------
303   - *
304   - */
305   -/*#define CONFIG_SYS_DER 0x2002000F*/
306   -#define CONFIG_SYS_DER 0
307   -
308   -/*
309   - * Init Memory Controller:
310   - *
311   - * BR0/1 and OR0/1 (FLASH)
312   - */
313   -
314   -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
315   -#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
316   -
317   -/* used to re-map FLASH both when starting from SRAM or FLASH:
318   - * restrict access enough to keep SRAM working (if any)
319   - * but not too much to meddle with FLASH accesses
320   - */
321   -
322   -#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
323   -
324   -#define CONFIG_SYS_REMAP_OR_AM 0x80000000
325   -#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
326   -
327   -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
328   -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
329   -
330   -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
331   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
332   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
333   -
334   -#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
335   -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
336   -
337   -/*
338   - * BR4 and OR4 (SDRAM)
339   - *
340   - */
341   -#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
342   -#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
343   -
344   -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
345   -#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
346   -
347   -#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
348   -#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
349   -
350   -/*
351   - * Memory Periodic Timer Prescaler
352   - */
353   -
354   -/*
355   - * Memory Periodic Timer Prescaler
356   - *
357   - * The Divider for PTA (refresh timer) configuration is based on an
358   - * example SDRAM configuration (64 MBit, one bank). The adjustment to
359   - * the number of chip selects (NCS) and the actually needed refresh
360   - * rate is done by setting MPTPR.
361   - *
362   - * PTA is calculated from
363   - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
364   - *
365   - * gclk CPU clock (not bus clock!)
366   - * Trefresh Refresh cycle * 4 (four word bursts used)
367   - *
368   - * 4096 Rows from SDRAM example configuration
369   - * 1000 factor s -> ms
370   - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
371   - * 4 Number of refresh cycles per period
372   - * 64 Refresh cycle in ms per number of rows
373   - * --------------------------------------------
374   - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
375   - *
376   - * 50 MHz => 50.000.000 / Divider = 98
377   - * 66 Mhz => 66.000.000 / Divider = 129
378   - * 80 Mhz => 80.000.000 / Divider = 156
379   - */
380   -
381   -#define CONFIG_SYS_MAMR_PTA 234
382   -
383   -/*
384   - * For 16 MBit, refresh rates could be 31.3 us
385   - * (= 64 ms / 2K = 125 / quad bursts).
386   - * For a simpler initialization, 15.6 us is used instead.
387   - *
388   - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
389   - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
390   - */
391   -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
392   -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
393   -
394   -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
395   -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
396   -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
397   -
398   -/*
399   - * MAMR settings for SDRAM
400   - */
401   -
402   -/* 8 column SDRAM */
403   -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
404   - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
405   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
406   -
407   -/* 9 column SDRAM */
408   -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
409   - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
410   - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
411   -
412   -#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
413   -
414   -/****************************************************************/
415   -
416   -#define NAND_SIZE 0x00010000 /* 64K */
417   -#define NAND_BASE 0xF1000000
418   -
419   -/*****************************************************************************/
420   -
421   -#define CONFIG_SYS_DIRECT_FLASH_TFTP
422   -
423   -/*****************************************************************************/
424   -
425   -/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
426   - * CxOE and CxRESET. We use the CxOE.
427   - */
428   -#define STATUS_LED_BIT 0x00000080 /* bit 24 */
429   -
430   -#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
431   -#define STATUS_LED_STATE STATUS_LED_BLINKING
432   -
433   -#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
434   -#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
435   -
436   -#ifndef __ASSEMBLY__
437   -
438   -/* LEDs */
439   -
440   -/* led_id_t is unsigned int mask */
441   -typedef unsigned int led_id_t;
442   -
443   -#define __led_toggle(_msk) \
444   - do { \
445   - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
446   - } while(0)
447   -
448   -#define __led_set(_msk, _st) \
449   - do { \
450   - if ((_st)) \
451   - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
452   - else \
453   - ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
454   - } while(0)
455   -
456   -#define __led_init(msk, st) __led_set(msk, st)
457   -
458   -#endif
459   -
460   -/******************************************************************************/
461   -
462   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
463   -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
464   -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
465   -
466   -/******************************************************************************/
467   -
468   -/* use board specific hardware */
469   -#undef CONFIG_WATCHDOG /* watchdog disabled */
470   -#define CONFIG_HW_WATCHDOG
471   -
472   -/*****************************************************************************/
473   -
474   -#define CONFIG_AUTO_COMPLETE 1
475   -#define CONFIG_CRC32_VERIFY 1
476   -#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
477   -
478   -/*****************************************************************************/
479   -
480   -/* pass open firmware flattened device tree */
481   -#define CONFIG_OF_LIBFDT 1
482   -
483   -#define OF_TBCLK (MPC8XX_HZ / 16)
484   -
485   -#endif /* __CONFIG_H */
include/status_led.h
Diff comments   View file @ 0ace4d9
... ... @@ -231,10 +231,6 @@
231 231  
232 232 # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
233 233  
234   -/***** STx XTc ********************************************************/
235   -#elif defined(CONFIG_STXXTC)
236   -/* XXX empty just to avoid the error */
237   -/************************************************************************/
238 234 #elif defined(CONFIG_V38B)
239 235  
240 236 # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */