serial: 16550: Add Ingenic JZ4780 support

Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>

serial: 16550: Add Ingenic JZ4780 support
Add compatibility string for the Ingenic JZ4780 SoC, the necessary UART enable bit into FCR and register shift. Neither are encoded in the DTS coming from Linux, so we need to support it this way. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut · Tom Rini
1 parent 79fd928188
Showing 2 changed files with 8 additions and 0 deletions Side-by-side Diff
drivers/serial/ns16550.c
include/ns16550.h
@@ -363,6 +363,7 @@
 #if CONFIG_IS_ENABLED(OF_CONTROL)
 enum {
 	PORT_NS16550 = 0,
+	PORT_JZ4780,
 };
 #endif
  
@@ -370,6 +371,7 @@
 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ns16550_platdata *plat = dev->platdata;
+	const u32 port_type = dev_get_driver_data(dev);
 	fdt_addr_t addr;
 	struct clk clk;
 	int err;
@@ -439,6 +441,8 @@
 	}
  
 	plat->fcr = UART_FCRVAL;
+	if (port_type == PORT_JZ4780)
+		plat->fcr |= UART_FCR_UME;
  
 	return 0;
 }
@@ -461,6 +465,7 @@
 static const struct udevice_id ns16550_serial_ids[] = {
 	{ .compatible = "ns16550",		.data = PORT_NS16550 },
 	{ .compatible = "ns16550a",		.data = PORT_NS16550 },
+	{ .compatible = "ingenic,jz4780-uart",	.data = PORT_JZ4780  },
 	{ .compatible = "nvidia,tegra20-uart",	.data = PORT_NS16550 },
 	{ .compatible = "snps,dw-apb-uart",	.data = PORT_NS16550 },
 	{ .compatible = "ti,omap2-uart",	.data = PORT_NS16550 },
@@ -118,6 +118,9 @@
 #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
 #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
  
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME		0x10
+
 /*
  * These are the definitions for the Modem Control Register
  */
...	...	@@ -363,6 +363,7 @@
363	363	#if CONFIG_IS_ENABLED(OF_CONTROL)
364	364	enum {
365	365	PORT_NS16550 = 0,
	366	+ PORT_JZ4780,
366	367	};
367	368	#endif
368	369
...	...	@@ -370,6 +371,7 @@
370	371	int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
371	372	{
372	373	struct ns16550_platdata *plat = dev->platdata;
	374	+ const u32 port_type = dev_get_driver_data(dev);
373	375	fdt_addr_t addr;
374	376	struct clk clk;
375	377	int err;
...	...	@@ -439,6 +441,8 @@
439	441	}
440	442
441	443	plat->fcr = UART_FCRVAL;
	444	+ if (port_type == PORT_JZ4780)
	445	+ plat->fcr \|= UART_FCR_UME;
442	446
443	447	return 0;
444	448	}
...	...	@@ -461,6 +465,7 @@
461	465	static const struct udevice_id ns16550_serial_ids[] = {
462	466	{ .compatible = "ns16550", .data = PORT_NS16550 },
463	467	{ .compatible = "ns16550a", .data = PORT_NS16550 },
	468	+ { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
464	469	{ .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
465	470	{ .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
466	471	{ .compatible = "ti,omap2-uart", .data = PORT_NS16550 },
...	...	@@ -118,6 +118,9 @@
118	118	#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
119	119	#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
120	120
	121	+/* Ingenic JZ47xx specific UART-enable bit. */
	122	+#define UART_FCR_UME 0x10
	123	+
121	124	/*
122	125	* These are the definitions for the Modem Control Register
123	126	*/