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Commit 0b2e13d9ccbe56e32dc674cf896b2fb55684368c

Authored by Chunhe Lan
Committed by York Sun
1 parent 652e29b4a0
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/85xx: Add T4240RDB board support 

T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]

Showing 15 changed files with 1453 additions and 1 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/t4240_ids.c
Diff comments   View file @ 0b2e13d
... ... @@ -64,11 +64,13 @@
64 64 };
65 65 #endif
66 66  
  67 +#ifdef CONFIG_SYS_SRIO
67 68 struct srio_liodn_id_table srio_liodn_tbl[] = {
68 69 SET_SRIO_LIODN_BASE(1, 307),
69 70 SET_SRIO_LIODN_BASE(2, 387),
70 71 };
71 72 int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
  73 +#endif
72 74  
73 75 struct liodn_id_table liodn_tbl[] = {
74 76 #ifdef CONFIG_SYS_DPAA_QBMAN
board/freescale/t4rdb/Makefile
Diff comments   View file @ 0b2e13d
  1 +#
  2 +# Copyright 2014 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-$(CONFIG_T4240RDB) += t4240rdb.o
  8 +obj-y += ddr.o
  9 +obj-y += eth.o
  10 +obj-$(CONFIG_PCI) += pci.o
  11 +obj-y += law.o
  12 +obj-y += tlb.o
board/freescale/t4rdb/ddr.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <i2c.h>
  9 +#include <hwconfig.h>
  10 +#include <asm/mmu.h>
  11 +#include <fsl_ddr_sdram.h>
  12 +#include <fsl_ddr_dimm_params.h>
  13 +#include <asm/fsl_law.h>
  14 +#include "ddr.h"
  15 +
  16 +DECLARE_GLOBAL_DATA_PTR;
  17 +
  18 +void fsl_ddr_board_options(memctl_options_t *popts,
  19 + dimm_params_t *pdimm,
  20 + unsigned int ctrl_num)
  21 +{
  22 + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  23 + ulong ddr_freq;
  24 +
  25 + if (ctrl_num > 2) {
  26 + printf("Not supported controller number %d\n", ctrl_num);
  27 + return;
  28 + }
  29 + if (!pdimm->n_ranks)
  30 + return;
  31 +
  32 + /*
  33 + * we use identical timing for all slots. If needed, change the code
  34 + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  35 + */
  36 + if (popts->registered_dimm_en)
  37 + pbsp = rdimms[0];
  38 + else
  39 + pbsp = udimms[0];
  40 +
  41 +
  42 + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  43 + * freqency and n_banks specified in board_specific_parameters table.
  44 + */
  45 + ddr_freq = get_ddr_freq(0) / 1000000;
  46 + while (pbsp->datarate_mhz_high) {
  47 + if (pbsp->n_ranks == pdimm->n_ranks &&
  48 + (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  49 + if (ddr_freq <= pbsp->datarate_mhz_high) {
  50 + popts->clk_adjust = pbsp->clk_adjust;
  51 + popts->wrlvl_start = pbsp->wrlvl_start;
  52 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  53 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  54 + goto found;
  55 + }
  56 + pbsp_highest = pbsp;
  57 + }
  58 + pbsp++;
  59 + }
  60 +
  61 + if (pbsp_highest) {
  62 + printf("Error: board specific timing not found for data\n"
  63 + "rate %lu MT/s\n"
  64 + "Trying to use the highest speed (%u) parameters\n",
  65 + ddr_freq, pbsp_highest->datarate_mhz_high);
  66 + popts->clk_adjust = pbsp_highest->clk_adjust;
  67 + popts->wrlvl_start = pbsp_highest->wrlvl_start;
  68 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  69 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  70 + } else {
  71 + panic("DIMM is not supported by this board");
  72 + }
  73 +found:
  74 + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  75 + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n"
  76 + "wrlvl_ctrl_3 0x%x\n",
  77 + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  78 + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  79 + pbsp->wrlvl_ctl_3);
  80 +
  81 + /*
  82 + * Factors to consider for half-strength driver enable:
  83 + * - number of DIMMs installed
  84 + */
  85 + popts->half_strength_driver_enable = 0;
  86 + /*
  87 + * Write leveling override
  88 + */
  89 + popts->wrlvl_override = 1;
  90 + popts->wrlvl_sample = 0xf;
  91 +
  92 + /*
  93 + * Rtt and Rtt_WR override
  94 + */
  95 + popts->rtt_override = 0;
  96 +
  97 + /* Enable ZQ calibration */
  98 + popts->zq_en = 1;
  99 +
  100 + /* DHC_EN =1, ODT = 75 Ohm */
  101 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  102 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  103 +}
  104 +
  105 +phys_size_t initdram(int board_type)
  106 +{
  107 + phys_size_t dram_size;
  108 +
  109 + puts("Initializing....using SPD\n");
  110 +
  111 + dram_size = fsl_ddr_sdram();
  112 +
  113 + dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  114 + dram_size *= 0x100000;
  115 +
  116 + puts(" DDR: ");
  117 + return dram_size;
  118 +}
board/freescale/t4rdb/ddr.h
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DDR_H__
  8 +#define __DDR_H__
  9 +struct board_specific_parameters {
  10 + u32 n_ranks;
  11 + u32 datarate_mhz_high;
  12 + u32 rank_gb;
  13 + u32 clk_adjust;
  14 + u32 wrlvl_start;
  15 + u32 wrlvl_ctl_2;
  16 + u32 wrlvl_ctl_3;
  17 +};
  18 +
  19 +/*
  20 + * These tables contain all valid speeds we want to override with board
  21 + * specific parameters. datarate_mhz_high values need to be in ascending order
  22 + * for each n_ranks group.
  23 + */
  24 +static const struct board_specific_parameters udimm0[] = {
  25 + /*
  26 + * memory controller 0
  27 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  28 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  29 + */
  30 + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a},
  31 + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09},
  32 + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b},
  33 + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a},
  34 + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
  35 + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c},
  36 + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a},
  37 + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a},
  38 + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a},
  39 + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b},
  40 + {}
  41 +};
  42 +
  43 +static const struct board_specific_parameters rdimm0[] = {
  44 + /*
  45 + * memory controller 0
  46 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl
  47 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3
  48 + */
  49 + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  50 + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906},
  51 + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
  52 + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  53 + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
  54 + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07},
  55 + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806},
  56 + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06},
  57 + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07},
  58 + {}
  59 +};
  60 +
  61 +/*
  62 + * The three slots have slightly different timing. The center values are good
  63 + * for all slots. We use identical speed tables for them. In future use, if
  64 + * DIMMs require separated tables, make more entries as needed.
  65 + */
  66 +static const struct board_specific_parameters *udimms[] = {
  67 + udimm0,
  68 +};
  69 +
  70 +/*
  71 + * The three slots have slightly different timing. See comments above.
  72 + */
  73 +static const struct board_specific_parameters *rdimms[] = {
  74 + rdimm0,
  75 +};
  76 +
  77 +
  78 +#endif
board/freescale/t4rdb/eth.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Chunhe Lan <Chunhe.Lan@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <command.h>
  11 +#include <netdev.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/cache.h>
  15 +#include <asm/immap_85xx.h>
  16 +#include <asm/fsl_law.h>
  17 +#include <fsl_ddr_sdram.h>
  18 +#include <asm/fsl_serdes.h>
  19 +#include <asm/fsl_portals.h>
  20 +#include <asm/fsl_liodn.h>
  21 +#include <malloc.h>
  22 +#include <fm_eth.h>
  23 +#include <fsl_mdio.h>
  24 +#include <miiphy.h>
  25 +#include <phy.h>
  26 +#include <asm/fsl_dtsec.h>
  27 +#include <asm/fsl_serdes.h>
  28 +#include <hwconfig.h>
  29 +
  30 +#include "../common/fman.h"
  31 +#include "t4rdb.h"
  32 +
  33 +void fdt_fixup_board_enet(void *fdt)
  34 +{
  35 + return;
  36 +}
  37 +
  38 +int board_eth_init(bd_t *bis)
  39 +{
  40 +#if defined(CONFIG_FMAN_ENET)
  41 + int i, interface;
  42 + struct memac_mdio_info dtsec_mdio_info;
  43 + struct memac_mdio_info tgec_mdio_info;
  44 + struct mii_dev *dev;
  45 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46 + u32 srds_prtcl_s1, srds_prtcl_s2;
  47 +
  48 + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  49 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  50 + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  51 + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  52 + FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  53 + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  54 +
  55 + dtsec_mdio_info.regs =
  56 + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
  57 +
  58 + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  59 +
  60 + /* Register the 1G MDIO bus */
  61 + fm_memac_mdio_init(bis, &dtsec_mdio_info);
  62 +
  63 + tgec_mdio_info.regs =
  64 + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
  65 + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  66 +
  67 + /* Register the 10G MDIO bus */
  68 + fm_memac_mdio_init(bis, &tgec_mdio_info);
  69 +
  70 + if (srds_prtcl_s1 == 28) {
  71 + /* SGMII */
  72 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
  73 + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
  74 + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
  75 + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
  76 + } else {
  77 + puts("Invalid SerDes1 protocol for T4240RDB\n");
  78 + }
  79 +
  80 + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  81 + interface = fm_info_get_enet_if(i);
  82 + switch (interface) {
  83 + case PHY_INTERFACE_MODE_SGMII:
  84 + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  85 + fm_info_set_mdio(i, dev);
  86 + break;
  87 + default:
  88 + break;
  89 + }
  90 + }
  91 +
  92 + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  93 + switch (fm_info_get_enet_if(i)) {
  94 + case PHY_INTERFACE_MODE_XGMII:
  95 + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  96 + fm_info_set_mdio(i, dev);
  97 + break;
  98 + default:
  99 + break;
  100 + }
  101 + }
  102 +
  103 +#if (CONFIG_SYS_NUM_FMAN == 2)
  104 + if (srds_prtcl_s2 == 56) {
  105 + /* SGMII && XFI */
  106 + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
  107 + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
  108 + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
  109 + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
  110 + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
  111 + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
  112 + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
  113 + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
  114 + } else {
  115 + puts("Invalid SerDes2 protocol for T4240RDB\n");
  116 + }
  117 +
  118 + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  119 + interface = fm_info_get_enet_if(i);
  120 + switch (interface) {
  121 + case PHY_INTERFACE_MODE_SGMII:
  122 + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  123 + fm_info_set_mdio(i, dev);
  124 + break;
  125 + default:
  126 + break;
  127 + }
  128 + }
  129 +
  130 + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
  131 + switch (fm_info_get_enet_if(i)) {
  132 + case PHY_INTERFACE_MODE_XGMII:
  133 + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  134 + fm_info_set_mdio(i, dev);
  135 + break;
  136 + default:
  137 + break;
  138 + }
  139 + }
  140 +#endif /* CONFIG_SYS_NUM_FMAN */
  141 +
  142 + cpu_eth_init(bis);
  143 +#endif /* CONFIG_FMAN_ENET */
  144 +
  145 + return pci_eth_init(bis);
  146 +}
board/freescale/t4rdb/law.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/fsl_law.h>
  9 +#include <asm/mmu.h>
  10 +
  11 +struct law_entry law_table[] = {
  12 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
  13 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  14 + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
  15 +#endif
  16 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  17 + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
  18 +#endif
  19 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  20 + /* Limit DCSR to 32M to access NPC Trace Buffer */
  21 + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
  22 +#endif
  23 +#ifdef CONFIG_SYS_NAND_BASE_PHYS
  24 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
  25 +#endif
  26 +};
  27 +
  28 +int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/t4rdb/pci.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <pci.h>
  10 +#include <asm/fsl_pci.h>
  11 +#include <libfdt.h>
  12 +#include <fdt_support.h>
  13 +#include <asm/fsl_serdes.h>
  14 +
  15 +void pci_init_board(void)
  16 +{
  17 + fsl_pcie_init_board(0);
  18 +}
  19 +
  20 +void pci_of_setup(void *blob, bd_t *bd)
  21 +{
  22 + FT_FSL_PCI_SETUP;
  23 +}
board/freescale/t4rdb/t4240rdb.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <i2c.h>
  10 +#include <netdev.h>
  11 +#include <linux/compiler.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/cache.h>
  15 +#include <asm/immap_85xx.h>
  16 +#include <asm/fsl_law.h>
  17 +#include <asm/fsl_serdes.h>
  18 +#include <asm/fsl_portals.h>
  19 +#include <asm/fsl_liodn.h>
  20 +#include <fm_eth.h>
  21 +
  22 +#include "t4rdb.h"
  23 +
  24 +DECLARE_GLOBAL_DATA_PTR;
  25 +
  26 +int checkboard(void)
  27 +{
  28 + struct cpu_type *cpu = gd->arch.cpu;
  29 +
  30 + printf("Board: %sRDB, ", cpu->name);
  31 +
  32 + puts("SERDES Reference Clocks:\n");
  33 + printf(" SERDES1=100MHz SERDES2=156.25MHz\n"
  34 + " SERDES3=100MHz SERDES4=100MHz\n");
  35 +
  36 + return 0;
  37 +}
  38 +
  39 +int board_early_init_r(void)
  40 +{
  41 + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  42 + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  43 +
  44 + /*
  45 + * Remap Boot flash + PROMJET region to caching-inhibited
  46 + * so that flash can be erased properly.
  47 + */
  48 +
  49 + /* Flush d-cache and invalidate i-cache of any FLASH data */
  50 + flush_dcache();
  51 + invalidate_icache();
  52 +
  53 + /* invalidate existing TLB entry for flash + promjet */
  54 + disable_tlb(flash_esel);
  55 +
  56 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  57 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58 + 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  59 +
  60 + set_liodns();
  61 +#ifdef CONFIG_SYS_DPAA_QBMAN
  62 + setup_portals();
  63 +#endif
  64 +
  65 + return 0;
  66 +}
  67 +
  68 +int misc_init_r(void)
  69 +{
  70 + return 0;
  71 +}
  72 +
  73 +void ft_board_setup(void *blob, bd_t *bd)
  74 +{
  75 + phys_addr_t base;
  76 + phys_size_t size;
  77 +
  78 + ft_cpu_setup(blob, bd);
  79 +
  80 + base = getenv_bootm_low();
  81 + size = getenv_bootm_size();
  82 +
  83 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  84 +
  85 +#ifdef CONFIG_PCI
  86 + pci_of_setup(blob, bd);
  87 +#endif
  88 +
  89 + fdt_fixup_liodn(blob);
  90 + fdt_fixup_dr_usb(blob, bd);
  91 +
  92 +#ifdef CONFIG_SYS_DPAA_FMAN
  93 + fdt_fixup_fman_ethernet(blob);
  94 + fdt_fixup_board_enet(blob);
  95 +#endif
  96 +}
  97 +
  98 +/*
  99 + * This function is called by bdinfo to print detail board information.
  100 + * As an exmaple for future board, we organize the messages into
  101 + * several sections. If applicable, the message is in the format of
  102 + * <name> = <value>
  103 + * It should aligned with normal output of bdinfo command.
  104 + *
  105 + * Voltage: Core, DDR and another configurable voltages
  106 + * Clock : Critical clocks which are not printed already
  107 + * RCW : RCW source if not printed already
  108 + * Misc : Other important information not in above catagories
  109 + */
  110 +void board_detail(void)
  111 +{
  112 + int rcwsrc;
  113 +
  114 + /* RCW section SW3[4] */
  115 + rcwsrc = 0x0;
  116 + puts("RCW source = ");
  117 + switch (rcwsrc & 0x1) {
  118 + case 0x1:
  119 + puts("SDHC/eMMC\n");
  120 + break;
  121 + default:
  122 + puts("I2C normal addressing\n");
  123 + break;
  124 + }
  125 +}
board/freescale/t4rdb/t4_pbi.cfg
Diff comments   View file @ 0b2e13d
  1 +#
  2 +# Copyright 2014 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +#PBI commands
  8 +#Initialize CPC1
  9 +09010000 00200400
  10 +09138000 00000000
  11 +091380c0 00000100
  12 +#512KB SRAM
  13 +09010100 00000000
  14 +09010104 fff80009
  15 +09010f00 08000000
  16 +#enable CPC1
  17 +09010000 80000000
  18 +#Configure LAW for CPC1
  19 +09000d00 00000000
  20 +09000d04 fff80000
  21 +09000d08 81000012
  22 +#slow mdio clock
  23 +095fc030 00008148
  24 +095fd030 00808148
  25 +#Configure alternate space
  26 +09000010 00000000
  27 +09000014 ff000000
  28 +09000018 81000000
  29 +#Flush PBL data
  30 +09138000 00000000
  31 +091380c0 00000000
board/freescale/t4rdb/t4_rcw.cfg
Diff comments   View file @ 0b2e13d
  1 +#PBL preamble and RCW header
  2 +aa55aa55 010e0100
  3 +#serdes protocol 28_56_2_10
  4 +16070019 18101916 00000000 00000000
  5 +70701050 00448c00 6c020000 f5000000
  6 +00000000 ee0000ee 00000000 000287fc
  7 +00000000 50000000 00000000 00000028
board/freescale/t4rdb/t4rdb.h
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __T4RDB_H__
  8 +#define __T4RDB_H__
  9 +
  10 +#undef CONFIG_SYS_NUM_FM1_DTSEC
  11 +#undef CONFIG_SYS_NUM_FM2_DTSEC
  12 +#define CONFIG_SYS_NUM_FM1_DTSEC 4
  13 +#define CONFIG_SYS_NUM_FM2_DTSEC 4
  14 +
  15 +void fdt_fixup_board_enet(void *blob);
  16 +void pci_of_setup(void *blob, bd_t *bd);
  17 +
  18 +#endif
board/freescale/t4rdb/tlb.c
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/mmu.h>
  9 +
  10 +struct fsl_e_tlb_entry tlb_table[] = {
  11 + /* TLB 0 - for temp stack in cache */
  12 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15 + 0, 0, BOOKE_PAGESZ_4K, 0),
  16 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  17 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19 + 0, 0, BOOKE_PAGESZ_4K, 0),
  20 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23 + 0, 0, BOOKE_PAGESZ_4K, 0),
  24 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  27 + 0, 0, BOOKE_PAGESZ_4K, 0),
  28 +
  29 + /* TLB 1 */
  30 + /* *I*** - Covers boot page */
  31 +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  32 + /*
  33 + * *I*G - L3SRAM. When L3 is used as 512K SRAM */
  34 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  35 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36 + 0, 0, BOOKE_PAGESZ_512K, 1),
  37 +#else
  38 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  39 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  40 + 0, 0, BOOKE_PAGESZ_4K, 1),
  41 +#endif
  42 +
  43 + /* *I*G* - CCSRBAR */
  44 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  45 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46 + 0, 1, BOOKE_PAGESZ_16M, 1),
  47 +
  48 + /* *I*G* - Flash, localbus */
  49 + /* This will be changed to *I*G* after relocation to RAM. */
  50 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  51 + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  52 + 0, 2, BOOKE_PAGESZ_256M, 1),
  53 +
  54 + /* *I*G* - PCI */
  55 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  56 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57 + 0, 3, BOOKE_PAGESZ_1G, 1),
  58 +
  59 + /* *I*G* - PCI */
  60 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  61 + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  62 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63 + 0, 4, BOOKE_PAGESZ_256M, 1),
  64 +
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  66 + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  67 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68 + 0, 5, BOOKE_PAGESZ_256M, 1),
  69 +
  70 + /* *I*G* - PCI I/O */
  71 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  72 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73 + 0, 6, BOOKE_PAGESZ_256K, 1),
  74 +
  75 + /* Bman/Qman */
  76 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  77 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  78 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  79 + 0, 9, BOOKE_PAGESZ_16M, 1),
  80 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  81 + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  82 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  83 + 0, 10, BOOKE_PAGESZ_16M, 1),
  84 +#endif
  85 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  86 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  87 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  88 + 0, 11, BOOKE_PAGESZ_16M, 1),
  89 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  90 + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  91 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92 + 0, 12, BOOKE_PAGESZ_16M, 1),
  93 +#endif
  94 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  95 + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  96 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97 + 0, 13, BOOKE_PAGESZ_32M, 1),
  98 +#endif
  99 +#ifdef CONFIG_SYS_NAND_BASE
  100 + /*
  101 + * *I*G - NAND
  102 + * entry 14 and 15 has been used hard coded, they will be disabled
  103 + * in cpu_init_f, so we use entry 16 for nand.
  104 + */
  105 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  106 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  107 + 0, 16, BOOKE_PAGESZ_64K, 1),
  108 +#endif
  109 +};
  110 +
  111 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
... ... @@ -983,6 +983,7 @@
983 983 Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
984 984 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
985 985 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
  986 +Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan <Chunhe.Lan@freescale.com>
986 987 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
987 988 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
988 989 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
drivers/mmc/fsl_esdhc.c
Diff comments   View file @ 0b2e13d
... ... @@ -96,7 +96,7 @@
96 96 else if (cmd->resp_type & MMC_RSP_PRESENT)
97 97 xfertyp |= XFERTYP_RSPTYP_48;
98 98  
99   -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
  99 +#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
100 100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
101 101 xfertyp |= XFERTYP_CMDTYP_ABORT;
102 102 #endif
include/configs/T4240RDB.h
Diff comments   View file @ 0b2e13d
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * T4240 RDB board configuration file
  9 + */
  10 +#ifndef __CONFIG_H
  11 +#define __CONFIG_H
  12 +
  13 +#define CONFIG_T4240RDB
  14 +#define CONFIG_PHYS_64BIT
  15 +
  16 +#define CONFIG_FSL_SATA_V2
  17 +#define CONFIG_PCIE4
  18 +
  19 +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  20 +
  21 +#ifdef CONFIG_RAMBOOT_PBL
  22 +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  23 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  24 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
  25 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
  26 +#endif
  27 +
  28 +#define CONFIG_DDR_ECC
  29 +
  30 +#define CONFIG_CMD_REGINFO
  31 +
  32 +/* High Level Configuration Options */
  33 +#define CONFIG_BOOKE
  34 +#define CONFIG_E500 /* BOOKE e500 family */
  35 +#define CONFIG_E500MC /* BOOKE e500mc family */
  36 +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  37 +#define CONFIG_MP /* support multiple processors */
  38 +
  39 +#ifndef CONFIG_SYS_TEXT_BASE
  40 +#define CONFIG_SYS_TEXT_BASE 0xeff40000
  41 +#endif
  42 +
  43 +#ifndef CONFIG_RESET_VECTOR_ADDRESS
  44 +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  45 +#endif
  46 +
  47 +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  48 +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  49 +#define CONFIG_FSL_IFC /* Enable IFC Support */
  50 +#define CONFIG_PCI /* Enable PCI/PCIE */
  51 +#define CONFIG_PCIE1 /* PCIE controler 1 */
  52 +#define CONFIG_PCIE2 /* PCIE controler 2 */
  53 +#define CONFIG_PCIE3 /* PCIE controler 3 */
  54 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  55 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  56 +
  57 +#define CONFIG_FSL_LAW /* Use common FSL init code */
  58 +
  59 +#define CONFIG_ENV_OVERWRITE
  60 +
  61 +/*
  62 + * These can be toggled for performance analysis, otherwise use default.
  63 + */
  64 +#define CONFIG_SYS_CACHE_STASHING
  65 +#define CONFIG_BTB /* toggle branch predition */
  66 +#ifdef CONFIG_DDR_ECC
  67 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  68 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  69 +#endif
  70 +
  71 +#define CONFIG_ENABLE_36BIT_PHYS
  72 +
  73 +#define CONFIG_ADDR_MAP
  74 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  75 +
  76 +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  77 +#define CONFIG_SYS_MEMTEST_END 0x00400000
  78 +#define CONFIG_SYS_ALT_MEMTEST
  79 +#define CONFIG_PANIC_HANG /* do not reset board on panic */
  80 +
  81 +/*
  82 + * Config the L3 Cache as L3 SRAM
  83 + */
  84 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  85 +
  86 +#define CONFIG_SYS_DCSRBAR 0xf0000000
  87 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  88 +
  89 +/*
  90 + * DDR Setup
  91 + */
  92 +#define CONFIG_VERY_BIG_RAM
  93 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  94 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  95 +
  96 +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
  97 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  98 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
  99 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
  100 +
  101 +#define CONFIG_DDR_SPD
  102 +#define CONFIG_SYS_FSL_DDR3
  103 +
  104 +
  105 +/*
  106 + * IFC Definitions
  107 + */
  108 +#define CONFIG_SYS_FLASH_BASE 0xe0000000
  109 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  110 +
  111 +
  112 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  113 +
  114 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  115 +#define CONFIG_MISC_INIT_R
  116 +
  117 +#define CONFIG_HWCONFIG
  118 +
  119 +/* define to use L1 as initial stack */
  120 +#define CONFIG_L1_INIT_RAM
  121 +#define CONFIG_SYS_INIT_RAM_LOCK
  122 +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  123 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  124 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  125 +/* The assembler doesn't like typecast */
  126 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  127 + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  128 + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  129 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  130 +
  131 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  132 + GENERATED_GBL_DATA_SIZE)
  133 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  134 +
  135 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  136 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  137 +
  138 +/* Serial Port - controlled on board with jumper J8
  139 + * open - index 2
  140 + * shorted - index 1
  141 + */
  142 +#define CONFIG_CONS_INDEX 1
  143 +#define CONFIG_SYS_NS16550
  144 +#define CONFIG_SYS_NS16550_SERIAL
  145 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  146 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  147 +
  148 +#define CONFIG_SYS_BAUDRATE_TABLE \
  149 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  150 +
  151 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  152 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  153 +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  154 +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  155 +
  156 +/* Use the HUSH parser */
  157 +#define CONFIG_SYS_HUSH_PARSER
  158 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  159 +
  160 +/* pass open firmware flat tree */
  161 +#define CONFIG_OF_LIBFDT
  162 +#define CONFIG_OF_BOARD_SETUP
  163 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  164 +
  165 +/* new uImage format support */
  166 +#define CONFIG_FIT
  167 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  168 +
  169 +/* I2C */
  170 +#define CONFIG_SYS_I2C
  171 +#define CONFIG_SYS_I2C_FSL
  172 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  173 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  174 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  175 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  176 +
  177 +/*
  178 + * General PCI
  179 + * Memory space is mapped 1-1, but I/O space must start from 0.
  180 + */
  181 +
  182 +/* controller 1, direct to uli, tgtid 3, Base address 20000 */
  183 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  184 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  185 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  186 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  187 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  188 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  189 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  190 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  191 +
  192 +/* controller 2, Slot 2, tgtid 2, Base address 201000 */
  193 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  194 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  195 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  196 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  197 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  198 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  199 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  200 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  201 +
  202 +/* controller 3, Slot 1, tgtid 1, Base address 202000 */
  203 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  204 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  205 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  206 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  207 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  208 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  209 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  210 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  211 +
  212 +/* controller 4, Base address 203000 */
  213 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  214 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  215 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  216 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  217 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  218 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  219 +
  220 +#ifdef CONFIG_PCI
  221 +#define CONFIG_PCI_INDIRECT_BRIDGE
  222 +#define CONFIG_NET_MULTI
  223 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  224 +#define CONFIG_E1000
  225 +
  226 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  227 +#define CONFIG_DOS_PARTITION
  228 +#endif /* CONFIG_PCI */
  229 +
  230 +/* SATA */
  231 +#ifdef CONFIG_FSL_SATA_V2
  232 +#define CONFIG_LIBATA
  233 +#define CONFIG_FSL_SATA
  234 +
  235 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  236 +#define CONFIG_SATA1
  237 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  238 +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  239 +#define CONFIG_SATA2
  240 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  241 +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  242 +
  243 +#define CONFIG_LBA48
  244 +#define CONFIG_CMD_SATA
  245 +#define CONFIG_DOS_PARTITION
  246 +#define CONFIG_CMD_EXT2
  247 +#endif
  248 +
  249 +#ifdef CONFIG_FMAN_ENET
  250 +#define CONFIG_MII /* MII PHY management */
  251 +#define CONFIG_ETHPRIME "FM1@DTSEC1"
  252 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  253 +#endif
  254 +
  255 +/*
  256 + * Environment
  257 + */
  258 +#define CONFIG_LOADS_ECHO /* echo on for serial download */
  259 +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  260 +
  261 +/*
  262 + * Command line configuration.
  263 + */
  264 +#include <config_cmd_default.h>
  265 +
  266 +#define CONFIG_CMD_DHCP
  267 +#define CONFIG_CMD_ELF
  268 +#define CONFIG_CMD_ERRATA
  269 +#define CONFIG_CMD_GREPENV
  270 +#define CONFIG_CMD_IRQ
  271 +#define CONFIG_CMD_I2C
  272 +#define CONFIG_CMD_MII
  273 +#define CONFIG_CMD_PING
  274 +#define CONFIG_CMD_SETEXPR
  275 +
  276 +#ifdef CONFIG_PCI
  277 +#define CONFIG_CMD_PCI
  278 +#define CONFIG_CMD_NET
  279 +#endif
  280 +
  281 +/*
  282 + * Miscellaneous configurable options
  283 + */
  284 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  285 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  286 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  287 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  288 +#ifdef CONFIG_CMD_KGDB
  289 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  290 +#else
  291 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  292 +#endif
  293 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  294 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  295 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  296 +
  297 +/*
  298 + * For booting Linux, the board info and command line data
  299 + * have to be in the first 64 MB of memory, since this is
  300 + * the maximum mapped by the Linux kernel during initialization.
  301 + */
  302 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  303 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  304 +
  305 +#ifdef CONFIG_CMD_KGDB
  306 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  307 +#endif
  308 +
  309 +/*
  310 + * Environment Configuration
  311 + */
  312 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  313 +#define CONFIG_BOOTFILE "uImage"
  314 +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
  315 +
  316 +/* default location for tftp and bootm */
  317 +#define CONFIG_LOADADDR 1000000
  318 +
  319 +
  320 +#define CONFIG_BAUDRATE 115200
  321 +
  322 +#define CONFIG_HVBOOT \
  323 + "setenv bootargs config-addr=0x60000000; " \
  324 + "bootm 0x01000000 - 0x00f00000"
  325 +
  326 +#ifdef CONFIG_SYS_NO_FLASH
  327 +#ifndef CONFIG_RAMBOOT_PBL
  328 +#define CONFIG_ENV_IS_NOWHERE
  329 +#endif
  330 +#else
  331 +#define CONFIG_FLASH_CFI_DRIVER
  332 +#define CONFIG_SYS_FLASH_CFI
  333 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  334 +#endif
  335 +
  336 +#if defined(CONFIG_SPIFLASH)
  337 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  338 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  339 +#define CONFIG_ENV_SPI_BUS 0
  340 +#define CONFIG_ENV_SPI_CS 0
  341 +#define CONFIG_ENV_SPI_MAX_HZ 10000000
  342 +#define CONFIG_ENV_SPI_MODE 0
  343 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  344 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  345 +#define CONFIG_ENV_SECT_SIZE 0x10000
  346 +#elif defined(CONFIG_SDCARD)
  347 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  348 +#define CONFIG_ENV_IS_IN_MMC
  349 +#define CONFIG_SYS_MMC_ENV_DEV 0
  350 +#define CONFIG_ENV_SIZE 0x2000
  351 +#define CONFIG_ENV_OFFSET (512 * 1658)
  352 +#elif defined(CONFIG_NAND)
  353 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  354 +#define CONFIG_ENV_IS_IN_NAND
  355 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  356 +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  357 +#elif defined(CONFIG_ENV_IS_NOWHERE)
  358 +#define CONFIG_ENV_SIZE 0x2000
  359 +#else
  360 +#define CONFIG_ENV_IS_IN_FLASH
  361 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  362 +#define CONFIG_ENV_SIZE 0x2000
  363 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  364 +#endif
  365 +
  366 +#define CONFIG_SYS_CLK_FREQ 66666666
  367 +#define CONFIG_DDR_CLK_FREQ 133333333
  368 +
  369 +#ifndef __ASSEMBLY__
  370 +unsigned long get_board_sys_clk(void);
  371 +unsigned long get_board_ddr_clk(void);
  372 +#endif
  373 +
  374 +/*
  375 + * DDR Setup
  376 + */
  377 +#define CONFIG_SYS_SPD_BUS_NUM 0
  378 +#define SPD_EEPROM_ADDRESS1 0x52
  379 +#define SPD_EEPROM_ADDRESS2 0x54
  380 +#define SPD_EEPROM_ADDRESS3 0x56
  381 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
  382 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  383 +
  384 +/*
  385 + * IFC Definitions
  386 + */
  387 +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  388 +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  389 + + 0x8000000) | \
  390 + CSPR_PORT_SIZE_16 | \
  391 + CSPR_MSEL_NOR | \
  392 + CSPR_V)
  393 +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
  394 +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  395 + CSPR_PORT_SIZE_16 | \
  396 + CSPR_MSEL_NOR | \
  397 + CSPR_V)
  398 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  399 +/* NOR Flash Timing Params */
  400 +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  401 +
  402 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  403 + FTIM0_NOR_TEADC(0x5) | \
  404 + FTIM0_NOR_TEAHC(0x5))
  405 +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  406 + FTIM1_NOR_TRAD_NOR(0x1A) |\
  407 + FTIM1_NOR_TSEQRAD_NOR(0x13))
  408 +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  409 + FTIM2_NOR_TCH(0x4) | \
  410 + FTIM2_NOR_TWPH(0x0E) | \
  411 + FTIM2_NOR_TWP(0x1c))
  412 +#define CONFIG_SYS_NOR_FTIM3 0x0
  413 +
  414 +#define CONFIG_SYS_FLASH_QUIET_TEST
  415 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  416 +
  417 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  418 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  419 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  420 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  421 +
  422 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  423 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
  424 + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
  425 +
  426 +/* NAND Flash on IFC */
  427 +#define CONFIG_NAND_FSL_IFC
  428 +#define CONFIG_SYS_NAND_MAX_ECCPOS 256
  429 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2
  430 +#define CONFIG_SYS_NAND_BASE 0xff800000
  431 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  432 +
  433 +#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  434 +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  435 + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  436 + | CSPR_MSEL_NAND /* MSEL = NAND */ \
  437 + | CSPR_V)
  438 +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  439 +
  440 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  441 + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  442 + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  443 + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  444 + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  445 + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  446 + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
  447 +
  448 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  449 +
  450 +/* ONFI NAND Flash mode0 Timing Params */
  451 +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  452 + FTIM0_NAND_TWP(0x18) | \
  453 + FTIM0_NAND_TWCHT(0x07) | \
  454 + FTIM0_NAND_TWH(0x0a))
  455 +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  456 + FTIM1_NAND_TWBE(0x39) | \
  457 + FTIM1_NAND_TRR(0x0e) | \
  458 + FTIM1_NAND_TRP(0x18))
  459 +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  460 + FTIM2_NAND_TREH(0x0a) | \
  461 + FTIM2_NAND_TWHRE(0x1e))
  462 +#define CONFIG_SYS_NAND_FTIM3 0x0
  463 +
  464 +#define CONFIG_SYS_NAND_DDR_LAW 11
  465 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  466 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  467 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  468 +#define CONFIG_CMD_NAND
  469 +
  470 +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  471 +
  472 +#if defined(CONFIG_NAND)
  473 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  474 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  475 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  476 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  477 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  478 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  479 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  480 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  481 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  482 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
  483 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  484 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  485 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  486 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  487 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  488 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  489 +#else
  490 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  491 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  492 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  493 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  494 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  495 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  496 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  497 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  498 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  499 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  500 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  501 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  502 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  503 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  504 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  505 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  506 +#endif
  507 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  508 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  509 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  510 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  511 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  512 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  513 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  514 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  515 +
  516 +#if defined(CONFIG_RAMBOOT_PBL)
  517 +#define CONFIG_SYS_RAMBOOT
  518 +#endif
  519 +
  520 +
  521 +/* I2C */
  522 +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
  523 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
  524 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  525 +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
  526 +
  527 +#define I2C_MUX_CH_DEFAULT 0x8
  528 +#define I2C_MUX_CH_VOL_MONITOR 0xa
  529 +#define I2C_MUX_CH_VSC3316_FS 0xc
  530 +#define I2C_MUX_CH_VSC3316_BS 0xd
  531 +
  532 +/* Voltage monitor on channel 2*/
  533 +#define I2C_VOL_MONITOR_ADDR 0x40
  534 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  535 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  536 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  537 +
  538 +/*
  539 + * eSPI - Enhanced SPI
  540 + */
  541 +#define CONFIG_FSL_ESPI
  542 +#define CONFIG_SPI_FLASH
  543 +#define CONFIG_SPI_FLASH_SST
  544 +#define CONFIG_CMD_SF
  545 +#define CONFIG_SF_DEFAULT_SPEED 10000000
  546 +#define CONFIG_SF_DEFAULT_MODE 0
  547 +
  548 +
  549 +/* Qman/Bman */
  550 +#ifndef CONFIG_NOBQFMAN
  551 +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  552 +#define CONFIG_SYS_BMAN_NUM_PORTALS 50
  553 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  554 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  555 +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  556 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50
  557 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  558 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  559 +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  560 +
  561 +#define CONFIG_SYS_DPAA_FMAN
  562 +#define CONFIG_SYS_DPAA_PME
  563 +#define CONFIG_SYS_PMAN
  564 +#define CONFIG_SYS_DPAA_DCE
  565 +#define CONFIG_SYS_DPAA_RMAN
  566 +#define CONFIG_SYS_INTERLAKEN
  567 +
  568 +/* Default address of microcode for the Linux Fman driver */
  569 +#if defined(CONFIG_SPIFLASH)
  570 +/*
  571 + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  572 + * env, so we got 0x110000.
  573 + */
  574 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH
  575 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  576 +#elif defined(CONFIG_SDCARD)
  577 +/*
  578 + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  579 + * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  580 + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  581 + */
  582 +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  583 +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  584 +#elif defined(CONFIG_NAND)
  585 +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  586 +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
  587 +#else
  588 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  589 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  590 +#endif
  591 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  592 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  593 +#endif /* CONFIG_NOBQFMAN */
  594 +
  595 +#ifdef CONFIG_SYS_DPAA_FMAN
  596 +#define CONFIG_FMAN_ENET
  597 +#define CONFIG_PHYLIB_10G
  598 +#define CONFIG_PHY_VITESSE
  599 +#define CONFIG_PHY_CORTINA
  600 +#define CONFIG_CORTINA_FW_ADDR 0xefe00000
  601 +#define CONFIG_CORTINA_FW_LENGTH 0x40000
  602 +#define CONFIG_PHY_TERANETICS
  603 +#define SGMII_PHY_ADDR1 0x0
  604 +#define SGMII_PHY_ADDR2 0x1
  605 +#define SGMII_PHY_ADDR3 0x2
  606 +#define SGMII_PHY_ADDR4 0x3
  607 +#define SGMII_PHY_ADDR5 0x4
  608 +#define SGMII_PHY_ADDR6 0x5
  609 +#define SGMII_PHY_ADDR7 0x6
  610 +#define SGMII_PHY_ADDR8 0x7
  611 +#define FM1_10GEC1_PHY_ADDR 0x10
  612 +#define FM1_10GEC2_PHY_ADDR 0x11
  613 +#define FM2_10GEC1_PHY_ADDR 0x12
  614 +#define FM2_10GEC2_PHY_ADDR 0x13
  615 +#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
  616 +#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
  617 +#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
  618 +#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
  619 +#endif
  620 +
  621 +
  622 +/* SATA */
  623 +#ifdef CONFIG_FSL_SATA_V2
  624 +#define CONFIG_LIBATA
  625 +#define CONFIG_FSL_SATA
  626 +
  627 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  628 +#define CONFIG_SATA1
  629 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  630 +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  631 +#define CONFIG_SATA2
  632 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  633 +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  634 +
  635 +#define CONFIG_LBA48
  636 +#define CONFIG_CMD_SATA
  637 +#define CONFIG_DOS_PARTITION
  638 +#define CONFIG_CMD_EXT2
  639 +#endif
  640 +
  641 +#ifdef CONFIG_FMAN_ENET
  642 +#define CONFIG_MII /* MII PHY management */
  643 +#define CONFIG_ETHPRIME "FM1@DTSEC1"
  644 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  645 +#endif
  646 +
  647 +/*
  648 +* USB
  649 +*/
  650 +#define CONFIG_CMD_USB
  651 +#define CONFIG_USB_STORAGE
  652 +#define CONFIG_USB_EHCI
  653 +#define CONFIG_USB_EHCI_FSL
  654 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  655 +#define CONFIG_CMD_EXT2
  656 +#define CONFIG_HAS_FSL_DR_USB
  657 +
  658 +#define CONFIG_MMC
  659 +
  660 +#ifdef CONFIG_MMC
  661 +#define CONFIG_FSL_ESDHC
  662 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  663 +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  664 +#define CONFIG_CMD_MMC
  665 +#define CONFIG_GENERIC_MMC
  666 +#define CONFIG_CMD_EXT2
  667 +#define CONFIG_CMD_FAT
  668 +#define CONFIG_DOS_PARTITION
  669 +#endif
  670 +
  671 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  672 +
  673 +#define __USB_PHY_TYPE utmi
  674 +
  675 +/*
  676 + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
  677 + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
  678 + * interleaving. It can be cacheline, page, bank, superbank.
  679 + * See doc/README.fsl-ddr for details.
  680 + */
  681 +#define CTRL_INTLV_PREFERED 3way_4KB
  682 +
  683 +#define CONFIG_EXTRA_ENV_SETTINGS \
  684 + "hwconfig=fsl_ddr:" \
  685 + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  686 + "bank_intlv=auto;" \
  687 + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  688 + "netdev=eth0\0" \
  689 + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  690 + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  691 + "tftpflash=tftpboot $loadaddr $uboot && " \
  692 + "protect off $ubootaddr +$filesize && " \
  693 + "erase $ubootaddr +$filesize && " \
  694 + "cp.b $loadaddr $ubootaddr $filesize && " \
  695 + "protect on $ubootaddr +$filesize && " \
  696 + "cmp.b $loadaddr $ubootaddr $filesize\0" \
  697 + "consoledev=ttyS0\0" \
  698 + "ramdiskaddr=2000000\0" \
  699 + "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
  700 + "fdtaddr=c00000\0" \
  701 + "fdtfile=t4240rdb/t4240rdb.dtb\0" \
  702 + "bdev=sda3\0"
  703 +
  704 +#define CONFIG_HVBOOT \
  705 + "setenv bootargs config-addr=0x60000000; " \
  706 + "bootm 0x01000000 - 0x00f00000"
  707 +
  708 +#define CONFIG_LINUX \
  709 + "setenv bootargs root=/dev/ram rw " \
  710 + "console=$consoledev,$baudrate $othbootargs;" \
  711 + "setenv ramdiskaddr 0x02000000;" \
  712 + "setenv fdtaddr 0x00c00000;" \
  713 + "setenv loadaddr 0x1000000;" \
  714 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  715 +
  716 +#define CONFIG_HDBOOT \
  717 + "setenv bootargs root=/dev/$bdev rw " \
  718 + "console=$consoledev,$baudrate $othbootargs;" \
  719 + "tftp $loadaddr $bootfile;" \
  720 + "tftp $fdtaddr $fdtfile;" \
  721 + "bootm $loadaddr - $fdtaddr"
  722 +
  723 +#define CONFIG_NFSBOOTCOMMAND \
  724 + "setenv bootargs root=/dev/nfs rw " \
  725 + "nfsroot=$serverip:$rootpath " \
  726 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  727 + "console=$consoledev,$baudrate $othbootargs;" \
  728 + "tftp $loadaddr $bootfile;" \
  729 + "tftp $fdtaddr $fdtfile;" \
  730 + "bootm $loadaddr - $fdtaddr"
  731 +
  732 +#define CONFIG_RAMBOOTCOMMAND \
  733 + "setenv bootargs root=/dev/ram rw " \
  734 + "console=$consoledev,$baudrate $othbootargs;" \
  735 + "tftp $ramdiskaddr $ramdiskfile;" \
  736 + "tftp $loadaddr $bootfile;" \
  737 + "tftp $fdtaddr $fdtfile;" \
  738 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  739 +
  740 +#define CONFIG_BOOTCOMMAND CONFIG_LINUX
  741 +
  742 +#include <asm/fsl_secure_boot.h>
  743 +
  744 +#ifdef CONFIG_SECURE_BOOT
  745 +/* Secure Boot target was not getting build for T4240 because of
  746 + * increased binary size. So the size is being reduced by removing USB
  747 + * which is anyways not used in Secure Environment.
  748 + */
  749 +#undef CONFIG_CMD_USB
  750 +#endif
  751 +
  752 +#endif /* __CONFIG_H */