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Commit 0c01c3e876c0db59b4075a4a7550020f0ea25981

Authored by Erik van Luijk
Committed by Andreas Bießmann
1 parent 8d77576371
Exists in v2017.01-smarct4x and in 33 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: at91: mpddr: allow multiple DDR controllers 

The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

Showing 14 changed files with 34 additions and 36 deletions Side-by-side Diff

arch/arm/mach-at91/include/mach/atmel_mpddrc.h
Diff comments   View file @ 0c01c3e
... ... @@ -23,8 +23,10 @@
23 23 u32 md;
24 24 };
25 25  
26   -int ddr2_init(const unsigned int ram_address,
27   - const struct atmel_mpddr *mpddr);
  26 +
  27 +int ddr2_init(const unsigned int base,
  28 + const unsigned int ram_address,
  29 + const struct atmel_mpddr *mpddr);
28 30  
29 31 /* Bit field in mode register */
30 32 #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0
arch/arm/mach-at91/mpddrc.c
Diff comments   View file @ 0c01c3e
... ... @@ -9,10 +9,10 @@
9 9 #include <asm/io.h>
10 10 #include <asm/arch/atmel_mpddrc.h>
11 11  
12   -static inline void atmel_mpddr_op(int mode, u32 ram_address)
  12 +static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
  13 + int mode,
  14 + u32 ram_address)
13 15 {
14   - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
15   -
16 16 writel(mode, &mpddr->mr);
17 17 writel(0, ram_address);
18 18 }
19 19  
... ... @@ -27,10 +27,13 @@
27 27 return 1;
28 28 }
29 29  
30   -int ddr2_init(const unsigned int ram_address,
  30 +
  31 +int ddr2_init(const unsigned int base,
  32 + const unsigned int ram_address,
31 33 const struct atmel_mpddr *mpddr_value)
32 34 {
33   - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  35 + const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
  36 +
34 37 u32 ba_off, cr;
35 38  
36 39 /* Compute bank offset according to NC in configuration register */
37 40  
38 41  
39 42  
40 43  
41 44  
... ... @@ -52,30 +55,30 @@
52 55 writel(mpddr_value->tpr2, &mpddr->tpr2);
53 56  
54 57 /* Issue a NOP command */
55   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  58 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
56 59  
57 60 /* A 200 us is provided to precede any signal toggle */
58 61 udelay(200);
59 62  
60 63 /* Issue a NOP command */
61   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
  64 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
62 65  
63 66 /* Issue an all banks precharge command */
64   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  67 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
65 68  
66 69 /* Issue an extended mode register set(EMRS2) to choose operation */
67   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  70 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
68 71 ram_address + (0x2 << ba_off));
69 72  
70 73 /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
71   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  74 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
72 75 ram_address + (0x3 << ba_off));
73 76  
74 77 /*
75 78 * Issue an extended mode register set(EMRS1) to enable DLL and
76 79 * program D.I.C (output driver impedance control)
77 80 */
78   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  81 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
79 82 ram_address + (0x1 << ba_off));
80 83  
81 84 /* Enable DLL reset */
82 85  
83 86  
84 87  
... ... @@ -83,21 +86,21 @@
83 86 writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
84 87  
85 88 /* A mode register set(MRS) cycle is issued to reset DLL */
86   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  89 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
87 90  
88 91 /* Issue an all banks precharge command */
89   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
  92 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
90 93  
91 94 /* Two auto-refresh (CBR) cycles are provided */
92   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
93   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  95 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
  96 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
94 97  
95 98 /* Disable DLL reset */
96 99 cr = readl(&mpddr->cr);
97 100 writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
98 101  
99 102 /* A mode register set (MRS) cycle is issued to disable DLL reset */
100   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
  103 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
101 104  
102 105 /* Set OCD calibration in default state */
103 106 cr = readl(&mpddr->cr);
... ... @@ -107,7 +110,7 @@
107 110 * An extended mode register set (EMRS1) cycle is issued
108 111 * to OCD default value
109 112 */
110   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  113 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
111 114 ram_address + (0x1 << ba_off));
112 115  
113 116 /* OCD calibration mode exit */
114 117  
... ... @@ -118,11 +121,11 @@
118 121 * An extended mode register set (EMRS1) cycle is issued
119 122 * to enable OCD exit
120 123 */
121   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
  124 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
122 125 ram_address + (0x1 << ba_off));
123 126  
124 127 /* A nornal mode command is provided */
125   - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
  128 + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
126 129  
127 130 /* Perform a write access to any DDR2-SDRAM address */
128 131 writel(0, ram_address);
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
Diff comments   View file @ 0c01c3e
... ... @@ -147,7 +147,7 @@
147 147 writel(csa, &mat->ebicsa);
148 148  
149 149 /* DDRAM2 Controller initialize */
150   - ddr2_init(ATMEL_BASE_CS6, &ddr2);
  150 + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
151 151 }
152 152 #endif
153 153  
board/atmel/at91sam9n12ek/at91sam9n12ek.c
Diff comments   View file @ 0c01c3e
... ... @@ -327,7 +327,7 @@
327 327 writel(csa, &matrix->ebicsa);
328 328  
329 329 /* DDRAM2 Controller initialize */
330   - ddr2_init(ATMEL_BASE_CS1, &ddr2);
  330 + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
331 331 }
332 332 #endif
board/atmel/at91sam9x5ek/at91sam9x5ek.c
Diff comments   View file @ 0c01c3e
... ... @@ -364,7 +364,7 @@
364 364 writel(csa, &matrix->ebicsa);
365 365  
366 366 /* DDRAM2 Controller initialize */
367   - ddr2_init(ATMEL_BASE_CS1, &ddr2);
  367 + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
368 368 }
369 369 #endif
board/atmel/sama5d3_xplained/sama5d3_xplained.c
Diff comments   View file @ 0c01c3e
... ... @@ -194,7 +194,7 @@
194 194 writel(0x4, &pmc->scer);
195 195  
196 196 /* DDRAM2 Controller initialize */
197   - ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
  197 + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
198 198 }
199 199  
200 200 void at91_pmc_init(void)
board/atmel/sama5d3xek/sama5d3xek.c
Diff comments   View file @ 0c01c3e
... ... @@ -433,7 +433,7 @@
433 433 writel(0x4, &pmc->scer);
434 434  
435 435 /* DDRAM2 Controller initialize */
436   - ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
  436 + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
437 437 }
438 438  
439 439 void at91_pmc_init(void)
board/atmel/sama5d4_xplained/sama5d4_xplained.c
Diff comments   View file @ 0c01c3e
... ... @@ -393,7 +393,7 @@
393 393 writel(0x4, &pmc->scer);
394 394  
395 395 /* DDRAM2 Controller initialize */
396   - ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
  396 + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
397 397 }
398 398  
399 399 void at91_pmc_init(void)
board/atmel/sama5d4ek/sama5d4ek.c
Diff comments   View file @ 0c01c3e
... ... @@ -389,7 +389,7 @@
389 389 writel(0x4, &pmc->scer);
390 390  
391 391 /* DDRAM2 Controller initialize */
392   - ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
  392 + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
393 393 }
394 394  
395 395 void at91_pmc_init(void)
board/siemens/corvus/board.c
Diff comments   View file @ 0c01c3e
... ... @@ -160,7 +160,7 @@
160 160 writel(csa, &mat->ebicsa);
161 161  
162 162 /* DDRAM2 Controller initialize */
163   - ddr2_init(ATMEL_BASE_CS6, &ddr2);
  163 + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
164 164 }
165 165 #endif
166 166  
include/configs/at91sam9m10g45ek.h
Diff comments   View file @ 0c01c3e
... ... @@ -251,6 +251,5 @@
251 251 #define CONFIG_SYS_MCKR 0x1301
252 252 #define CONFIG_SYS_MCKR_CSS 0x1302
253 253  
254   -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
255 254 #endif
include/configs/at91sam9n12ek.h
Diff comments   View file @ 0c01c3e
... ... @@ -259,8 +259,6 @@
259 259 #define CONFIG_SYS_MCKR 0x1301
260 260 #define CONFIG_SYS_MCKR_CSS 0x1302
261 261  
262   -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
263   -
264 262 #ifdef CONFIG_SYS_USE_MMC
265 263 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
266 264 #define CONFIG_SPL_MMC_SUPPORT
include/configs/at91sam9x5ek.h
Diff comments   View file @ 0c01c3e
... ... @@ -261,8 +261,6 @@
261 261 #define CONFIG_SYS_MCKR 0x1301
262 262 #define CONFIG_SYS_MCKR_CSS 0x1302
263 263  
264   -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC
265   -
266 264 #ifdef CONFIG_SYS_USE_MMC
267 265 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
268 266 #define CONFIG_SPL_MMC_SUPPORT
include/configs/corvus.h
Diff comments   View file @ 0c01c3e
... ... @@ -193,7 +193,5 @@
193 193 #define CONFIG_SYS_MCKR 0x1301
194 194 #define CONFIG_SYS_MCKR_CSS 0x1302
195 195  
196   -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
197   -
198 196 #endif