Eric Lee / smarc-uboot

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Commit 0c8721a466b5e0eca7e7fbe1007777fa82100541

Authored by Wolfgang Denk
1 parent a6e6cf0036
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Cleanup (PPC4xx is AMCC now)

Showing 80 changed files with 191 additions and 187 deletions Side-by-side Diff

... ... @@ -2,6 +2,8 @@
2 2 Changes for U-Boot 1.1.4:
3 3 ======================================================================
4 4  
  5 +* Cleanup (PPC4xx is AMCC now)
  6 +
5 7 * esd CPCI2DP board added
6 8 Patch by Matthias Fuchs, 22 Sep 2005
7 9  
... ... @@ -340,7 +340,7 @@
340 340  
341 341 N: Stefan Roese
342 342 E: stefan.roese@esd-electronics.com
343   -D: IBM PPC401/403/405GP Support; Windows environment support
  343 +D: AMCC PPC401/403/405GP Support; Windows environment support
344 344  
345 345 N: Erwin Rol
346 346 E: erwin@muffin.org
... ... @@ -356,7 +356,7 @@
356 356  
357 357 N: Travis B. Sawyer
358 358 E: travis.sawyer@sandburst.com
359   -D: Support for IBM PPC440GX, XES XPedite1000 440GX PrPMC board. IBM 440gx Ref Platform (Ocotea)
  359 +D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea)
360 360  
361 361 N: Paolo Scaffardi
362 362 E: arsenio@tin.it
... ... @@ -145,7 +145,7 @@
145 145 - mpc85xx Files specific to Freescale MPC85xx CPUs
146 146 - nios Files specific to Altera NIOS CPUs
147 147 - nios2 Files specific to Altera Nios-II CPUs
148   - - ppc4xx Files specific to IBM PowerPC 4xx CPUs
  148 + - ppc4xx Files specific to AMCC PowerPC 4xx CPUs
149 149 - pxa Files specific to Intel XScale PXA CPUs
150 150 - s3c44b0 Files specific to Samsung S3C44B0 CPUs
151 151 - sa1100 Files specific to Intel StrongARM SA1100 CPUs
... ... @@ -497,7 +497,7 @@
497 497 - Console UART Number:
498 498 CONFIG_UART1_CONSOLE
499 499  
500   - IBM PPC4xx only.
  500 + AMCC PPC4xx only.
501 501 If defined internal UART1 (and not UART0) is used
502 502 as default U-Boot console.
503 503  
board/MAI/AmigaOneG3SE/ps2kbd.c
Diff comments   View file @ 0c8721a
... ... @@ -656,7 +656,7 @@
656 656 | KBD_MODE_DISABLE_MOUSE
657 657 | KBD_MODE_KCC);
658 658  
659   - /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
  659 + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
660 660 kbd_write_command_w(KBD_CCMD_READ_MODE);
661 661 if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
662 662 /*
board/amcc/ocotea/config.mk
Diff comments   View file @ 0c8721a
... ... @@ -22,7 +22,7 @@
22 22 #
23 23  
24 24 #
25   -# IBM 440GX Reference Platform (Ocotea) board
  25 +# AMCC 440GX Reference Platform (Ocotea) board
26 26 #
27 27  
28 28 #TEXT_BASE = 0xFFFE0000
board/dave/PPChameleonEVB/PPChameleonEVB.c
Diff comments   View file @ 0c8721a
... ... @@ -279,10 +279,10 @@
279 279 case 1:
280 280 switch (pvr) {
281 281 case PVR_405EP_RB:
282   - sprintf (info, " IBM PowerPC 405EP Rev. B");
  282 + sprintf (info, " AMCC PowerPC 405EP Rev. B");
283 283 break;
284 284 default:
285   - sprintf (info, " IBM PowerPC 405EP Rev. <unknown>");
  285 + sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
286 286 break;
287 287 }
288 288 return;
... ... @@ -26,10 +26,10 @@
26 26 #include "eric.h"
27 27 #include <asm/processor.h>
28 28  
29   -#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
30   -#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
31   -#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
32   -#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
  29 +#define PPC405GP_GPIO0_OR 0xef600700 /* GPIO Output */
  30 +#define PPC405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
  31 +#define PPC405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
  32 +#define PPC405GP_GPIO0_IR 0xef60071c /* GPIO Input */
33 33  
34 34 int board_early_init_f (void)
35 35 {
... ... @@ -50,7 +50,7 @@
50 50 | IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
51 51 | IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
52 52 | -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
53   - | IBM405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in IBM405GP_GPIO0_OR,
  53 + | PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
54 54 | else tristate)
55 55 | Note for ERIC board:
56 56 | An interrupt taken for the HOST (IRQ 28) indicates that
... ... @@ -70,8 +70,8 @@
70 70  
71 71 mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
72 72  
73   - out32 (IBM405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
74   - out32 (IBM405GP_GPIO0_TCR, 0x7E400000);
  73 + out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
  74 + out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
75 75  
76 76 return 0;
77 77 }
board/esd/ocrtc/cmd_ocrtc.c
Diff comments   View file @ 0c8721a
... ... @@ -29,8 +29,8 @@
29 29  
30 30 #if (CONFIG_COMMANDS & CFG_CMD_BSP)
31 31  
32   -#define IBM_VENDOR_ID 0x1014
33   -#define PPC405_DEVICE_ID 0x0156
  32 +#define AMCC_VENDOR_ID 0x1014
  33 +#define PPC405_DEVICE_ID 0x0156
34 34  
35 35  
36 36 /*
... ... @@ -43,7 +43,7 @@
43 43 u32 addr;
44 44  
45 45 while (bdf >= 0) {
46   - if ((bdf = pci_find_device(IBM_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
  46 + if ((bdf = pci_find_device(AMCC_VENDOR_ID, PPC405_DEVICE_ID, idx++)) < 0) {
47 47 break;
48 48 }
49 49 printf("Found device nr %d at %x!\n", idx-1, bdf);
board/mpl/common/kbd.c
Diff comments   View file @ 0c8721a
... ... @@ -613,7 +613,7 @@
613 613 | KBD_MODE_DISABLE_MOUSE
614 614 | KBD_MODE_KCC);
615 615  
616   - /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
  616 + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
617 617 kbd_write_command_w(KBD_CCMD_READ_MODE);
618 618 if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
619 619 /*
board/mpl/common/pci_parts.h
Diff comments   View file @ 0c8721a
... ... @@ -137,7 +137,7 @@
137 137 { } /* end of device table */
138 138 };
139 139 /* PPC405 Dummy only used to prevent autosetup on this host bridge */
140   -static struct pci_pip405_config_entry ibm405_dummy[] = {
  140 +static struct pci_pip405_config_entry ppc405_dummy[] = {
141 141 { } /* end of device table */
142 142 };
143 143  
... ... @@ -150,7 +150,7 @@
150 150 PCI_DEVICE_ID_IBM_405GP,
151 151 PCI_ANY_ID,
152 152 PCI_ANY_ID, PCI_ANY_ID, 0,
153   - pci_pip405_write_regs, {(unsigned long) ibm405_dummy}},
  153 + pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
154 154  
155 155 {PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
156 156 PCI_DEVICE_ID_INTEL_82371AB_0,
... ... @@ -77,17 +77,17 @@
77 77 dest = (unsigned short *)daddr;
78 78  
79 79 /* Get DCR output register */
80   - grego = in32(IBM405GP_GPIO0_OR);
  80 + grego = in32(PPC405GP_GPIO0_OR);
81 81  
82 82 /* Reset FPGA */
83 83 grego &= ~GPIO_XCV_PROG; /* PROG line low */
84   - out32(IBM405GP_GPIO0_OR, grego);
  84 + out32(PPC405GP_GPIO0_OR, grego);
85 85  
86 86 /* Setup timeout timer */
87 87 start = get_timer(0);
88 88  
89 89 /* Wait for FPGA init line */
90   - while(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
  90 + while(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT) { /* Wait INIT line low */
91 91 /* Check for timeout - 100us max, so use 3ms */
92 92 if (get_timer(start) > 3) {
93 93 printf(" failed to start init.\n");
94 94  
... ... @@ -100,10 +100,10 @@
100 100  
101 101 /* Unreset FPGA */
102 102 grego |= GPIO_XCV_PROG; /* PROG line high */
103   - out32(IBM405GP_GPIO0_OR, grego);
  103 + out32(PPC405GP_GPIO0_OR, grego);
104 104  
105 105 /* Wait for FPGA end of init period . */
106   - while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
  106 + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_INIT)) { /* Wait for INIT hi */
107 107  
108 108 /* Check for timeout */
109 109 if (get_timer(start) > 3) {
... ... @@ -112,7 +112,7 @@
112 112  
113 113 /* Reset FPGA */
114 114 grego &= ~GPIO_XCV_PROG; /* PROG line low */
115   - out32(IBM405GP_GPIO0_OR, grego);
  115 + out32(PPC405GP_GPIO0_OR, grego);
116 116  
117 117 goto done;
118 118 }
119 119  
120 120  
121 121  
122 122  
... ... @@ -127,18 +127,18 @@
127 127 mtdcr(CPC0_CR0, greg); /* ... just do it */
128 128  
129 129 /* turn on open drain for CNFG */
130   - greg = in32(IBM405GP_GPIO0_ODR); /* get open drain register */
  130 + greg = in32(PPC405GP_GPIO0_ODR); /* get open drain register */
131 131 greg |= cnfg; /* CNFG open drain */
132   - out32(IBM405GP_GPIO0_ODR, greg); /* .. just do it */
  132 + out32(PPC405GP_GPIO0_ODR, greg); /* .. just do it */
133 133  
134 134 /* Turn output enable on for CNFG */
135   - greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
  135 + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
136 136 greg |= cnfg; /* CNFG tristate inactive */
137   - out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
  137 + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
138 138  
139 139 /* Setup FPGA for programming */
140 140 grego &= ~cnfg; /* CONFIG line low */
141   - out32(IBM405GP_GPIO0_OR, grego);
  141 + out32(PPC405GP_GPIO0_OR, grego);
142 142  
143 143 /*
144 144 * Program the FPGA
145 145  
146 146  
... ... @@ -149,12 +149,12 @@
149 149  
150 150 /* Done programming */
151 151 grego |= cnfg; /* CONFIG line high */
152   - out32(IBM405GP_GPIO0_OR, grego);
  152 + out32(PPC405GP_GPIO0_OR, grego);
153 153  
154 154 /* Turn output enable OFF for CNFG */
155   - greg = in32(IBM405GP_GPIO0_TCR); /* get tristate register */
  155 + greg = in32(PPC405GP_GPIO0_TCR); /* get tristate register */
156 156 greg &= ~cnfg; /* CNFG tristate inactive */
157   - out32(IBM405GP_GPIO0_TCR, greg); /* ... just do it */
  157 + out32(PPC405GP_GPIO0_TCR, greg); /* ... just do it */
158 158  
159 159 /* Toggle IRQ/GPIO */
160 160 greg = mfdcr(CPC0_CR0); /* get chip ctrl register */
... ... @@ -180,7 +180,7 @@
180 180 start = get_timer(0);
181 181  
182 182 /* Wait for FPGA end of programming period . */
183   - while(!(in32(IBM405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
  183 + while(!(in32(PPC405GP_GPIO0_IR) & GPIO_XCV_DONE)) { /* Test DONE low */
184 184  
185 185 /* Check for timeout */
186 186 if (get_timer(start) > 3) {
... ... @@ -189,7 +189,7 @@
189 189  
190 190 /* Reset FPGA */
191 191 grego &= ~GPIO_XCV_PROG; /* PROG line low */
192   - out32(IBM405GP_GPIO0_OR, grego);
  192 + out32(PPC405GP_GPIO0_OR, grego);
193 193  
194 194 goto done;
195 195 }
... ... @@ -47,9 +47,9 @@
47 47 /*
48 48 * Setup GPIO pins - reset devices.
49 49 */
50   - out32 (IBM405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
51   - out32 (IBM405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
52   - out32 (IBM405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
  50 + out32 (PPC405GP_GPIO0_ODR, 0x10000000); /* one open drain pin */
  51 + out32 (PPC405GP_GPIO0_OR, 0x3E000000); /* set output pins to default */
  52 + out32 (PPC405GP_GPIO0_TCR, 0x7f800000); /* setup for output */
53 53  
54 54 /*
55 55 * IRQ 0-15 405GP internally generated; active high; level sensitive
... ... @@ -78,9 +78,9 @@
78 78 /*
79 79 * Setup GPIO pins
80 80 */
81   - out32 (IBM405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
82   - out32 (IBM405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
83   - out32 (IBM405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
  81 + out32 (PPC405GP_GPIO0_ODR, 0x01800000); /* XCV Done Open Drain */
  82 + out32 (PPC405GP_GPIO0_OR, 0x03800000); /* set out pins to default */
  83 + out32 (PPC405GP_GPIO0_TCR, 0x66C00000); /* setup for output */
84 84  
85 85 /*
86 86 * IRQ 0-15 405GP internally generated; active high; level sensitive
87 87  
... ... @@ -238,14 +238,14 @@
238 238 #if defined(CONFIG_W7OLMG)
239 239 unsigned long greg; /* GPIO Register */
240 240  
241   - greg = in32 (IBM405GP_GPIO0_OR);
  241 + greg = in32 (PPC405GP_GPIO0_OR);
242 242  
243 243 /*
244 244 * XXX - Unreset devices - this should be moved into VxWorks driver code
245 245 */
246 246 greg |= 0x41800000L; /* SAM, PHY, Galileo */
247 247  
248   - out32 (IBM405GP_GPIO0_OR, greg); /* set output pins to default */
  248 + out32 (PPC405GP_GPIO0_OR, greg); /* set output pins to default */
249 249 #endif /* CONFIG_W7OLMG */
250 250  
251 251 /*
... ... @@ -25,13 +25,13 @@
25 25 #define _W7O_H_
26 26 #include <config.h>
27 27  
28   -/* IBM 405GP PowerPC GPIO registers */
29   -#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
30   -#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
31   -#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
32   -#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
  28 +/* AMCC 405GP PowerPC GPIO registers */
  29 +#define PPC405GP_GPIO0_OR 0xef600700L /* GPIO Output */
  30 +#define PPC405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
  31 +#define PPC405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
  32 +#define PPC405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
33 33  
34   -/* IBM 405GP DCRs */
  34 +/* AMCC 405GP DCRs */
35 35 #define CPC0_CR0 0xb1 /* Chip control register 0 */
36 36  
37 37 /* LMG FPGA <=> CPU GPIO signals */
... ... @@ -22,7 +22,7 @@
22 22 */
23 23  
24 24 /*
25   - * IBM 4XX DCR Functions
  25 + * AMCC 4XX DCR Functions
26 26 */
27 27  
28 28 #include <common.h>
29 29  
30 30  
31 31  
32 32  
33 33  
34 34  
35 35  
36 36  
37 37  
38 38  
39 39  
40 40  
41 41  
42 42  
43 43  
44 44  
... ... @@ -31,89 +31,91 @@
31 31  
32 32 #if defined(CONFIG_4xx) && (CONFIG_COMMANDS & CFG_CMD_SETGETDCR)
33 33  
34   -/* ======================================================================
35   - * Interpreter command to retrieve an IBM PPC 4xx Device Control Register
36   - * ======================================================================
  34 +/* =======================================================================
  35 + * Interpreter command to retrieve an AMCC PPC 4xx Device Control Register
  36 + * =======================================================================
37 37 */
38 38 int do_getdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
39 39 {
40   - unsigned short dcrn; /* Device Control Register Num */
41   - unsigned long value; /* DCR's value */
  40 + unsigned short dcrn; /* Device Control Register Num */
  41 + unsigned long value; /* DCR's value */
42 42  
43   - unsigned long get_dcr(unsigned short);
  43 + unsigned long get_dcr (unsigned short);
44 44  
45   - /* Validate arguments */
46   - if (argc < 2) {
47   - printf("Usage:\n%s\n", cmdtp->usage);
48   - return 1;
49   - }
  45 + /* Validate arguments */
  46 + if (argc < 2) {
  47 + printf ("Usage:\n%s\n", cmdtp->usage);
  48 + return 1;
  49 + }
50 50  
51   - /* Get a DCR */
52   - dcrn = (unsigned short)simple_strtoul(argv[ 1 ], NULL, 16);
53   - value = get_dcr(dcrn);
  51 + /* Get a DCR */
  52 + dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
  53 + value = get_dcr (dcrn);
54 54  
55   - printf("%04x: %08lx\n", dcrn, value);
  55 + printf ("%04x: %08lx\n", dcrn, value);
56 56  
57   - return 0;
58   -} /* do_getdcr */
  57 + return 0;
  58 +}
59 59  
60 60  
61 61 /* ======================================================================
62   - * Interpreter command to set an IBM PPC 4xx Device Control Register
  62 + * Interpreter command to set an AMCC PPC 4xx Device Control Register
63 63 * ======================================================================
64 64 */
65   -int do_setdcr ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  65 +int do_setdcr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
66 66 {
67   - unsigned long get_dcr(unsigned short );
68   - unsigned long set_dcr(unsigned short , unsigned long );
69   - unsigned short dcrn; /* Device Control Register Num */
70   - unsigned long value;
71   - /* DCR's value */
72   - int nbytes;
73   - extern char console_buffer[];
  67 + unsigned long get_dcr (unsigned short);
  68 + unsigned long set_dcr (unsigned short, unsigned long);
  69 + unsigned short dcrn; /* Device Control Register Num */
  70 + unsigned long value;
74 71  
75   - /* Validate arguments */
76   - if (argc < 2) {
77   - printf("Usage:\n%s\n", cmdtp->usage);
78   - return 1;
79   - }
  72 + /* DCR's value */
  73 + int nbytes;
  74 + extern char console_buffer[];
80 75  
81   - /* Set a DCR */
82   - dcrn = (unsigned short)simple_strtoul(argv[1], NULL, 16);
83   - do {
84   - value = get_dcr(dcrn);
85   - printf("%04x: %08lx", dcrn, value);
86   - nbytes = readline(" ? ");
87   - if (nbytes == 0) {
88   - /*
89   - * <CR> pressed as only input, don't modify current
90   - * location and exit command.
91   - */
92   - nbytes = 1;
93   - return 0;
94   - } else {
95   - unsigned long i;
96   - char *endp;
97   - i = simple_strtoul(console_buffer, &endp, 16);
98   - nbytes = endp - console_buffer;
99   - if (nbytes)
100   - set_dcr(dcrn, i);
  76 + /* Validate arguments */
  77 + if (argc < 2) {
  78 + printf ("Usage:\n%s\n", cmdtp->usage);
  79 + return 1;
101 80 }
102   - } while (nbytes);
103 81  
104   - return 0;
105   -} /* do_setdcr */
  82 + /* Set a DCR */
  83 + dcrn = (unsigned short) simple_strtoul (argv[1], NULL, 16);
  84 + do {
  85 + value = get_dcr (dcrn);
  86 + printf ("%04x: %08lx", dcrn, value);
  87 + nbytes = readline (" ? ");
  88 + if (nbytes == 0) {
  89 + /*
  90 + * <CR> pressed as only input, don't modify current
  91 + * location and exit command.
  92 + */
  93 + nbytes = 1;
  94 + return 0;
  95 + } else {
  96 + unsigned long i;
  97 + char *endp;
106 98  
  99 + i = simple_strtoul (console_buffer, &endp, 16);
  100 + nbytes = endp - console_buffer;
  101 + if (nbytes)
  102 + set_dcr (dcrn, i);
  103 + }
  104 + } while (nbytes);
  105 +
  106 + return 0;
  107 +}
  108 +
107 109 /***************************************************/
108 110  
109 111 U_BOOT_CMD(
110 112 getdcr, 2, 1, do_getdcr,
111   - "getdcr - Get an IBM PPC 4xx DCR's value\n",
  113 + "getdcr - Get an AMCC PPC 4xx DCR's value\n",
112 114 "dcrn - return a DCR's value.\n"
113 115 );
114 116 U_BOOT_CMD(
115 117 setdcr, 2, 1, do_setdcr,
116   - "setdcr - Set an IBM PPC 4xx DCR's value\n",
  118 + "setdcr - Set an AMCC PPC 4xx DCR's value\n",
117 119 "dcrn - set a DCR's value.\n"
118 120 );
119 121  
cpu/ppc4xx/4xx_enet.c
Diff comments   View file @ 0c8721a
... ... @@ -90,7 +90,7 @@
90 90 #include "vecnum.h"
91 91  
92 92 /*
93   - * Only compile for platform with IBM/AMCC EMAC ethernet controller and
  93 + * Only compile for platform with AMCC EMAC ethernet controller and
94 94 * network support enabled.
95 95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
96 96 */
cpu/ppc4xx/bedbug_405.c
Diff comments   View file @ 0c8721a
... ... @@ -25,7 +25,7 @@
25 25  
26 26  
27 27 /* ======================================================================
28   - * Initialize the global bug_ctx structure for the IBM PPC405. Clear all
  28 + * Initialize the global bug_ctx structure for the AMCC PPC405. Clear all
29 29 * of the breakpoints.
30 30 * ====================================================================== */
31 31  
... ... @@ -320,7 +320,7 @@
320 320 #endif
321 321  
322 322 #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
323   -#error "External serial clock not supported on IBM PPC405EP!"
  323 +#error "External serial clock not supported on AMCC PPC405EP!"
324 324 #endif
325 325  
326 326 #define UART_RBR 0x00
cpu/ppc4xx/spd_sdram.c
Diff comments   View file @ 0c8721a
... ... @@ -14,7 +14,7 @@
14 14 *
15 15 * (C) Copyright 2002
16 16 * Jun Gu, Artesyn Technology, jung@artesyncp.com
17   - * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
  17 + * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
18 18 *
19 19 * (C) Copyright 2005
20 20 * Stefan Roese, DENX Software Engineering, sr@denx.de.
... ... @@ -108,7 +108,7 @@
108 108 * This function is reading data from the DIMM module EEPROM over the SPD bus
109 109 * and uses that to program the sdram controller.
110 110 *
111   - * This works on boards that has the same schematics that the IBM walnut has.
  111 + * This works on boards that has the same schematics that the AMCC walnut has.
112 112 *
113 113 * Input: null for default I2C spd functions or a pointer to a custom function
114 114 * returning spd_data.
... ... @@ -696,7 +696,7 @@
696 696 * This function is reading data from the DIMM module EEPROM over the SPD bus
697 697 * and uses that to program the sdram controller.
698 698 *
699   - * This works on boards that has the same schematics that the IBM walnut has.
  699 + * This works on boards that has the same schematics that the AMCC walnut has.
700 700 *
701 701 * BUG: Don't handle ECC memory
702 702 * BUG: A few values in the TR register is currently hardcoded
... ... @@ -42,7 +42,7 @@
42 42 /* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
43 43 /*------------------------------------------------------------------------------- */
44 44  
45   -/* U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
  45 +/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
46 46 *
47 47 *
48 48 * The processor starts at 0xfffffffc and the code is executed
doc/I2C_Edge_Conditions
Diff comments   View file @ 0c8721a
... ... @@ -28,7 +28,7 @@
28 28  
29 29 Notes
30 30 -----
31   -!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
  31 +!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
32 32  
33 33 This reset edge condition could possibly be present in every I2C
34 34 controller and device available. For boards where a I2C bus reset
... ... @@ -2,7 +2,7 @@
2 2 --------------------------
3 3  
4 4 These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot.
5   -A specific implementation is made for the IBM405 processor but other flavors
  5 +A specific implementation is made for the AMCC 405 processor but other flavors
6 6 can be easily implemented.
7 7  
8 8 #####################
... ... @@ -58,7 +58,7 @@
58 58 routines are common to all PowerPC processors.
59 59  
60 60 ./cpu/ppc4xx/bedbug_405.c
61   - IBM PPC405 specific debugger routines.
  61 + AMCC PPC405 specific debugger routines.
62 62  
63 63  
64 64 Bedbug support for the MPC860
1   - IBM Ebony Board
  1 + AMCC Ebony Board
2 2  
3 3 Last Update: September 12, 2002
4 4 =======================================================================
5 5  
6   -This file contains some handy info regarding U-Boot and the IBM
  6 +This file contains some handy info regarding U-Boot and the AMCC
7 7 Ebony evalutation board. See the README.ppc440 for additional
8 8 information.
9 9  
... ... @@ -5,7 +5,7 @@
5 5 ---------------
6 6  
7 7 The Xilinx ML300 board is based on the Virtex-II Pro FPGA with
8   -integrated IBM PowerPC 405 core. The board is normally booted from
  8 +integrated AMCC PowerPC 405 core. The board is normally booted from
9 9 System ACE CF. U-Boot is then run out of main memory.
10 10  
11 11 An FPGA is a configurable and thus very flexible device. To
doc/README.mpc85xxads
Diff comments   View file @ 0c8721a
... ... @@ -130,7 +130,7 @@
130 130 include/configs/MPC8540ADS.h
131 131 include/configs/MPC8560ADS.h
132 132  
133   - CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
  133 + CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, AMCC 440, etc)
134 134 CONFIG_E500 BOOKE e500 family(Motorola)
135 135 CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
136 136 CONFIG_MPC8540 MPC8540 specific
1   - IBM Ocotea Board
  1 + AMCC Ocotea Board
2 2  
3 3 Last Update: March 2, 2004
4 4 =======================================================================
5 5  
6   -This file contains some handy info regarding U-Boot and the IBM
  6 +This file contains some handy info regarding U-Boot and the AMCC
7 7 Ocotea 440gx evalutation board. See the README.ppc440 for additional
8 8 information.
9 9  
... ... @@ -53,7 +53,7 @@
53 53 This has been done in the 440gx_enet.c file with a #ifdef/endif
54 54 pair.
55 55  
56   -IBM does not store the EMAC ethernet addresses within their PIBS bootloader.
  56 +AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
57 57 The addresses contained in the config header file are from my particular
58 58 board and you _*should*_ change them to reflect your board either in the
59 59 config file and/or in your environment variables. I found the addresses on
doc/README.ocotea-PIBS-to-U-Boot
Diff comments   View file @ 0c8721a
... ... @@ -75,8 +75,8 @@
75 75  
76 76 U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
77 77  
78   -IBM PowerPC 440 GX Rev. C
79   -Board: IBM 440GX Evaluation Board
  78 +AMCC PowerPC 440 GX Rev. C
  79 +Board: AMCC 440GX Evaluation Board
80 80 VCO: 1066 MHz
81 81 CPU: 533 MHz
82 82 PLB: 152 MHz
... ... @@ -12,7 +12,7 @@
12 12 405gp code. A sample board support implementation is contained
13 13 in the board/ebony directory.
14 14  
15   -All testing was performed using the IBM Ebony board using both
  15 +All testing was performed using the AMCC Ebony board using both
16 16 Rev B and Rev C silicon. However, since the Rev B. silicon has
17 17 extensive errata, support for Rev B. is minimal (it boots, and
18 18 features such as i2c, pci, tftpboot, etc. seem to work ok).
... ... @@ -193,7 +193,7 @@
193 193 | KBD_MODE_DISABLE_MOUSE
194 194 | KBD_MODE_KCC);
195 195  
196   - /* ibm powerpc portables need this to use scan-code set 1 -- Cort */
  196 + /* AMCC powerpc portables need this to use scan-code set 1 -- Cort */
197 197 kbd_write_command_w(KBD_CCMD_READ_MODE);
198 198 if (!(kbd_wait_for_input() & KBD_MODE_KCC)) {
199 199 /*
include/asm-ppc/processor.h
Diff comments   View file @ 0c8721a
... ... @@ -694,7 +694,7 @@
694 694 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
695 695  
696 696 /*
697   - * IBM has further subdivided the standard PowerPC 16-bit version and
  697 + * AMCC has further subdivided the standard PowerPC 16-bit version and
698 698 * revision subfields of the PVR for the PowerPC 403s into the following:
699 699 */
700 700  
... ... @@ -825,7 +825,7 @@
825 825 #define _MACH_gemini 0x00000200 /* Synergy Microsystems gemini board */
826 826 #define _MACH_classic 0x00000400 /* RPCG RPX-Classic 8xx board */
827 827 #define _MACH_oak 0x00000800 /* IBM "Oak" 403 eval. board */
828   -#define _MACH_walnut 0x00001000 /* IBM "Walnut" 405GP eval. board */
  828 +#define _MACH_walnut 0x00001000 /* AMCC "Walnut" 405GP eval. board */
829 829 #define _MACH_8260 0x00002000 /* Generic 8260 */
830 830 #define _MACH_sandpoint 0x00004000 /* Motorola SPS Processor eval board */
831 831 #define _MACH_tqm860 0x00008000 /* TQM860/L */
include/asm-ppc/u-boot.h
Diff comments   View file @ 0c8721a
... ... @@ -79,7 +79,7 @@
79 79 defined(CONFIG_405EP) || \
80 80 defined(CONFIG_440)
81 81 unsigned char bi_s_version[4]; /* Version of this structure */
82   - unsigned char bi_r_version[32]; /* Version of the ROM (IBM) */
  82 + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */
83 83 unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */
84 84 unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */
85 85 unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */
include/configs/ADCIOP.h
Diff comments   View file @ 0c8721a
... ... @@ -184,7 +184,7 @@
184 184 * Cache Configuration
185 185 */
186 186 #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
187   -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
  187 +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
188 188 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
189 189 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
190 190 #endif
include/configs/APC405.h
Diff comments   View file @ 0c8721a
... ... @@ -263,7 +263,7 @@
263 263 /*-----------------------------------------------------------------------
264 264 * Cache Configuration
265 265 */
266   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  266 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
267 267 /* have only 8kB, 16kB is save here */
268 268 #define CFG_CACHELINE_SIZE 32 /* ... */
269 269 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/AR405.h
Diff comments   View file @ 0c8721a
... ... @@ -204,7 +204,7 @@
204 204 /*-----------------------------------------------------------------------
205 205 * Cache Configuration
206 206 */
207   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  207 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
208 208 /* have only 8kB, 16kB is save here */
209 209 #define CFG_CACHELINE_SIZE 32 /* ... */
210 210 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/ASH405.h
Diff comments   View file @ 0c8721a
... ... @@ -264,7 +264,7 @@
264 264 /*-----------------------------------------------------------------------
265 265 * Cache Configuration
266 266 */
267   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  267 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
268 268 /* have only 8kB, 16kB is save here */
269 269 #define CFG_CACHELINE_SIZE 32 /* ... */
270 270 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CANBT.h
Diff comments   View file @ 0c8721a
... ... @@ -171,7 +171,7 @@
171 171 /*-----------------------------------------------------------------------
172 172 * Cache Configuration
173 173 */
174   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  174 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
175 175 #define CFG_CACHELINE_SIZE 32 /* ... */
176 176 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
177 177 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/CATcenter.h
Diff comments   View file @ 0c8721a
... ... @@ -409,7 +409,7 @@
409 409 /*-----------------------------------------------------------------------
410 410 * Cache Configuration
411 411 */
412   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  412 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
413 413 /* have only 8kB, 16kB is save here */
414 414 #define CFG_CACHELINE_SIZE 32 /* ... */
415 415 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CPCI2DP.h
Diff comments   View file @ 0c8721a
... ... @@ -212,7 +212,7 @@
212 212 /*-----------------------------------------------------------------------
213 213 * Cache Configuration
214 214 */
215   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  215 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
216 216 /* have only 8kB, 16kB is save here */
217 217 #define CFG_CACHELINE_SIZE 32 /* ... */
218 218 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CPCI405.h
Diff comments   View file @ 0c8721a
... ... @@ -256,7 +256,7 @@
256 256 /*-----------------------------------------------------------------------
257 257 * Cache Configuration
258 258 */
259   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  259 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
260 260 #define CFG_CACHELINE_SIZE 32 /* ... */
261 261 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
262 262 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/CPCI4052.h
Diff comments   View file @ 0c8721a
... ... @@ -306,7 +306,7 @@
306 306 /*-----------------------------------------------------------------------
307 307 * Cache Configuration
308 308 */
309   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  309 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
310 310 /* have only 8kB, 16kB is save here */
311 311 #define CFG_CACHELINE_SIZE 32 /* ... */
312 312 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CPCI405AB.h
Diff comments   View file @ 0c8721a
... ... @@ -278,7 +278,7 @@
278 278 /*-----------------------------------------------------------------------
279 279 * Cache Configuration
280 280 */
281   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  281 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
282 282 /* have only 8kB, 16kB is save here */
283 283 #define CFG_CACHELINE_SIZE 32 /* ... */
284 284 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CPCI405DT.h
Diff comments   View file @ 0c8721a
... ... @@ -309,7 +309,7 @@
309 309 /*-----------------------------------------------------------------------
310 310 * Cache Configuration
311 311 */
312   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  312 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
313 313 /* have only 8kB, 16kB is save here */
314 314 #define CFG_CACHELINE_SIZE 32 /* ... */
315 315 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/CPCI440.h
Diff comments   View file @ 0c8721a
... ... @@ -265,7 +265,7 @@
265 265 /*-----------------------------------------------------------------------
266 266 * Cache Configuration
267 267 */
268   -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
  268 +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
269 269 #define CFG_CACHELINE_SIZE 32 /* ... */
270 270 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
271 271 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/CPCIISER4.h
Diff comments   View file @ 0c8721a
... ... @@ -187,7 +187,7 @@
187 187 /*-----------------------------------------------------------------------
188 188 * Cache Configuration
189 189 */
190   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  190 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
191 191 #define CFG_CACHELINE_SIZE 32 /* ... */
192 192 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
193 193 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/DASA_SIM.h
Diff comments   View file @ 0c8721a
... ... @@ -183,7 +183,7 @@
183 183 * Cache Configuration
184 184 */
185 185 #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */
186   -#define CFG_CACHELINE_SIZE 16 /* For IBM 401/403 CPUs */
  186 +#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */
187 187 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
188 188 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
189 189 #endif
include/configs/DP405.h
Diff comments   View file @ 0c8721a
... ... @@ -232,7 +232,7 @@
232 232 /*-----------------------------------------------------------------------
233 233 * Cache Configuration
234 234 */
235   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  235 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
236 236 /* have only 8kB, 16kB is save here */
237 237 #define CFG_CACHELINE_SIZE 32 /* ... */
238 238 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/DU405.h
Diff comments   View file @ 0c8721a
... ... @@ -223,7 +223,7 @@
223 223 /*-----------------------------------------------------------------------
224 224 * Cache Configuration
225 225 */
226   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  226 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
227 227 #define CFG_CACHELINE_SIZE 32 /* ... */
228 228 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
229 229 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/ERIC.h
Diff comments   View file @ 0c8721a
... ... @@ -323,7 +323,7 @@
323 323 /*-----------------------------------------------------------------------
324 324 * Cache Configuration
325 325 */
326   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  326 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
327 327 #define CFG_CACHELINE_SIZE 32 /* ... */
328 328 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
329 329 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/G2000.h
Diff comments   View file @ 0c8721a
... ... @@ -321,7 +321,7 @@
321 321 /*-----------------------------------------------------------------------
322 322 * Cache Configuration
323 323 */
324   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  324 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
325 325 /* have only 8kB, 16kB is save here */
326 326 #define CFG_CACHELINE_SIZE 32 /* ... */
327 327 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/HH405.h
Diff comments   View file @ 0c8721a
... ... @@ -359,7 +359,7 @@
359 359 /*-----------------------------------------------------------------------
360 360 * Cache Configuration
361 361 */
362   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  362 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
363 363 /* have only 8kB, 16kB is save here */
364 364 #define CFG_CACHELINE_SIZE 32 /* ... */
365 365 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/HUB405.h
Diff comments   View file @ 0c8721a
... ... @@ -266,7 +266,7 @@
266 266 /*-----------------------------------------------------------------------
267 267 * Cache Configuration
268 268 */
269   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  269 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
270 270 /* have only 8kB, 16kB is save here */
271 271 #define CFG_CACHELINE_SIZE 32 /* ... */
272 272 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/JSE.h
Diff comments   View file @ 0c8721a
... ... @@ -269,7 +269,7 @@
269 269 /*-----------------------------------------------------------------------
270 270 * Cache Configuration
271 271 */
272   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */
  272 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */
273 273 #define CFG_CACHELINE_SIZE 32 /* ... */
274 274 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
275 275 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/KAREF.h
Diff comments   View file @ 0c8721a
... ... @@ -278,7 +278,7 @@
278 278 /*-----------------------------------------------------------------------
279 279 * Cache Configuration
280 280 */
281   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  281 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
282 282 #define CFG_CACHELINE_SIZE 32
283 283 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
284 284 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
include/configs/METROBOX.h
Diff comments   View file @ 0c8721a
... ... @@ -346,7 +346,7 @@
346 346 /*-----------------------------------------------------------------------
347 347 * Cache Configuration
348 348 */
349   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  349 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
350 350 #define CFG_CACHELINE_SIZE 32
351 351 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
352 352 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */
include/configs/MIP405.h
Diff comments   View file @ 0c8721a
... ... @@ -257,7 +257,7 @@
257 257 /*-----------------------------------------------------------------------
258 258 * Cache Configuration
259 259 */
260   -#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
  260 +#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */
261 261 #define CFG_CACHELINE_SIZE 32 /* ... */
262 262 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
263 263 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/ML2.h
Diff comments   View file @ 0c8721a
... ... @@ -193,7 +193,7 @@
193 193 /*-----------------------------------------------------------------------
194 194 * Cache Configuration
195 195 */
196   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  196 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
197 197 #define CFG_CACHELINE_SIZE 32 /* ... */
198 198 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
199 199 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/OCRTC.h
Diff comments   View file @ 0c8721a
... ... @@ -213,7 +213,7 @@
213 213 /*-----------------------------------------------------------------------
214 214 * Cache Configuration
215 215 */
216   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  216 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
217 217 #define CFG_CACHELINE_SIZE 32 /* ... */
218 218 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
219 219 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/ORSG.h
Diff comments   View file @ 0c8721a
... ... @@ -211,7 +211,7 @@
211 211 /*-----------------------------------------------------------------------
212 212 * Cache Configuration
213 213 */
214   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  214 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
215 215 #define CFG_CACHELINE_SIZE 32 /* ... */
216 216 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
217 217 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/PCI405.h
Diff comments   View file @ 0c8721a
... ... @@ -241,7 +241,7 @@
241 241 /*-----------------------------------------------------------------------
242 242 * Cache Configuration
243 243 */
244   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  244 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
245 245 #define CFG_CACHELINE_SIZE 32 /* ... */
246 246 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
247 247 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/PIP405.h
Diff comments   View file @ 0c8721a
... ... @@ -224,7 +224,7 @@
224 224 /*-----------------------------------------------------------------------
225 225 * Cache Configuration
226 226 */
227   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  227 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
228 228 #define CFG_CACHELINE_SIZE 32 /* ... */
229 229 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
230 230 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/PLU405.h
Diff comments   View file @ 0c8721a
... ... @@ -330,7 +330,7 @@
330 330 /*-----------------------------------------------------------------------
331 331 * Cache Configuration
332 332 */
333   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  333 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
334 334 /* have only 8kB, 16kB is save here */
335 335 #define CFG_CACHELINE_SIZE 32 /* ... */
336 336 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/PMC405.h
Diff comments   View file @ 0c8721a
... ... @@ -245,7 +245,7 @@
245 245 /*-----------------------------------------------------------------------
246 246 * Cache Configuration
247 247 */
248   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  248 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
249 249 /* have only 8kB, 16kB is save here */
250 250 #define CFG_CACHELINE_SIZE 32 /* ... */
251 251 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/PPChameleonEVB.h
Diff comments   View file @ 0c8721a
... ... @@ -422,7 +422,7 @@
422 422 /*-----------------------------------------------------------------------
423 423 * Cache Configuration
424 424 */
425   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  425 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
426 426 /* have only 8kB, 16kB is save here */
427 427 #define CFG_CACHELINE_SIZE 32 /* ... */
428 428 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/VOH405.h
Diff comments   View file @ 0c8721a
... ... @@ -314,7 +314,7 @@
314 314 /*-----------------------------------------------------------------------
315 315 * Cache Configuration
316 316 */
317   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  317 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
318 318 /* have only 8kB, 16kB is save here */
319 319 #define CFG_CACHELINE_SIZE 32 /* ... */
320 320 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/VOM405.h
Diff comments   View file @ 0c8721a
... ... @@ -237,7 +237,7 @@
237 237 /*-----------------------------------------------------------------------
238 238 * Cache Configuration
239 239 */
240   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  240 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
241 241 /* have only 8kB, 16kB is save here */
242 242 #define CFG_CACHELINE_SIZE 32 /* ... */
243 243 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/W7OLMC.h
Diff comments   View file @ 0c8721a
... ... @@ -275,7 +275,7 @@
275 275 /*-----------------------------------------------------------------------
276 276 * Cache Configuration
277 277 */
278   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  278 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
279 279 #define CFG_CACHELINE_SIZE 32 /* ... */
280 280 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
281 281 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
include/configs/W7OLMG.h
Diff comments   View file @ 0c8721a
... ... @@ -276,7 +276,7 @@
276 276 /*-----------------------------------------------------------------------
277 277 * Cache Configuration
278 278 */
279   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  279 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
280 280 #define CFG_CACHELINE_SIZE 32 /* ... */
281 281 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
282 282 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
include/configs/WUH405.h
Diff comments   View file @ 0c8721a
... ... @@ -265,7 +265,7 @@
265 265 /*-----------------------------------------------------------------------
266 266 * Cache Configuration
267 267 */
268   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  268 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
269 269 /* have only 8kB, 16kB is save here */
270 270 #define CFG_CACHELINE_SIZE 32 /* ... */
271 271 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/XPEDITE1K.h
Diff comments   View file @ 0c8721a
... ... @@ -24,7 +24,7 @@
24 24 * config for XPedite1000 from XES Inc.
25 25 * Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
26 26 * (C) Copyright 2003 Sandburst Corporation
27   - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
  27 + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
28 28 ***********************************************************************/
29 29  
30 30 #ifndef __CONFIG_H
... ... @@ -253,7 +253,7 @@
253 253 /*-----------------------------------------------------------------------
254 254 * Cache Configuration
255 255 */
256   -#define CFG_DCACHE_SIZE 8192 /* For IBM 440GX CPUs */
  256 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */
257 257 #define CFG_CACHELINE_SIZE 32 /* ... */
258 258 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
259 259 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/bamboo.h
Diff comments   View file @ 0c8721a
... ... @@ -378,7 +378,7 @@
378 378 /*-----------------------------------------------------------------------
379 379 * Cache Configuration
380 380 */
381   -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
  381 +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
382 382 #define CFG_CACHELINE_SIZE 32 /* ... */
383 383 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
384 384 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/bubinga.h
Diff comments   View file @ 0c8721a
... ... @@ -308,7 +308,7 @@
308 308 /*-----------------------------------------------------------------------
309 309 * Cache Configuration
310 310 */
311   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */
  311 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */
312 312 #define CFG_CACHELINE_SIZE 32 /* ... */
313 313 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
314 314 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/csb272.h
Diff comments   View file @ 0c8721a
... ... @@ -291,7 +291,7 @@
291 291 * Cache configuration
292 292 *
293 293 */
294   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  294 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
295 295 /* have only 8kB, 16kB is save here */
296 296 #define CFG_CACHELINE_SIZE 32
297 297  
include/configs/csb472.h
Diff comments   View file @ 0c8721a
... ... @@ -291,7 +291,7 @@
291 291 * Cache configuration
292 292 *
293 293 */
294   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  294 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
295 295 /* have only 8kB, 16kB is save here */
296 296 #define CFG_CACHELINE_SIZE 32
297 297  
include/configs/ebony.h
Diff comments   View file @ 0c8721a
... ... @@ -21,7 +21,7 @@
21 21 */
22 22  
23 23 /************************************************************************
24   - * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony)
  24 + * board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
25 25 ***********************************************************************/
26 26  
27 27 #ifndef __CONFIG_H
... ... @@ -272,7 +272,7 @@
272 272 /*-----------------------------------------------------------------------
273 273 * Cache Configuration
274 274 */
275   -#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  275 +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
276 276 #define CFG_CACHELINE_SIZE 32 /* ... */
277 277 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
278 278 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/ml300.h
Diff comments   View file @ 0c8721a
... ... @@ -147,7 +147,7 @@
147 147 /*-----------------------------------------------------------------------
148 148 * Cache Configuration
149 149 */
150   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs */
  150 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */
151 151 #define CFG_CACHELINE_SIZE 32 /* ... */
152 152  
153 153 /*-----------------------------------------------------------------------
include/configs/ocotea.h
Diff comments   View file @ 0c8721a
... ... @@ -30,7 +30,7 @@
30 30  
31 31  
32 32 /************************************************************************
33   - * OCOTEA.h - configuration for IBM 440GX Ref (Ocotea)
  33 + * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
34 34 ***********************************************************************/
35 35  
36 36 #ifndef __CONFIG_H
... ... @@ -297,7 +297,7 @@
297 297 /*-----------------------------------------------------------------------
298 298 * Cache Configuration
299 299 */
300   -#define CFG_DCACHE_SIZE 32768 /* For IBM 440 CPUs */
  300 +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
301 301 #define CFG_CACHELINE_SIZE 32 /* ... */
302 302 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
303 303 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/sbc405.h
Diff comments   View file @ 0c8721a
... ... @@ -226,7 +226,7 @@
226 226 /*-----------------------------------------------------------------------
227 227 * Cache Configuration
228 228 */
229   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  229 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
230 230 /* have only 8kB, 16kB is save here */
231 231 #define CFG_CACHELINE_SIZE 32 /* ... */
232 232 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/walnut.h
Diff comments   View file @ 0c8721a
... ... @@ -267,7 +267,7 @@
267 267 /*-----------------------------------------------------------------------
268 268 * Cache Configuration
269 269 */
270   -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  270 +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
271 271 /* have only 8kB, 16kB is save here */
272 272 #define CFG_CACHELINE_SIZE 32 /* ... */
273 273 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
include/configs/yellowstone.h
Diff comments   View file @ 0c8721a
... ... @@ -291,7 +291,7 @@
291 291 /*-----------------------------------------------------------------------
292 292 * Cache Configuration
293 293 */
294   -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
  294 +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
295 295 #define CFG_CACHELINE_SIZE 32 /* ... */
296 296 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
297 297 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
include/configs/yosemite.h
Diff comments   View file @ 0c8721a
... ... @@ -292,7 +292,7 @@
292 292 /*-----------------------------------------------------------------------
293 293 * Cache Configuration
294 294 */
295   -#define CFG_DCACHE_SIZE (32<<10) /* For IBM 440 CPUs */
  295 +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
296 296 #define CFG_CACHELINE_SIZE 32 /* ... */
297 297 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
298 298 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
... ... @@ -84,7 +84,7 @@
84 84 void reset_5xx_watchdog(volatile immap_t *immr);
85 85 #endif
86 86  
87   -/* IBM 4xx */
  87 +/* AMCC 4xx */
88 88 #if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
89 89 void reset_4xx_watchdog(void);
90 90 #endif