Eric Lee / smarc-uboot

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Commit 0ca855a9e2718339692681594cfd225aa54adf56

Authored by Ye Li
1 parent 6a09251091
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18456-3 mx6sx_arm2: Add 17x17 ARM2 and 14x14 ARM2 support 

Porting the 17x17 ARM2 and 14x14 ARM2 board codes from v2017.03. The
14x14 ARM2 shares similar board design with 17x17 ARM2, but uses LPDDR2
memory. So share the codes for them.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 10 changed files with 1936 additions and 3 deletions Side-by-side Diff

arch/arm/mach-imx/mx6/Kconfig
Diff comments   View file @ 0ca855a
... ... @@ -96,14 +96,14 @@
96 96 default y if !MX6SLL
97 97 help
98 98 This feature searches the gpc node in loaded DTB and checking the
99   - "fsl,ldo-bypass" property. When the property is set, board relevant
100   - PMIC settings are called to adjust for LDO bypass.
  99 + "fsl,ldo-bypass" property. When the property is set, board relevant
  100 + PMIC settings are called to adjust for LDO bypass.
101 101  
102 102 config CMD_BEE
103 103 bool "Enable commands for Bus Encryption Engine(BEE)"
104 104 depends on MX6UL
105 105 help
106   - Set "Y" to enable the bee commands
  106 + Set "Y" to enable the bee commands
107 107  
108 108 config MODULE_FUSE
109 109 bool "Enable the module disable fuse checking on i.MX6"
... ... @@ -353,6 +353,22 @@
353 353 select DM_THERMAL
354 354 select BOARD_EARLY_INIT_F
355 355  
  356 +config TARGET_MX6SX_14X14_ARM2
  357 + bool "mx6sx_14x14_arm2"
  358 + select MX6SX
  359 + select DM
  360 + select DM_THERMAL
  361 + select BOARD_EARLY_INIT_F
  362 + select BOARD_LATE_INIT
  363 +
  364 +config TARGET_MX6SX_17X17_ARM2
  365 + bool "mx6sx_17x17_arm2"
  366 + select MX6SX
  367 + select DM
  368 + select DM_THERMAL
  369 + select BOARD_EARLY_INIT_F
  370 + select BOARD_LATE_INIT
  371 +
356 372 config TARGET_MX6UL_9X9_EVK
357 373 bool "mx6ul_9x9_evk"
358 374 select BOARD_LATE_INIT
... ... @@ -544,6 +560,7 @@
544 560 source "board/freescale/mx6sllevk/Kconfig"
545 561 source "board/freescale/mx6sxsabresd/Kconfig"
546 562 source "board/freescale/mx6sxsabreauto/Kconfig"
  563 +source "board/freescale/mx6sx_17x17_arm2/Kconfig"
547 564 source "board/freescale/mx6ul_14x14_evk/Kconfig"
548 565 source "board/freescale/mx6ullevk/Kconfig"
549 566 source "board/grinn/liteboard/Kconfig"
board/freescale/mx6sx_17x17_arm2/Kconfig
Diff comments   View file @ 0ca855a
  1 +if TARGET_MX6SX_17X17_ARM2 || TARGET_MX6SX_14X14_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx6sx_17x17_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx6sx_17x17_arm2"
  11 +
  12 +config SYS_TEXT_BASE
  13 + default 0x87800000
  14 +
  15 +config LPDDR2_BOARD
  16 + bool "Select for the board using LPDDR2 not default DDR3"
  17 +
  18 +config NOR
  19 + bool "Support for NOR flash"
  20 + help
  21 + The i.MX SoC supports having a NOR flash connected to the WEIM.
  22 + Need to set this for NOR_BOOT.
  23 +endif
board/freescale/mx6sx_17x17_arm2/Makefile
Diff comments   View file @ 0ca855a
  1 +# (C) Copyright 2014 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx6sx_17x17_arm2.o
board/freescale/mx6sx_17x17_arm2/imximage.cfg
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_QSPI_BOOT
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_NOR_BOOT)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x020c4068 0xffffffff
  54 +DATA 4 0x020c406c 0xffffffff
  55 +DATA 4 0x020c4070 0xffffffff
  56 +DATA 4 0x020c4074 0xffffffff
  57 +DATA 4 0x020c4078 0xffffffff
  58 +DATA 4 0x020c407c 0xffffffff
  59 +DATA 4 0x020c4080 0xffffffff
  60 +DATA 4 0x020c4084 0xffffffff
  61 +
  62 +DATA 4 0x020e0618 0x000c0000
  63 +DATA 4 0x020e05fc 0x00000000
  64 +DATA 4 0x020e032c 0x00000030
  65 +
  66 +DATA 4 0x020e0300 0x00000030
  67 +DATA 4 0x020e02fc 0x00000030
  68 +DATA 4 0x020e05f4 0x00000030
  69 +DATA 4 0x020e0340 0x00000030
  70 +
  71 +DATA 4 0x020e0320 0x00000000
  72 +DATA 4 0x020e0310 0x00000030
  73 +DATA 4 0x020e0314 0x00000030
  74 +DATA 4 0x020e0614 0x00000030
  75 +
  76 +DATA 4 0x020e05f8 0x00020000
  77 +DATA 4 0x020e0330 0x00000030
  78 +DATA 4 0x020e0334 0x00000030
  79 +DATA 4 0x020e0338 0x00000030
  80 +DATA 4 0x020e033c 0x00000030
  81 +DATA 4 0x020e0608 0x00020000
  82 +DATA 4 0x020e060c 0x00000030
  83 +DATA 4 0x020e0610 0x00000030
  84 +DATA 4 0x020e061c 0x00000030
  85 +DATA 4 0x020e0620 0x00000030
  86 +DATA 4 0x020e02ec 0x00000030
  87 +DATA 4 0x020e02f0 0x00000030
  88 +DATA 4 0x020e02f4 0x00000030
  89 +DATA 4 0x020e02f8 0x00000030
  90 +DATA 4 0x021b0800 0xa1390003
  91 +DATA 4 0x021b080c 0x00270025
  92 +DATA 4 0x021b0810 0x001B001E
  93 +DATA 4 0x021b083c 0x4144013C
  94 +DATA 4 0x021b0840 0x01300128
  95 +DATA 4 0x021b0848 0x4044464A
  96 +DATA 4 0x021b0850 0x3A383C34
  97 +DATA 4 0x021b081c 0x33333333
  98 +DATA 4 0x021b0820 0x33333333
  99 +DATA 4 0x021b0824 0x33333333
  100 +DATA 4 0x021b0828 0x33333333
  101 +DATA 4 0x021b08b8 0x00000800
  102 +DATA 4 0x021b0004 0x0002002d
  103 +DATA 4 0x021b0008 0x00333030
  104 +DATA 4 0x021b000c 0x676b52f3
  105 +DATA 4 0x021b0010 0xb66d8b63
  106 +DATA 4 0x021b0014 0x01ff00db
  107 +DATA 4 0x021b0018 0x00011740
  108 +DATA 4 0x021b001c 0x00008000
  109 +DATA 4 0x021b002c 0x000026d2
  110 +DATA 4 0x021b0030 0x006b1023
  111 +DATA 4 0x021b0040 0x0000005f
  112 +DATA 4 0x021b0000 0x84190000
  113 +DATA 4 0x021b001c 0x04008032
  114 +DATA 4 0x021b001c 0x00008033
  115 +DATA 4 0x021b001c 0x00068031
  116 +DATA 4 0x021b001c 0x05208030
  117 +DATA 4 0x021b001c 0x04008040
  118 +DATA 4 0x021b0020 0x00000800
  119 +DATA 4 0x021b0818 0x00011117
  120 +DATA 4 0x021b001c 0x00000000
  121 +
  122 +#endif
board/freescale/mx6sx_17x17_arm2/imximage_wp.cfg
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_QSPI_BOOT
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_NOR_BOOT)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_SECURE_BOOT
  33 +CSF CONFIG_CSF_SIZE
  34 +#endif
  35 +
  36 +/*
  37 + * Device Configuration Data (DCD)
  38 + *
  39 + * Each entry must have the format:
  40 + * Addr-type Address Value
  41 + *
  42 + * where:
  43 + * Addr-type register length (1,2 or 4 bytes)
  44 + * Address absolute address of the register
  45 + * value value to be stored in the register
  46 + */
  47 +
  48 +DATA 4 0x020c4068 0xffffffff
  49 +DATA 4 0x020c406c 0xffffffff
  50 +DATA 4 0x020c4070 0xffffffff
  51 +DATA 4 0x020c4074 0xffffffff
  52 +DATA 4 0x020c4078 0xffffffff
  53 +DATA 4 0x020c407c 0xffffffff
  54 +DATA 4 0x020c4080 0xffffffff
  55 +DATA 4 0x020c4084 0xffffffff
  56 +
  57 +DATA 4 0x020e0618 0x000c0000
  58 +DATA 4 0x020e05fc 0x00000000
  59 +DATA 4 0x020e032c 0x00000030
  60 +
  61 +DATA 4 0x020e0300 0x00000030
  62 +DATA 4 0x020e02fc 0x00000030
  63 +DATA 4 0x020e05f4 0x00000030
  64 +DATA 4 0x020e0340 0x00000030
  65 +
  66 +DATA 4 0x020e0320 0x00000000
  67 +DATA 4 0x020e0310 0x00000030
  68 +DATA 4 0x020e0314 0x00000030
  69 +DATA 4 0x020e0614 0x00000030
  70 +
  71 +DATA 4 0x020e05f8 0x00020000
  72 +DATA 4 0x020e0330 0x00000030
  73 +DATA 4 0x020e0334 0x00000030
  74 +DATA 4 0x020e0338 0x00000030
  75 +DATA 4 0x020e033c 0x00000030
  76 +DATA 4 0x020e0608 0x00020000
  77 +DATA 4 0x020e060c 0x00000030
  78 +DATA 4 0x020e0610 0x00000030
  79 +DATA 4 0x020e061c 0x00000030
  80 +DATA 4 0x020e0620 0x00000030
  81 +DATA 4 0x020e02ec 0x00000030
  82 +DATA 4 0x020e02f0 0x00000030
  83 +DATA 4 0x020e02f4 0x00000030
  84 +DATA 4 0x020e02f8 0x00000030
  85 +DATA 4 0x021b0800 0xa1390003
  86 +DATA 4 0x021b080c 0x002E003C
  87 +DATA 4 0x021b0810 0x001A003F
  88 +DATA 4 0x021b083c 0x41480150
  89 +DATA 4 0x021b0840 0x012C0150
  90 +DATA 4 0x021b0848 0x40404646
  91 +DATA 4 0x021b0850 0x38363C32
  92 +DATA 4 0x021b08c0 0x2492244A
  93 +DATA 4 0x021b081c 0x33333333
  94 +DATA 4 0x021b0820 0x33333333
  95 +DATA 4 0x021b0824 0x33333333
  96 +DATA 4 0x021b0828 0x33333333
  97 +DATA 4 0x021b08b8 0x00000800
  98 +DATA 4 0x021b0004 0x0002002d
  99 +DATA 4 0x021b0008 0x00333030
  100 +DATA 4 0x021b000c 0x676b52f3
  101 +DATA 4 0x021b0010 0xb66d8b63
  102 +DATA 4 0x021b0014 0x01ff00db
  103 +DATA 4 0x021b0018 0x00011740
  104 +DATA 4 0x021b001c 0x00008000
  105 +DATA 4 0x021b002c 0x000026d2
  106 +DATA 4 0x021b0030 0x006b1023
  107 +DATA 4 0x021b0040 0x0000005f
  108 +DATA 4 0x021b0000 0x84190000
  109 +DATA 4 0x021b001c 0x04008032
  110 +DATA 4 0x021b001c 0x00008033
  111 +DATA 4 0x021b001c 0x00068031
  112 +DATA 4 0x021b001c 0x05208030
  113 +DATA 4 0x021b001c 0x04008040
  114 +DATA 4 0x021b0020 0x00000800
  115 +DATA 4 0x021b0818 0x00022227
  116 +DATA 4 0x021b0004 0x0002556d
  117 +DATA 4 0x021b0404 0x00011006
  118 +DATA 4 0x021b001c 0x00000000
board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +#ifdef CONFIG_QSPI_BOOT
  25 +BOOT_FROM qspi
  26 +#elif defined(CONFIG_NOR_BOOT)
  27 +BOOT_FROM nor
  28 +#else
  29 +BOOT_FROM sd
  30 +#endif
  31 +
  32 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  33 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  34 +PLUGIN board/freescale/mx6sx_17x17_arm2/plugin.bin 0x00907000
  35 +#else
  36 +
  37 +#ifdef CONFIG_SECURE_BOOT
  38 +CSF CONFIG_CSF_SIZE
  39 +#endif
  40 +
  41 +/*
  42 + * Device Configuration Data (DCD)
  43 + *
  44 + * Each entry must have the format:
  45 + * Addr-type Address Value
  46 + *
  47 + * where:
  48 + * Addr-type register length (1,2 or 4 bytes)
  49 + * Address absolute address of the register
  50 + * value value to be stored in the register
  51 + */
  52 +
  53 +DATA 4 0x020c4068 0xffffffff
  54 +DATA 4 0x020c406c 0xffffffff
  55 +DATA 4 0x020c4070 0xffffffff
  56 +DATA 4 0x020c4074 0xffffffff
  57 +DATA 4 0x020c4078 0xffffffff
  58 +DATA 4 0x020c407c 0xffffffff
  59 +DATA 4 0x020c4080 0xffffffff
  60 +DATA 4 0x020c4084 0xffffffff
  61 +
  62 +DATA 4 0x020c4018 0x00260324
  63 +
  64 +DATA 4 0x020e0618 0x00080000
  65 +DATA 4 0x020e05fc 0x00000000
  66 +DATA 4 0x020e032c 0x00000030
  67 +
  68 +DATA 4 0x020e0300 0x00000028
  69 +DATA 4 0x020e02fc 0x00000028
  70 +DATA 4 0x020e05f4 0x00000028
  71 +DATA 4 0x020e0340 0x00000028
  72 +
  73 +DATA 4 0x020e0320 0x00000000
  74 +DATA 4 0x020e0310 0x00000000
  75 +DATA 4 0x020e0314 0x00000000
  76 +DATA 4 0x020e0614 0x00000028
  77 +
  78 +DATA 4 0x020e05f8 0x00020000
  79 +DATA 4 0x020e0330 0x00003028
  80 +DATA 4 0x020e0334 0x00003028
  81 +DATA 4 0x020e0338 0x00003028
  82 +DATA 4 0x020e033c 0x00003028
  83 +
  84 +DATA 4 0x020e0608 0x00020000
  85 +DATA 4 0x020e060c 0x00000028
  86 +DATA 4 0x020e0610 0x00000028
  87 +DATA 4 0x020e061c 0x00000028
  88 +DATA 4 0x020e0620 0x00000028
  89 +
  90 +DATA 4 0x020e02ec 0x00000028
  91 +DATA 4 0x020e02f0 0x00000028
  92 +DATA 4 0x020e02f4 0x00000028
  93 +DATA 4 0x020e02f8 0x00000028
  94 +
  95 +DATA 4 0x021b001c 0x00008000
  96 +DATA 4 0x021b085c 0x1b4700c7
  97 +
  98 +DATA 4 0x021b0800 0xa1390003
  99 +DATA 4 0x021b0890 0x00380000
  100 +DATA 4 0x021b08b8 0x00000800
  101 +
  102 +DATA 4 0x021b081c 0x33333333
  103 +DATA 4 0x021b0820 0x33333333
  104 +DATA 4 0x021b0824 0x33333333
  105 +DATA 4 0x021b0828 0x33333333
  106 +
  107 +DATA 4 0x021b082c 0x51111111
  108 +DATA 4 0x021b0830 0x51111111
  109 +DATA 4 0x021b0834 0x51111111
  110 +DATA 4 0x021b0838 0x51111111
  111 +
  112 +DATA 4 0x021b0848 0x42424244
  113 +
  114 +DATA 4 0x021b0850 0x2E30322E
  115 +DATA 4 0x021b08c0 0x2492244A
  116 +DATA 4 0x021b083c 0x20000000
  117 +DATA 4 0x021b0840 0x0
  118 +
  119 +DATA 4 0x021b08b8 0x00000800
  120 +
  121 +DATA 4 0x021b000c 0x33374133
  122 +DATA 4 0x021b0004 0x00020024
  123 +DATA 4 0x021b0010 0x00100A42
  124 +DATA 4 0x021b0014 0x00000093
  125 +DATA 4 0x021b0018 0x00001748
  126 +DATA 4 0x021b002c 0x0f9f26d2
  127 +DATA 4 0x021b0030 0x0000020e
  128 +DATA 4 0x021b0038 0x00190778
  129 +DATA 4 0x021b0008 0x00000000
  130 +DATA 4 0x021b0040 0x0000004f
  131 +DATA 4 0x021b0000 0xc3110000
  132 +
  133 +DATA 4 0x021b001c 0x00008010
  134 +DATA 4 0x021b001c 0x003f8030
  135 +DATA 4 0x021b001c 0xff0a8030
  136 +DATA 4 0x021b001c 0x82018030
  137 +DATA 4 0x021b001c 0x04028030
  138 +DATA 4 0x021b001c 0x01038030
  139 +
  140 +DATA 4 0x021b001c 0x00008018
  141 +DATA 4 0x021b001c 0x003f8038
  142 +DATA 4 0x021b001c 0xff0a8038
  143 +DATA 4 0x021b001c 0x82018038
  144 +DATA 4 0x021b001c 0x04028038
  145 +DATA 4 0x021b001c 0x01038038
  146 +
  147 +DATA 4 0x021b0020 0x00001800
  148 +DATA 4 0x021b0818 0x00000000
  149 +
  150 +DATA 4 0x021b0800 0xa1310003
  151 +DATA 4 0x021b0004 0x00025576
  152 +DATA 4 0x021b0404 0x00011006
  153 +DATA 4 0x021b001c 0x00000000
  154 +
  155 +#endif
board/freescale/mx6sx_17x17_arm2/mx6sx_17x17_arm2.c
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/iomux.h>
  9 +#include <asm/arch/imx-regs.h>
  10 +#include <asm/arch/mx6-pins.h>
  11 +#include <asm/arch/sys_proto.h>
  12 +#include <asm/gpio.h>
  13 +#include <asm/mach-imx/iomux-v3.h>
  14 +#include <asm/mach-imx/boot_mode.h>
  15 +#include <asm/io.h>
  16 +#include <linux/sizes.h>
  17 +#include <common.h>
  18 +#include <fsl_esdhc.h>
  19 +#include <mmc.h>
  20 +#include <miiphy.h>
  21 +#include <netdev.h>
  22 +#ifdef CONFIG_SYS_I2C_MXC
  23 +#include <i2c.h>
  24 +#include <asm/mach-imx/mxc_i2c.h>
  25 +#endif
  26 +#include <asm/arch/crm_regs.h>
  27 +#include <power/pmic.h>
  28 +#include <power/pfuze100_pmic.h>
  29 +#include "../common/pfuze.h"
  30 +#include <usb.h>
  31 +#include <usb/ehci-ci.h>
  32 +#include <dm.h>
  33 +
  34 +DECLARE_GLOBAL_DATA_PTR;
  35 +
  36 +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  37 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  38 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39 +
  40 +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  42 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43 +
  44 +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  45 + PAD_CTL_SPEED_MED | \
  46 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  47 +
  48 +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  49 + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST)
  50 +
  51 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  53 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  54 + PAD_CTL_ODE)
  55 +
  56 +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  57 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  58 +
  59 +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  60 +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  61 + PAD_CTL_SRE_FAST)
  62 +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  63 +
  64 +#define SPI_PAD_CTRL (PAD_CTL_HYS | \
  65 + PAD_CTL_SPEED_MED | \
  66 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  67 +
  68 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  69 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  70 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  71 +
  72 +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
  73 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  74 + PAD_CTL_DSE_40ohm)
  75 +
  76 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  77 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  78 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  79 +
  80 +#ifdef CONFIG_SYS_I2C
  81 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  82 +/* I2C1 for PMIC */
  83 +struct i2c_pads_info i2c_pad_info1 = {
  84 + .scl = {
  85 + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  86 + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  87 + .gp = IMX_GPIO_NR(1, 0),
  88 + },
  89 + .sda = {
  90 + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  91 + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  92 + .gp = IMX_GPIO_NR(1, 1),
  93 + },
  94 +};
  95 +
  96 +/* I2C2 */
  97 +struct i2c_pads_info i2c_pad_info2 = {
  98 + .scl = {
  99 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
  100 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
  101 + .gp = IMX_GPIO_NR(1, 2),
  102 + },
  103 + .sda = {
  104 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
  105 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
  106 + .gp = IMX_GPIO_NR(1, 3),
  107 + },
  108 +};
  109 +#endif
  110 +
  111 +#ifdef CONFIG_POWER
  112 +#define I2C_PMIC 0
  113 +int power_init_board(void)
  114 +{
  115 + struct pmic *pfuze;
  116 + unsigned int reg;
  117 + int ret;
  118 +
  119 + pfuze = pfuze_common_init(I2C_PMIC);
  120 + if (!pfuze)
  121 + return -ENODEV;
  122 +
  123 + ret = pfuze_mode_init(pfuze, APS_PFM);
  124 + if (ret < 0)
  125 + return ret;
  126 +
  127 + /* set SW1AB staby volatage 0.975V */
  128 + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
  129 + reg &= ~0x3f;
  130 + reg |= PFUZE100_SW1ABC_SETP(9750);
  131 + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
  132 +
  133 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  134 + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
  135 + reg &= ~0xc0;
  136 + reg |= 0x40;
  137 + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
  138 +
  139 + /* set SW1C staby volatage 0.975V */
  140 + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
  141 + reg &= ~0x3f;
  142 + reg |= PFUZE100_SW1ABC_SETP(9750);
  143 + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
  144 +
  145 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  146 + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
  147 + reg &= ~0xc0;
  148 + reg |= 0x40;
  149 + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
  150 +
  151 + return 0;
  152 +}
  153 +
  154 +#ifdef CONFIG_LDO_BYPASS_CHECK
  155 +void ldo_mode_set(int ldo_bypass)
  156 +{
  157 + unsigned int value;
  158 + int is_400M;
  159 + u32 vddarm;
  160 + struct pmic *p = pmic_get("PFUZE100");
  161 +
  162 + if (!p) {
  163 + printf("No PMIC found!\n");
  164 + return;
  165 + }
  166 +
  167 + /* switch to ldo_bypass mode */
  168 + if (ldo_bypass) {
  169 + prep_anatop_bypass();
  170 + /* decrease VDDARM to 1.275V */
  171 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  172 + value &= ~0x3f;
  173 + value |= PFUZE100_SW1ABC_SETP(12750);
  174 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  175 +
  176 + /* decrease VDDSOC to 1.3V */
  177 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  178 + value &= ~0x3f;
  179 + value |= PFUZE100_SW1ABC_SETP(13000);
  180 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  181 +
  182 + is_400M = set_anatop_bypass(1);
  183 + if (is_400M)
  184 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  185 + else
  186 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  187 +
  188 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  189 + value &= ~0x3f;
  190 + value |= vddarm;
  191 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  192 +
  193 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  194 + value &= ~0x3f;
  195 + value |= PFUZE100_SW1ABC_SETP(11750);
  196 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  197 +
  198 + finish_anatop_bypass();
  199 + printf("switch to ldo_bypass mode!\n");
  200 + }
  201 +
  202 +}
  203 +#endif
  204 +
  205 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  206 +int power_init_board(void)
  207 +{
  208 + struct udevice *dev;
  209 + int ret;
  210 +
  211 + dev = pfuze_common_init();
  212 + if (!dev)
  213 + return -ENODEV;
  214 +
  215 + ret = pfuze_mode_init(dev, APS_PFM);
  216 + if (ret < 0)
  217 + return ret;
  218 +
  219 + return 0;
  220 +}
  221 +
  222 +#ifdef CONFIG_LDO_BYPASS_CHECK
  223 +void ldo_mode_set(int ldo_bypass)
  224 +{
  225 + struct udevice *dev;
  226 + int ret;
  227 + int is_400M;
  228 + u32 vddarm;
  229 +
  230 + ret = pmic_get("pfuze100", &dev);
  231 + if (ret == -ENODEV) {
  232 + printf("No PMIC found!\n");
  233 + return;
  234 + }
  235 +
  236 + /* switch to ldo_bypass mode , boot on 800Mhz */
  237 + if (ldo_bypass) {
  238 + prep_anatop_bypass();
  239 +
  240 + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
  241 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
  242 +
  243 + /* increase VDDSOC to 1.3V */
  244 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
  245 +
  246 + is_400M = set_anatop_bypass(1);
  247 + if (is_400M)
  248 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  249 + else
  250 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  251 +
  252 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
  253 +
  254 + /* decrease VDDSOC to 1.175V */
  255 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
  256 +
  257 + finish_anatop_bypass();
  258 + printf("switch to ldo_bypass mode!\n");
  259 + }
  260 +}
  261 +#endif
  262 +#endif
  263 +
  264 +int dram_init(void)
  265 +{
  266 + gd->ram_size = PHYS_SDRAM_SIZE;
  267 +
  268 + return 0;
  269 +}
  270 +
  271 +static iomux_v3_cfg_t const uart1_pads[] = {
  272 + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  273 + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  274 +};
  275 +
  276 +#ifndef CONFIG_MXC_SPI
  277 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  278 + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  279 + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  280 + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  281 + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  282 + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  283 + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  284 +};
  285 +#endif
  286 +
  287 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  288 + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  289 + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  290 + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  291 + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  292 + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  293 + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  294 + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  295 + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  296 + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  297 + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  298 +
  299 + /*CD pin*/
  300 + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  301 +};
  302 +
  303 +static iomux_v3_cfg_t const usdhc4_pads[] = {
  304 + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  305 + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  306 + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  307 + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  308 + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  309 + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  310 + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  311 + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  312 + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  313 + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  314 +};
  315 +
  316 +#ifdef CONFIG_FEC_MXC
  317 +static iomux_v3_cfg_t const fec1_pads[] = {
  318 + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  319 + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  320 + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  321 + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  322 + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  323 + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  324 + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  325 + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  326 + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  327 + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  328 + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  329 + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  330 + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  331 + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  332 +
  333 + /* AR8031 PHY Reset. For arm2 board, silder the resistance */
  334 + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  335 +};
  336 +
  337 +static void setup_iomux_fec1(void)
  338 +{
  339 + SETUP_IOMUX_PADS(fec1_pads);
  340 +}
  341 +#endif
  342 +
  343 +static void setup_iomux_uart(void)
  344 +{
  345 + SETUP_IOMUX_PADS(uart1_pads);
  346 +}
  347 +
  348 +#ifdef CONFIG_FSL_QSPI
  349 +#ifndef CONFIG_DM_SPI
  350 +#define QSPI_PAD_CTRL1 \
  351 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
  352 + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
  353 +
  354 +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm)
  355 +
  356 +static iomux_v3_cfg_t const quadspi_pads[] = {
  357 + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  358 + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  359 + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  360 + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  361 + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  362 + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  363 + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  364 + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  365 + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  366 + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  367 + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  368 + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  369 +
  370 +};
  371 +#endif
  372 +
  373 +int board_qspi_init(void)
  374 +{
  375 +#ifndef CONFIG_DM_SPI
  376 + /* Set the iomux */
  377 + SETUP_IOMUX_PADS(quadspi_pads);
  378 +#endif
  379 +
  380 + /* Set the clock */
  381 + enable_qspi_clk(1);
  382 +
  383 + return 0;
  384 +}
  385 +#endif
  386 +
  387 +#ifdef CONFIG_FSL_ESDHC
  388 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  389 + {USDHC2_BASE_ADDR, 0, 4},
  390 + {USDHC3_BASE_ADDR},
  391 + {USDHC4_BASE_ADDR},
  392 +};
  393 +
  394 +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
  395 +
  396 +int board_mmc_get_env_dev(int dev_no)
  397 +{
  398 +#ifdef CONFIG_MXC_SPI
  399 + dev_no -= 2;
  400 +#else
  401 + dev_no--;
  402 +#endif
  403 +
  404 + return dev_no;
  405 +}
  406 +
  407 +int mmc_map_to_kernel_blk(int dev_no)
  408 +{
  409 +#ifdef CONFIG_MXC_SPI
  410 + return dev_no + 2;
  411 +#else
  412 + return dev_no + 1;
  413 +#endif
  414 +}
  415 +
  416 +int board_mmc_getcd(struct mmc *mmc)
  417 +{
  418 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  419 + int ret = 0;
  420 +
  421 + switch (cfg->esdhc_base) {
  422 + case USDHC2_BASE_ADDR:
  423 + ret = 1; /*always present */
  424 + break;
  425 + case USDHC3_BASE_ADDR:
  426 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  427 + break;
  428 + case USDHC4_BASE_ADDR:
  429 + ret = 1; /*always present */
  430 + break;
  431 + }
  432 +
  433 + return ret;
  434 +}
  435 +
  436 +#ifdef CONFIG_MXC_SPI
  437 +int board_mmc_init(bd_t *bis)
  438 +{
  439 + int i;
  440 +
  441 + /*
  442 + * According to the board_mmc_init() the following map is done:
  443 + * (U-boot device node) (Physical Port)
  444 + * mmc0 SD3 (SDB)
  445 + * mmc1 eMMC
  446 + */
  447 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  448 + switch (i) {
  449 + case 0:
  450 + SETUP_IOMUX_PADS(usdhc3_pads);
  451 + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
  452 + gpio_direction_input(USDHC3_CD_GPIO);
  453 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  454 + break;
  455 + case 1:
  456 + SETUP_IOMUX_PADS(usdhc4_pads);
  457 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  458 + break;
  459 + default:
  460 + printf("Warning: you configured more USDHC controllers"
  461 + "(%d) than supported by the board\n", i + 1);
  462 + return 0;
  463 + }
  464 +
  465 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  466 + printf("Warning: failed to initialize mmc dev %d\n", i);
  467 + }
  468 +
  469 + return 0;
  470 +}
  471 +
  472 +#else
  473 +int board_mmc_init(bd_t *bis)
  474 +{
  475 + int i;
  476 +
  477 + /*
  478 + * According to the board_mmc_init() the following map is done:
  479 + * (U-boot device node) (Physical Port)
  480 + * mmc0 SD2 (SDA)
  481 + * mmc1 SD3 (SDB)
  482 + * mmc2 eMMC
  483 + */
  484 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  485 + switch (i) {
  486 + case 0:
  487 + SETUP_IOMUX_PADS(usdhc2_pads);
  488 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  489 + break;
  490 + case 1:
  491 + SETUP_IOMUX_PADS(usdhc3_pads);
  492 + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
  493 + gpio_direction_input(USDHC3_CD_GPIO);
  494 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  495 + break;
  496 + case 2:
  497 + SETUP_IOMUX_PADS(usdhc4_pads);
  498 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  499 + break;
  500 + default:
  501 + printf("Warning: you configured more USDHC controllers"
  502 + "(%d) than supported by the board\n", i + 1);
  503 + return 0;
  504 + }
  505 +
  506 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  507 + printf("Warning: failed to initialize mmc dev %d\n", i);
  508 + }
  509 +
  510 + return 0;
  511 +}
  512 +#endif
  513 +#endif
  514 +
  515 +#ifdef CONFIG_MXC_SPI
  516 +iomux_v3_cfg_t const ecspi4_pads[] = {
  517 + MX6_PAD_SD2_CLK__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  518 + MX6_PAD_SD2_DATA3__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  519 + MX6_PAD_SD2_CMD__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  520 + MX6_PAD_SD2_DATA2__GPIO6_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  521 +};
  522 +
  523 +void setup_spinor(void)
  524 +{
  525 + SETUP_IOMUX_PADS(ecspi4_pads);
  526 + gpio_request(IMX_GPIO_NR(6, 10), "ecspi cs");
  527 + gpio_direction_output(IMX_GPIO_NR(6, 10), 0);
  528 +}
  529 +
  530 +int board_spi_cs_gpio(unsigned bus, unsigned cs)
  531 +{
  532 + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(6, 10)) : -1;
  533 +}
  534 +#endif
  535 +
  536 +#ifdef CONFIG_MTD_NOR_FLASH
  537 +iomux_v3_cfg_t eimnor_pads[] = {
  538 + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  539 + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  540 + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  541 + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  542 + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  543 + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  544 + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  545 + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  546 + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  547 + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  548 + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  549 + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
  550 + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  551 + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  552 + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  553 + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  554 + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  555 + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  556 + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  557 + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  558 + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  559 + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  560 + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  561 + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  562 + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  563 + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  564 +
  565 + MX6_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  566 + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  567 + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  568 + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL),
  569 +
  570 + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  571 +};
  572 +static void eimnor_cs_setup(void)
  573 +{
  574 + writel(0x00000120, WEIM_BASE_ADDR + 0x090);
  575 + writel(0x00610089, WEIM_BASE_ADDR + 0x000);
  576 + writel(0x00000001, WEIM_BASE_ADDR + 0x004);
  577 + writel(0x1c022000, WEIM_BASE_ADDR + 0x008);
  578 + writel(0x00000000, WEIM_BASE_ADDR + 0x00c);
  579 + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010);
  580 +}
  581 +
  582 +static void setup_eimnor(void)
  583 +{
  584 + SETUP_IOMUX_PADS(eimnor_pads);
  585 +
  586 + eimnor_cs_setup();
  587 +}
  588 +#endif
  589 +
  590 +#ifdef CONFIG_NAND_MXS
  591 +iomux_v3_cfg_t gpmi_pads[] = {
  592 + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  593 + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  594 + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  595 + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
  596 + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  597 + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  598 + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  599 + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  600 + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  601 + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  602 + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  603 + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  604 + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  605 + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  606 + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  607 +};
  608 +
  609 +static void setup_gpmi_nand(void)
  610 +{
  611 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  612 +
  613 + /* config gpmi nand iomux */
  614 + SETUP_IOMUX_PADS(gpmi_pads);
  615 +
  616 + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
  617 + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
  618 + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
  619 +
  620 + /* enable apbh clock gating */
  621 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  622 +}
  623 +#endif
  624 +
  625 +#ifdef CONFIG_FEC_MXC
  626 +int board_eth_init(bd_t *bis)
  627 +{
  628 + int ret;
  629 +
  630 + setup_iomux_fec1();
  631 +
  632 + ret = fecmxc_initialize_multi(bis, 0,
  633 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  634 + if (ret)
  635 + printf("FEC1 MXC: %s:failed\n", __func__);
  636 +
  637 + return 0;
  638 +}
  639 +
  640 +#define MAX7322_I2C_ADDR 0x68
  641 +#define MAX7322_I2C_BUS 1
  642 +
  643 +static int setup_fec(void)
  644 +{
  645 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  646 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  647 + int ret;
  648 + unsigned char value = 1;
  649 +
  650 + /* clear gpr1[13], gpr1[17] to select anatop clock */
  651 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  652 +
  653 + ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  654 + if (ret)
  655 + return ret;
  656 +
  657 +/* Reset AR8031 PHY */
  658 + gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset");
  659 + gpio_direction_output(IMX_GPIO_NR(4, 22) , 0);
  660 + udelay(500);
  661 + gpio_set_value(IMX_GPIO_NR(4, 22), 1);
  662 +
  663 +#ifdef CONFIG_DM_I2C
  664 + struct udevice *bus, *dev;
  665 + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus);
  666 + if (ret) {
  667 + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret);
  668 + return ret;
  669 + }
  670 +
  671 + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev);
  672 + if (ret) {
  673 + printf("MAX7322 Not found, ret = %d\n", ret);
  674 + return ret;
  675 + }
  676 +
  677 + /* Write 0x1 to enable O0 output, this device has no addr */
  678 + /* hence addr length is 0 */
  679 + value = 0x1;
  680 + ret = dm_i2c_write(dev, 0, &value, 1);
  681 + if (ret) {
  682 + printf("MAX7322 write failed, ret = %d\n", ret);
  683 + return ret;
  684 + }
  685 +#else
  686 + /* This is needed to drive the pads to 1.8V instead of 1.5V */
  687 + i2c_set_bus_num(MAX7322_I2C_BUS);
  688 +
  689 + if (!i2c_probe(MAX7322_I2C_ADDR)) {
  690 + /* Write 0x1 to enable O0 output, this device has no addr */
  691 + /* hence addr length is 0 */
  692 + value = 0x1;
  693 + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1))
  694 + printf("MAX7322 write failed\n");
  695 + } else {
  696 + printf("MAX7322 Not found\n");
  697 + }
  698 +#endif
  699 +
  700 + return 0;
  701 +}
  702 +
  703 +int board_phy_config(struct phy_device *phydev)
  704 +{
  705 +#ifdef CONFIG_FEC_ENABLE_MAX7322
  706 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  707 + Phy control debug reg 0 */
  708 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  709 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  710 +#endif
  711 +
  712 + /* rgmii tx clock delay enable */
  713 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  714 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  715 +
  716 + if (phydev->drv->config)
  717 + phydev->drv->config(phydev);
  718 +
  719 + return 0;
  720 +}
  721 +#endif
  722 +
  723 +int board_early_init_f(void)
  724 +{
  725 + setup_iomux_uart();
  726 + return 0;
  727 +}
  728 +
  729 +#ifdef CONFIG_USB_EHCI_MX6
  730 +#ifndef CONFIG_DM_USB
  731 +
  732 +#define USB_OTHERREGS_OFFSET 0x800
  733 +#define UCTRL_PWR_POL (1 << 9)
  734 +
  735 +iomux_v3_cfg_t const usb_otg_pads[] = {
  736 + /*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/
  737 + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  738 + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  739 +};
  740 +
  741 +static void setup_usb(void)
  742 +{
  743 + SETUP_IOMUX_PADS(usb_otg_pads);
  744 +}
  745 +
  746 +int board_usb_phy_mode(int port)
  747 +{
  748 + return USB_INIT_HOST;
  749 +}
  750 +
  751 +int board_ehci_hcd_init(int port)
  752 +{
  753 + u32 *usbnc_usb_ctrl;
  754 +
  755 + if (port >= 1)
  756 + return -EINVAL;
  757 +
  758 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  759 + port * 4);
  760 +
  761 + /* Set Power polarity */
  762 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  763 +
  764 + return 0;
  765 +}
  766 +#endif
  767 +#endif
  768 +
  769 +int board_init(void)
  770 +{
  771 + /* address of boot parameters */
  772 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  773 +
  774 +#ifdef CONFIG_SYS_I2C
  775 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  776 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  777 +#endif
  778 +
  779 +#ifdef CONFIG_FEC_MXC
  780 + setup_fec();
  781 +#endif
  782 +
  783 +#ifdef CONFIG_MXC_SPI
  784 + setup_spinor();
  785 +#endif
  786 +
  787 +#ifdef CONFIG_MTD_NOR_FLASH
  788 + setup_eimnor();
  789 +#endif
  790 +
  791 +#ifdef CONFIG_NAND_MXS
  792 + setup_gpmi_nand();
  793 +#endif
  794 +
  795 +#ifdef CONFIG_FSL_QSPI
  796 + board_qspi_init();
  797 +#endif
  798 +
  799 +#ifdef CONFIG_USB_EHCI_MX6
  800 +#ifndef CONFIG_DM_USB
  801 + setup_usb();
  802 +#endif
  803 +#endif
  804 + return 0;
  805 +}
  806 +
  807 +#ifdef CONFIG_CMD_BMODE
  808 +static const struct boot_mode board_boot_modes[] = {
  809 + /* 4 bit bus width */
  810 + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  811 + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  812 + {"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)},
  813 + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
  814 + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)},
  815 + {"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)},
  816 + {NULL, 0},
  817 +};
  818 +#endif
  819 +
  820 +int board_late_init(void)
  821 +{
  822 +#ifdef CONFIG_CMD_BMODE
  823 + add_board_boot_modes(board_boot_modes);
  824 +#endif
  825 +
  826 +#ifdef CONFIG_ENV_IS_IN_MMC
  827 + board_late_mmc_env_init();
  828 +#endif
  829 +
  830 + return 0;
  831 +}
  832 +
  833 +u32 get_board_rev(void)
  834 +{
  835 + return get_cpu_rev();
  836 +}
  837 +
  838 +int checkboard(void)
  839 +{
  840 +#ifdef CONFIG_TARGET_MX6SX_14X14_ARM2
  841 + puts("Board: MX6SX 14x14 ARM2\n");
  842 +#else
  843 + puts("Board: MX6SX 17x17 ARM2\n");
  844 +#endif
  845 +
  846 + return 0;
  847 +}
board/freescale/mx6sx_17x17_arm2/plugin.S
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6sx_17x17_ddr3_evk_ddr_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000c0000
  13 + str r1, [r0, #0x618]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x5fc]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x32c]
  18 +
  19 + ldr r1, =0x00000030
  20 + str r1, [r0, #0x300]
  21 + str r1, [r0, #0x2fc]
  22 + str r1, [r0, #0x5f4]
  23 + str r1, [r0, #0x340]
  24 +
  25 + ldr r1, =0x00000000
  26 + str r1, [r0, #0x320]
  27 + ldr r1, =0x00000030
  28 + str r1, [r0, #0x310]
  29 + str r1, [r0, #0x314]
  30 + str r1, [r0, #0x614]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x5f8]
  34 + ldr r1, =0x00000030
  35 + str r1, [r0, #0x330]
  36 + str r1, [r0, #0x334]
  37 + str r1, [r0, #0x338]
  38 + str r1, [r0, #0x33c]
  39 + ldr r1, =0x00020000
  40 + str r1, [r0, #0x608]
  41 + ldr r1, =0x00000030
  42 + str r1, [r0, #0x60c]
  43 + str r1, [r0, #0x610]
  44 + str r1, [r0, #0x61c]
  45 + str r1, [r0, #0x620]
  46 + str r1, [r0, #0x2ec]
  47 + str r1, [r0, #0x2f0]
  48 + str r1, [r0, #0x2f4]
  49 + str r1, [r0, #0x2f8]
  50 +
  51 + ldr r0, =MMDC_P0_BASE_ADDR
  52 + ldr r2, =0xa1390003
  53 + str r2, [r0, #0x800]
  54 + ldr r2, =0x00270025
  55 + str r2, [r0, #0x80c]
  56 + ldr r2, =0x001B001E
  57 + str r2, [r0, #0x810]
  58 + ldr r2, =0x4144013C
  59 + str r2, [r0, #0x83c]
  60 + ldr r2, =0x01300128
  61 + str r2, [r0, #0x840]
  62 + ldr r2, =0x4044464A
  63 + str r2, [r0, #0x848]
  64 + ldr r2, =0x3A383C34
  65 + str r2, [r0, #0x850]
  66 +
  67 + ldr r2, =0x33333333
  68 + str r2, [r0, #0x81c]
  69 + str r2, [r0, #0x820]
  70 + str r2, [r0, #0x824]
  71 + str r2, [r0, #0x828]
  72 +
  73 + ldr r2, =0x00000800
  74 + str r2, [r0, #0x8b8]
  75 + ldr r2, =0x0002002d
  76 + str r2, [r0, #0x004]
  77 + ldr r2, =0x00333030
  78 + str r2, [r0, #0x008]
  79 + ldr r2, =0x676b52f3
  80 + str r2, [r0, #0x00c]
  81 + ldr r2, =0xb66d8b63
  82 + str r2, [r0, #0x010]
  83 + ldr r2, =0x01ff00db
  84 + str r2, [r0, #0x014]
  85 + ldr r2, =0x00011740
  86 + str r2, [r0, #0x018]
  87 + ldr r2, =0x00008000
  88 + str r2, [r0, #0x01c]
  89 + ldr r2, =0x000026d2
  90 + str r2, [r0, #0x02c]
  91 + ldr r2, =0x006b1023
  92 + str r2, [r0, #0x030]
  93 + ldr r2, =0x0000005f
  94 + str r2, [r0, #0x040]
  95 + ldr r2, =0x84190000
  96 + str r2, [r0, #0x000]
  97 + ldr r2, =0x04008032
  98 + str r2, [r0, #0x01c]
  99 + ldr r2, =0x00008033
  100 + str r2, [r0, #0x01c]
  101 + ldr r2, =0x00068031
  102 + str r2, [r0, #0x01c]
  103 + ldr r2, =0x05208030
  104 + str r2, [r0, #0x01c]
  105 + ldr r2, =0x04008040
  106 + str r2, [r0, #0x01c]
  107 + ldr r2, =0x00000800
  108 + str r2, [r0, #0x020]
  109 + ldr r2, =0x00011117
  110 + str r2, [r0, #0x818]
  111 + ldr r2, =0x00000000
  112 + str r2, [r0, #0x01c]
  113 +
  114 +.endm
  115 +.macro imx6_clock_gating
  116 + ldr r0, =CCM_BASE_ADDR
  117 + ldr r1, =0xffffffff
  118 + str r1, [r0, #0x068]
  119 + str r1, [r0, #0x06c]
  120 + str r1, [r0, #0x070]
  121 + str r1, [r0, #0x074]
  122 + str r1, [r0, #0x078]
  123 + str r1, [r0, #0x07c]
  124 + str r1, [r0, #0x080]
  125 + str r1, [r0, #0x084]
  126 +.endm
  127 +
  128 +.macro imx6_qos_setting
  129 +.endm
  130 +
  131 +.macro imx6sx_14x14_lpddr2_arm2_ddr_setting
  132 + ldr r0, =IOMUXC_BASE_ADDR
  133 + ldr r1, =0x00080000
  134 + str r1, [r0, #0x618]
  135 + ldr r1, =0x00000000
  136 + str r1, [r0, #0x5fc]
  137 + ldr r1, =0x00000030
  138 + str r1, [r0, #0x32c]
  139 +
  140 + ldr r1, =0x00000028
  141 + str r1, [r0, #0x300]
  142 + str r1, [r0, #0x2fc]
  143 + str r1, [r0, #0x5f4]
  144 + str r1, [r0, #0x340]
  145 +
  146 + ldr r1, =0x00000000
  147 + str r1, [r0, #0x320]
  148 + str r1, [r0, #0x310]
  149 + str r1, [r0, #0x314]
  150 + ldr r1, =0x00000028
  151 + str r1, [r0, #0x614]
  152 +
  153 + ldr r1, =0x00020000
  154 + str r1, [r0, #0x5f8]
  155 + ldr r1, =0x00003028
  156 + str r1, [r0, #0x330]
  157 + str r1, [r0, #0x334]
  158 + str r1, [r0, #0x338]
  159 + str r1, [r0, #0x33c]
  160 + ldr r1, =0x00020000
  161 + str r1, [r0, #0x608]
  162 + ldr r1, =0x00000028
  163 + str r1, [r0, #0x60c]
  164 + str r1, [r0, #0x610]
  165 + str r1, [r0, #0x61c]
  166 + str r1, [r0, #0x620]
  167 + str r1, [r0, #0x2ec]
  168 + str r1, [r0, #0x2f0]
  169 + str r1, [r0, #0x2f4]
  170 + str r1, [r0, #0x2f8]
  171 +
  172 + ldr r0, =MMDC_P0_BASE_ADDR
  173 + ldr r2, =0x00008000
  174 + str r2, [r0, #0x1c]
  175 + ldr r2, =0x1b4700c7
  176 + str r2, [r0, #0x85c]
  177 + ldr r2, =0xa1390003
  178 + str r2, [r0, #0x800]
  179 + ldr r2, =0x00380000
  180 + str r2, [r0, #0x890]
  181 + ldr r2, =0x00000800
  182 + str r2, [r0, #0x8b8]
  183 +
  184 + ldr r2, =0x33333333
  185 + str r2, [r0, #0x81c]
  186 + str r2, [r0, #0x820]
  187 + str r2, [r0, #0x824]
  188 + str r2, [r0, #0x828]
  189 +
  190 + ldr r2, =0x51111111
  191 + str r2, [r0, #0x82c]
  192 + str r2, [r0, #0x830]
  193 + str r2, [r0, #0x834]
  194 + str r2, [r0, #0x838]
  195 +
  196 + ldr r2, =0x42424244
  197 + str r2, [r0, #0x848]
  198 + ldr r2, =0x2E30322E
  199 + str r2, [r0, #0x850]
  200 + ldr r2, =0x2492244A
  201 + str r2, [r0, #0x8c0]
  202 + ldr r2, =0x20000000
  203 + str r2, [r0, #0x83c]
  204 + ldr r2, =0x00000000
  205 + str r2, [r0, #0x840]
  206 + ldr r2, =0x00000800
  207 + str r2, [r0, #0x8b8]
  208 +
  209 + ldr r2, =0x33374133
  210 + str r2, [r0, #0x00c]
  211 + ldr r2, =0x00020024
  212 + str r2, [r0, #0x004]
  213 + ldr r2, =0x00100A42
  214 + str r2, [r0, #0x010]
  215 + ldr r2, =0x00000093
  216 + str r2, [r0, #0x014]
  217 + ldr r2, =0x00001748
  218 + str r2, [r0, #0x018]
  219 + ldr r2, =0x0f9f26d2
  220 + str r2, [r0, #0x02c]
  221 + ldr r2, =0x0000020e
  222 + str r2, [r0, #0x030]
  223 + ldr r2, =0x00190778
  224 + str r2, [r0, #0x038]
  225 + ldr r2, =0x00000000
  226 + str r2, [r0, #0x008]
  227 + ldr r2, =0x0000004f
  228 + str r2, [r0, #0x040]
  229 + ldr r2, =0xc3110000
  230 + str r2, [r0, #0x000]
  231 +
  232 + ldr r2, =0x00008010
  233 + str r2, [r0, #0x01c]
  234 + ldr r2, =0x003f8030
  235 + str r2, [r0, #0x01c]
  236 + ldr r2, =0xff0a8030
  237 + str r2, [r0, #0x01c]
  238 + ldr r2, =0x82018030
  239 + str r2, [r0, #0x01c]
  240 + ldr r2, =0x04028030
  241 + str r2, [r0, #0x01c]
  242 + ldr r2, =0x01038030
  243 + str r2, [r0, #0x01c]
  244 +
  245 + ldr r2, =0x00008018
  246 + str r2, [r0, #0x01c]
  247 + ldr r2, =0x003f8038
  248 + str r2, [r0, #0x01c]
  249 + ldr r2, =0xff0a8038
  250 + str r2, [r0, #0x01c]
  251 + ldr r2, =0x82018038
  252 + str r2, [r0, #0x01c]
  253 + ldr r2, =0x04028038
  254 + str r2, [r0, #0x01c]
  255 + ldr r2, =0x01038038
  256 + str r2, [r0, #0x01c]
  257 +
  258 + ldr r2, =0x00001800
  259 + str r2, [r0, #0x020]
  260 + ldr r2, =0x00000000
  261 + str r2, [r0, #0x818]
  262 + ldr r2, =0xa1310003
  263 + str r2, [r0, #0x800]
  264 + ldr r2, =0x00025576
  265 + str r2, [r0, #0x004]
  266 + ldr r2, =0x00011006
  267 + str r2, [r0, #0x404]
  268 + ldr r2, =0x00000000
  269 + str r2, [r0, #0x01c]
  270 +.endm
  271 +
  272 +.macro imx6_ddr_setting
  273 +#if defined(CONFIG_TARGET_MX6SX_14X14_ARM2) && defined (CONFIG_LPDDR2_BOARD)
  274 + imx6sx_14x14_lpddr2_arm2_ddr_setting
  275 +#else
  276 + imx6sx_17x17_ddr3_evk_ddr_setting
  277 +#endif
  278 +.endm
  279 +
  280 +/* include the common plugin code here */
  281 +#include <asm/arch/mx6_plugin.S>
include/configs/mx6sx_17x17_arm2.h
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX6SX_17X17_ARM2_CONFIG_H
  10 +#define __MX6SX_17X17_ARM2_CONFIG_H
  11 +
  12 +#include "mx6sx_arm2.h"
  13 +
  14 +#ifdef CONFIG_MXC_SPI /* Pin conflict between SPI-NOR and SD2 */
  15 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  16 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC3 */
  17 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  18 +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
  19 +#else
  20 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  21 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
  22 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  23 +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
  24 +#endif
  25 +
  26 +#ifdef CONFIG_MXC_SPI
  27 +#undef CONFIG_SYS_FLASH_SECT_SIZE
  28 +#undef CONFIG_SYS_MAX_FLASH_SECT
  29 +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024)
  30 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  31 +#define CONFIG_SYS_FLASH_PROTECTION
  32 +#endif
  33 +
  34 +#endif
include/configs/mx6sx_arm2.h
Diff comments   View file @ 0ca855a
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX6SX ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX6SX_ARM2_CONFIG_H
  10 +#define __MX6SX_ARM2_CONFIG_H
  11 +
  12 +#include "mx6_common.h"
  13 +
  14 +#define CONFIG_DBG_MONITOR
  15 +
  16 +/* Size of malloc() pool */
  17 +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
  18 +
  19 +#define CONFIG_IMX_THERMAL
  20 +
  21 +#define CONFIG_MXC_UART
  22 +#define CONFIG_MXC_UART_BASE UART1_BASE
  23 +
  24 +/* MMC Configs */
  25 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  26 +
  27 +#define CONFIG_FEC_MXC
  28 +#define CONFIG_MII
  29 +#define IMX_FEC_BASE ENET_BASE_ADDR
  30 +#define CONFIG_FEC_XCV_TYPE RGMII
  31 +#ifdef CONFIG_DM_ETH
  32 +#define CONFIG_ETHPRIME "eth0"
  33 +#else
  34 +#define CONFIG_ETHPRIME "FEC"
  35 +#endif
  36 +#define CONFIG_FEC_MXC_PHYADDR 1
  37 +
  38 +#define CONFIG_PHYLIB
  39 +#define CONFIG_PHY_ATHEROS
  40 +
  41 +/* I2C configs */
  42 +#ifndef CONFIG_DM_I2C
  43 +#define CONFIG_SYS_I2C
  44 +#endif
  45 +#ifdef CONFIG_CMD_I2C
  46 +#define CONFIG_SYS_I2C_MXC
  47 +#define CONFIG_SYS_I2C_SPEED 100000
  48 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  49 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  50 +#endif
  51 +
  52 +/* PMIC */
  53 +#ifndef CONFIG_DM_PMIC
  54 +#define CONFIG_POWER
  55 +#define CONFIG_POWER_I2C
  56 +#define CONFIG_POWER_PFUZE100
  57 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  58 +#endif
  59 +
  60 +#ifdef CONFIG_IMX_BOOTAUX
  61 +#ifdef CONFIG_DM_SPI
  62 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */
  63 +#define SF_QSPI2_B_CS_NUM 2
  64 +#else
  65 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 /* Set to QSPI2 B flash at default */
  66 +#define SF_QSPI2_B_CS_NUM 1
  67 +#endif
  68 +
  69 +#define UPDATE_M4_ENV \
  70 + "m4image=m4_qspi.bin\0" \
  71 + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
  72 + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
  73 + "update_m4_from_sd=" \
  74 + "if sf probe 1:${m4_qspi_cs}; then " \
  75 + "if run loadm4image; then " \
  76 + "setexpr fw_sz ${filesize} + 0xffff; " \
  77 + "setexpr fw_sz ${fw_sz} / 0x10000; " \
  78 + "setexpr fw_sz ${fw_sz} * 0x10000; " \
  79 + "sf erase 0x0 ${fw_sz}; " \
  80 + "sf write ${loadaddr} 0x0 ${filesize}; " \
  81 + "fi; " \
  82 + "fi\0" \
  83 + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
  84 +#else
  85 +#define UPDATE_M4_ENV ""
  86 +#endif
  87 +
  88 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  89 +#ifdef CONFIG_NAND_BOOT
  90 +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) "
  91 +#else
  92 +#define MFG_NAND_PARTITION ""
  93 +#endif
  94 +
  95 +#define CONFIG_MFG_ENV_SETTINGS \
  96 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  97 + "rdinit=/linuxrc " \
  98 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  99 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  100 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  101 + "g_mass_storage.iSerialNumber=\"\" "\
  102 + MFG_NAND_PARTITION \
  103 + "\0" \
  104 + "initrd_addr=0x83800000\0" \
  105 + "initrd_high=0xffffffff\0" \
  106 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  107 +
  108 +#if defined(CONFIG_NAND_BOOT)
  109 +#define CONFIG_EXTRA_ENV_SETTINGS \
  110 + CONFIG_MFG_ENV_SETTINGS \
  111 + "panel=Hannstar-XGA\0" \
  112 + "fdt_addr=0x83000000\0" \
  113 + "fdt_high=0xffffffff\0" \
  114 + "console=ttymxc0\0" \
  115 + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \
  116 + "root=ubi0:rootfs rootfstype=ubifs " \
  117 + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\
  118 + "bootcmd=nand read ${loadaddr} 0x4000000 0x800000;"\
  119 + "nand read ${fdt_addr} 0x5000000 0x100000;"\
  120 + "bootz ${loadaddr} - ${fdt_addr}\0"
  121 +
  122 +#else
  123 +#define CONFIG_EXTRA_ENV_SETTINGS \
  124 + CONFIG_MFG_ENV_SETTINGS \
  125 + UPDATE_M4_ENV \
  126 + "panel=Hannstar-XGA\0" \
  127 + "script=boot.scr\0" \
  128 + "image=zImage\0" \
  129 + "console=ttymxc0\0" \
  130 + "fdt_high=0xffffffff\0" \
  131 + "initrd_high=0xffffffff\0" \
  132 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  133 + "fdt_addr=0x83000000\0" \
  134 + "boot_fdt=try\0" \
  135 + "ip_dyn=yes\0" \
  136 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  137 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  138 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  139 + "mmcautodetect=yes\0" \
  140 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  141 + "root=${mmcroot}\0" \
  142 + "loadbootscript=" \
  143 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  144 + "bootscript=echo Running bootscript from mmc ...; " \
  145 + "source\0" \
  146 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  147 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  148 + "mmcboot=echo Booting from mmc ...; " \
  149 + "run mmcargs; " \
  150 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  151 + "if run loadfdt; then " \
  152 + "bootz ${loadaddr} - ${fdt_addr}; " \
  153 + "else " \
  154 + "if test ${boot_fdt} = try; then " \
  155 + "bootz; " \
  156 + "else " \
  157 + "echo WARN: Cannot load the DT; " \
  158 + "fi; " \
  159 + "fi; " \
  160 + "else " \
  161 + "bootz; " \
  162 + "fi;\0" \
  163 + "netargs=setenv bootargs console=${console},${baudrate} " \
  164 + "root=/dev/nfs " \
  165 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  166 + "netboot=echo Booting from net ...; " \
  167 + "run netargs; " \
  168 + "if test ${ip_dyn} = yes; then " \
  169 + "setenv get_cmd dhcp; " \
  170 + "else " \
  171 + "setenv get_cmd tftp; " \
  172 + "fi; " \
  173 + "${get_cmd} ${image}; " \
  174 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  175 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  176 + "bootz ${loadaddr} - ${fdt_addr}; " \
  177 + "else " \
  178 + "if test ${boot_fdt} = try; then " \
  179 + "bootz; " \
  180 + "else " \
  181 + "echo WARN: Cannot load the DT; " \
  182 + "fi; " \
  183 + "fi; " \
  184 + "else " \
  185 + "bootz; " \
  186 + "fi;\0"
  187 +
  188 +#define CONFIG_BOOTCOMMAND \
  189 + "mmc dev ${mmcdev};" \
  190 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  191 + "if run loadbootscript; then " \
  192 + "run bootscript; " \
  193 + "else " \
  194 + "if run loadimage; then " \
  195 + "run mmcboot; " \
  196 + "else run netboot; " \
  197 + "fi; " \
  198 + "fi; " \
  199 + "else run netboot; fi"
  200 +#endif
  201 +
  202 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  203 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
  204 +
  205 +/* Physical Memory Map */
  206 +#define CONFIG_NR_DRAM_BANKS 1
  207 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
  208 +#define PHYS_SDRAM_SIZE SZ_1G
  209 +
  210 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  211 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  212 +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
  213 +
  214 +#define CONFIG_SYS_INIT_SP_OFFSET \
  215 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  216 +#define CONFIG_SYS_INIT_SP_ADDR \
  217 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  218 +
  219 +#define CONFIG_ENV_SIZE SZ_8K
  220 +
  221 +#ifdef CONFIG_NAND_BOOT
  222 +#define CONFIG_CMD_NAND
  223 +#elif defined CONFIG_SPI_BOOT
  224 +#define CONFIG_MXC_SPI
  225 +#elif defined CONFIG_NOR_BOOT
  226 +#define CONFIG_MTD_NOR_FLASH
  227 +#endif
  228 +
  229 +#ifdef CONFIG_FSL_QSPI
  230 +#define CONFIG_SYS_FSL_QSPI_AHB
  231 +#define FSL_QSPI_FLASH_SIZE SZ_32M
  232 +#define FSL_QSPI_FLASH_NUM 2
  233 +#define CONFIG_SF_DEFAULT_BUS 1
  234 +#define CONFIG_SF_DEFAULT_CS 0
  235 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  236 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  237 +#endif
  238 +
  239 +
  240 +#ifdef CONFIG_MXC_SPI
  241 +#define CONFIG_SF_DEFAULT_BUS 3
  242 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  243 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  244 +#define CONFIG_SF_DEFAULT_CS 0
  245 +#endif
  246 +
  247 +#ifdef CONFIG_NOR_BOOT
  248 +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
  249 +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
  250 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  251 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  252 +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
  253 +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
  254 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
  255 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  256 +#endif
  257 +
  258 +#ifdef CONFIG_CMD_NAND
  259 +#define CONFIG_CMD_NAND_TRIMFFS
  260 +
  261 +/* NAND stuff */
  262 +#define CONFIG_NAND_MXS
  263 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  264 +#define CONFIG_SYS_NAND_BASE 0x40000000
  265 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  266 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  267 +
  268 +/* DMA stuff, needed for GPMI/MXS NAND support */
  269 +#define CONFIG_APBH_DMA
  270 +#define CONFIG_APBH_DMA_BURST
  271 +#define CONFIG_APBH_DMA_BURST8
  272 +#endif
  273 +
  274 +
  275 +#if defined(CONFIG_ENV_IS_IN_MMC)
  276 +#define CONFIG_ENV_OFFSET (14 * SZ_64K)
  277 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  278 +#define CONFIG_ENV_OFFSET (896 * 1024)
  279 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  280 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  281 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  282 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  283 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  284 +#elif defined(CONFIG_ENV_IS_IN_NAND)
  285 +#undef CONFIG_ENV_SIZE
  286 +#define CONFIG_ENV_OFFSET (60 << 20)
  287 +#define CONFIG_ENV_SECT_SIZE (128 << 10)
  288 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  289 +#elif defined(CONFIG_ENV_IS_IN_FLASH)
  290 +#undef CONFIG_ENV_SIZE
  291 +#define CONFIG_ENV_SIZE CONFIG_SYS_FLASH_SECT_SIZE
  292 +#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SIZE
  293 +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_FLASH_SECT_SIZE)
  294 +#endif
  295 +
  296 +#ifdef CONFIG_VIDEO
  297 +#define CONFIG_VIDEO_MXS
  298 +#define CONFIG_VIDEO_LOGO
  299 +#define CONFIG_SPLASH_SCREEN
  300 +#define CONFIG_SPLASH_SCREEN_ALIGN
  301 +#define CONFIG_BMP_16BPP
  302 +#define CONFIG_VIDEO_BMP_RLE8
  303 +#define CONFIG_VIDEO_BMP_LOGO
  304 +#define CONFIG_IMX_VIDEO_SKIP
  305 +#define CONFIG_SYS_CONSOLE_BG_COL 0x00
  306 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0
  307 +#ifdef CONFIG_VIDEO_GIS
  308 +#define CONFIG_VIDEO_CSI
  309 +#define CONFIG_VIDEO_PXP
  310 +#define CONFIG_VIDEO_VADC
  311 +#endif
  312 +#endif
  313 +
  314 +
  315 +/* USB Configs */
  316 +#ifdef CONFIG_CMD_USB
  317 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  318 +#endif
  319 +
  320 +#ifndef CONFIG_DM_USB
  321 +#define CONFIG_USB_EHCI
  322 +#define CONFIG_USB_EHCI_MX6
  323 +#define CONFIG_USB_STORAGE
  324 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  325 +#define CONFIG_MXC_USB_FLAGS 0
  326 +/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/
  327 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  328 +#endif
  329 +
  330 +#endif /* __CONFIG_H */