Eric Lee / smarc-uboot

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Commit 0d00f9b6c136634e673a7412d99df68aaa6c9a6a

Authored by Wenyou Yang
Committed by Simon Glass
1 parent 62904b7346
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

board: sama5d4ek: fix DD2 configuration 

Fix the DDR2 configuration to make SPL work.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

Showing 2 changed files with 21 additions and 2 deletions Side-by-side Diff

arch/arm/mach-at91/include/mach/atmel_mpddrc.h
Diff comments   View file @ 0d00f9b
... ... @@ -186,8 +186,13 @@
186 186 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_73 0x6
187 187 #define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_110 0x7
188 188  
189   -#define ATMEL_MPDDRC_IO_CALIBR_TZQIO 0x7f
  189 +#define ATMEL_MPDDRC_IO_CALIBR_TZQIO (0x7f << 8)
190 190 #define ATMEL_MPDDRC_IO_CALIBR_TZQIO_(x) (((x) & 0x7f) << 8)
  191 +
  192 +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP (0xf << 16)
  193 +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEP_(x) (((x) & 0xf) << 16)
  194 +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN (0xf << 20)
  195 +#define ATMEL_MPDDRC_IO_CALIBR_CALCODEN_(x) (((x) & 0xf) << 20)
191 196  
192 197 #define ATMEL_MPDDRC_IO_CALIBR_EN_CALIB (0x1 << 4)
193 198  
board/atmel/sama5d4ek/sama5d4ek.c
Diff comments   View file @ 0d00f9b
... ... @@ -230,7 +230,6 @@
230 230 ATMEL_MPDDRC_CR_NR_ROW_14 |
231 231 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
232 232 ATMEL_MPDDRC_CR_NB_8BANKS |
233   - ATMEL_MPDDRC_CR_NDQS_DISABLED |
234 233 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
235 234 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
236 235  
237 236  
... ... @@ -260,12 +259,27 @@
260 259 void mem_init(void)
261 260 {
262 261 struct atmel_mpddrc_config ddr2;
  262 + const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
  263 + u32 tmp;
263 264  
264 265 ddr2_conf(&ddr2);
265 266  
266 267 /* Enable MPDDR clock */
267 268 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
268 269 at91_system_clk_enable(AT91_PMC_DDR);
  270 +
  271 + tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE;
  272 + writel(tmp, &mpddr->rd_data_path);
  273 +
  274 + tmp = readl(&mpddr->io_calibr);
  275 + tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV |
  276 + ATMEL_MPDDRC_IO_CALIBR_TZQIO |
  277 + ATMEL_MPDDRC_IO_CALIBR_CALCODEP |
  278 + ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) |
  279 + ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 |
  280 + ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) |
  281 + ATMEL_MPDDRC_IO_CALIBR_EN_CALIB;
  282 + writel(tmp, &mpddr->io_calibr);
269 283  
270 284 /* DDRAM2 Controller initialize */
271 285 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);