driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller

fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

driver/fsl_pci: Add fsl_pci_init_port function to initialize a PCI controller
fsl_pci_init_port can be called from board specific PCI initialization routines to setup the PCI (or PCIe) controller. This will reduce code redundancy in most of the 85xx/86xx FSL board ports that setup PCI. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Poonam Aggrwal · Kumar Gala
1 parent 05f6f66474
Showing 2 changed files with 70 additions and 0 deletions Side-by-side Diff
drivers/pci/fsl_pci_init.c
include/asm-ppc/fsl_pci.h
@@ -412,6 +412,50 @@
 	}
 }
  
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+			struct pci_controller *hose, int busno)
+{
+	volatile ccsr_fsl_pci_t *pci;
+	struct pci_region *r;
+
+	pci = (ccsr_fsl_pci_t *) pci_info->regs;
+
+	/* on non-PCIe controllers we don't have pme_msg_det so this code
+	 * should do nothing since the read will return 0
+	 */
+	if (in_be32(&pci->pme_msg_det)) {
+		out_be32(&pci->pme_msg_det, 0xffffffff);
+		debug (" with errors.  Clearing.  Now 0x%08x",
+			pci->pme_msg_det);
+	}
+
+	r = hose->regions + hose->region_count;
+
+	/* outbound memory */
+	pci_set_region(r++,
+			pci_info->mem_bus,
+			pci_info->mem_phys,
+			pci_info->mem_size,
+			PCI_REGION_MEM);
+
+	/* outbound io */
+	pci_set_region(r++,
+			pci_info->io_bus,
+			pci_info->io_phys,
+			pci_info->io_size,
+			PCI_REGION_IO);
+
+	hose->region_count = r - hose->regions;
+	hose->first_busno = busno;
+
+	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+
+	printf("\n    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
+			hose->first_busno, hose->last_busno);
+
+	return(hose->last_busno + 1);
+}
+
 /* Enable inbound PCI config cycles for agent/endpoint interface */
 void fsl_pci_config_unlock(struct pci_controller *hose)
 {
@@ -154,5 +154,31 @@
 	char	res24[252];
 } ccsr_fsl_pci_t;
  
+struct fsl_pci_info {
+	unsigned long	regs;
+	pci_addr_t	mem_bus;
+	phys_size_t	mem_phys;
+	pci_size_t	mem_size;
+	pci_addr_t	io_bus;
+	phys_size_t	io_phys;
+	pci_size_t	io_size;
+	int		pci_num;
+};
+
+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
+				struct pci_controller *hose, int busno);
+
+#define SET_STD_PCIE_INFO(x, num) \
+{			\
+	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
+	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
+	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
+	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
+	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
+	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
+	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+	x.pci_num = num; \
+}
+
 #endif
...	...	@@ -412,6 +412,50 @@
412	412	}
413	413	}
414	414
	415	+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
	416	+ struct pci_controller *hose, int busno)
	417	+{
	418	+ volatile ccsr_fsl_pci_t *pci;
	419	+ struct pci_region *r;
	420	+
	421	+ pci = (ccsr_fsl_pci_t *) pci_info->regs;
	422	+
	423	+ /* on non-PCIe controllers we don't have pme_msg_det so this code
	424	+ * should do nothing since the read will return 0
	425	+ */
	426	+ if (in_be32(&pci->pme_msg_det)) {
	427	+ out_be32(&pci->pme_msg_det, 0xffffffff);
	428	+ debug (" with errors. Clearing. Now 0x%08x",
	429	+ pci->pme_msg_det);
	430	+ }
	431	+
	432	+ r = hose->regions + hose->region_count;
	433	+
	434	+ /* outbound memory */
	435	+ pci_set_region(r++,
	436	+ pci_info->mem_bus,
	437	+ pci_info->mem_phys,
	438	+ pci_info->mem_size,
	439	+ PCI_REGION_MEM);
	440	+
	441	+ /* outbound io */
	442	+ pci_set_region(r++,
	443	+ pci_info->io_bus,
	444	+ pci_info->io_phys,
	445	+ pci_info->io_size,
	446	+ PCI_REGION_IO);
	447	+
	448	+ hose->region_count = r - hose->regions;
	449	+ hose->first_busno = busno;
	450	+
	451	+ fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
	452	+
	453	+ printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
	454	+ hose->first_busno, hose->last_busno);
	455	+
	456	+ return(hose->last_busno + 1);
	457	+}
	458	+
415	459	/* Enable inbound PCI config cycles for agent/endpoint interface */
416	460	void fsl_pci_config_unlock(struct pci_controller *hose)
417	461	{
...	...	@@ -154,5 +154,31 @@
154	154	char res24[252];
155	155	} ccsr_fsl_pci_t;
156	156
	157	+struct fsl_pci_info {
	158	+ unsigned long regs;
	159	+ pci_addr_t mem_bus;
	160	+ phys_size_t mem_phys;
	161	+ pci_size_t mem_size;
	162	+ pci_addr_t io_bus;
	163	+ phys_size_t io_phys;
	164	+ pci_size_t io_size;
	165	+ int pci_num;
	166	+};
	167	+
	168	+int fsl_pci_init_port(struct fsl_pci_info *pci_info,
	169	+ struct pci_controller *hose, int busno);
	170	+
	171	+#define SET_STD_PCIE_INFO(x, num) \
	172	+{ \
	173	+ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
	174	+ x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
	175	+ x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
	176	+ x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
	177	+ x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
	178	+ x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
	179	+ x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
	180	+ x.pci_num = num; \
	181	+}
	182	+
157	183	#endif