Eric Lee / smarc-uboot

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Commit 0dc78ff857337a82d39d7e4390e317ffbc93097f

Authored by Nikhil Badola
Committed by York Sun
1 parent 7fc63cca61
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers: usb: fsl: Workaround for Erratum A004477 

Add a delay of 1 microsecond before issuing soft reset to the
controller to let ongoing ULPI transaction complete.
This prevents corruption of ULPI Function Control Register which
eventually prevents phy clock from entering to low power mode

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 49 additions and 0 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/cmd_errata.c
Diff comments   View file @ 0dc78ff
... ... @@ -299,6 +299,10 @@
299 299 if (has_erratum_a007798())
300 300 puts("Work-around for Erratum A007798 enabled\n");
301 301 #endif
  302 +#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
  303 + if (has_erratum_a004477())
  304 + puts("Work-around for Erratum A004477 enabled\n");
  305 +#endif
302 306 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
303 307 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
304 308 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ 0dc78ff
... ... @@ -163,6 +163,7 @@
163 163 #define CONFIG_SYS_FSL_ERRATUM_A004508
164 164 #define CONFIG_SYS_FSL_ERRATUM_A007075
165 165 #define CONFIG_SYS_FSL_ERRATUM_A006261
  166 +#define CONFIG_SYS_FSL_ERRATUM_A004477
166 167 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
167 168 #define CONFIG_ESDHC_HC_BLK_ADDR
168 169  
... ... @@ -294,6 +295,7 @@
294 295 #define CONFIG_FSL_SATA_ERRATUM_A001
295 296 #define CONFIG_SYS_FSL_ERRATUM_A004508
296 297 #define CONFIG_SYS_FSL_ERRATUM_A005125
  298 +#define CONFIG_SYS_FSL_ERRATUM_A004477
297 299  
298 300 #elif defined(CONFIG_P1023)
299 301 #define CONFIG_MAX_CPUS 2
... ... @@ -374,6 +376,7 @@
374 376 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
375 377 #define CONFIG_SYS_FSL_ERRATUM_A004508
376 378 #define CONFIG_SYS_FSL_ERRATUM_A005125
  379 +#define CONFIG_SYS_FSL_ERRATUM_A004477
377 380 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
378 381  
379 382 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
... ... @@ -591,6 +594,7 @@
591 594 #define CONFIG_NAND_FSL_IFC
592 595 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
593 596 #define CONFIG_SYS_FSL_ERRATUM_A005125
  597 +#define CONFIG_SYS_FSL_ERRATUM_A004477
594 598 #define CONFIG_ESDHC_HC_BLK_ADDR
595 599  
596 600 #elif defined(CONFIG_BSC9132)
... ... @@ -615,6 +619,7 @@
615 619 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
616 620 #define CONFIG_SYS_FSL_ERRATUM_A005125
617 621 #define CONFIG_SYS_FSL_ERRATUM_A005434
  622 +#define CONFIG_SYS_FSL_ERRATUM_A004477
618 623 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
619 624 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
620 625 #define CONFIG_ESDHC_HC_BLK_ADDR
... ... @@ -723,6 +728,7 @@
723 728 #define CONFIG_SYS_FSL_ERRATUM_A006475
724 729 #define CONFIG_SYS_FSL_ERRATUM_A006384
725 730 #define CONFIG_SYS_FSL_ERRATUM_A007212
  731 +#define CONFIG_SYS_FSL_ERRATUM_A004477
726 732 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
727 733 #define CONFIG_SYS_FSL_SFP_VER_3_0
728 734  
drivers/usb/host/ehci-fsl.c
Diff comments   View file @ 0dc78ff
... ... @@ -138,6 +138,16 @@
138 138 if (has_erratum_a007798())
139 139 set_txfifothresh(ehci, TXFIFOTHRESH);
140 140  
  141 + if (has_erratum_a004477()) {
  142 + /*
  143 + * When reset is issued while any ULPI transaction is ongoing
  144 + * then it may result to corruption of ULPI Function Control
  145 + * Register which eventually causes phy clock to enter low
  146 + * power mode which stops the clock. Thus delay is required
  147 + * before reset to let ongoing ULPI transaction complete.
  148 + */
  149 + udelay(1);
  150 + }
141 151 return 0;
142 152 }
143 153  
... ... @@ -209,6 +209,30 @@
209 209 return false;
210 210 }
211 211  
  212 +static inline bool has_erratum_a004477(void)
  213 +{
  214 + u32 svr = get_svr();
  215 + u32 soc = SVR_SOC_VER(svr);
  216 +
  217 + switch (soc) {
  218 + case SVR_P1010:
  219 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  220 + case SVR_P1022:
  221 + case SVR_9131:
  222 + case SVR_9132:
  223 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
  224 + case SVR_P2020:
  225 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
  226 + IS_SVR_REV(svr, 2, 1);
  227 + case SVR_B4860:
  228 + case SVR_B4420:
  229 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  230 + case SVR_P4080:
  231 + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
  232 + }
  233 +
  234 + return false;
  235 +}
212 236 #else
213 237 static inline bool has_dual_phy(void)
214 238 {
... ... @@ -236,6 +260,11 @@
236 260 }
237 261  
238 262 static inline bool has_erratum_a005697(void)
  263 +{
  264 + return false;
  265 +}
  266 +
  267 +static inline bool has_erratum_a004477(void)
239 268 {
240 269 return false;
241 270 }