Fix "i2c sdram" command for DDR2 DIMMs

Many of the SPD bytes for DDR2 SDRAM are not interpreted correctly by the "i2c sdram" command. This patch provides correct alternative interpretations when DDR2 memory is detected. Signed-off-by: Larry Johnson <lrj@acm.org>

Fix "i2c sdram" command for DDR2 DIMMs
Many of the SPD bytes for DDR2 SDRAM are not interpreted correctly by the "i2c sdram" command. This patch provides correct alternative interpretations when DDR2 memory is detected. Signed-off-by: Larry Johnson <lrj@acm.org>
Larry Johnson · Wolfgang Denk
1 parent 64134f0112
Showing 1 changed file with 496 additions and 119 deletions Side-by-side Diff
common/cmd_i2c.c
@@ -662,6 +662,7 @@
  */
 int do_sdram  ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
+	enum {unknown, EDO, SDRAM, DDR2} type;
 	u_char	chip;
 	u_char	data[128];
 	u_char	cksum;
@@ -696,10 +697,22 @@
 	printf("Serial memory size           0x%02X\n", 1 << data[1]);
 	puts ("Memory type                  ");
 	switch(data[2]) {
-		case 2:  puts ("EDO\n");	break;
-		case 4:  puts ("SDRAM\n");	break;
-		case 8:  puts ("DDR2\n");	break;
-		default: puts ("unknown\n");	break;
+	case 2:
+		type = EDO;
+		puts ("EDO\n");
+		break;
+	case 4:
+		type = SDRAM;
+		puts ("SDRAM\n");
+		break;
+	case 8:
+		type = DDR2;
+		puts ("DDR2\n");
+		break;
+	default:
+		type = unknown;
+		puts ("unknown\n");
+		break;
 	}
 	puts ("Row address bits             ");
 	if ((data[3] & 0x00F0) == 0)
  
  
  
@@ -711,22 +724,89 @@
 		printf("%d\n", data[4] & 0x0F);
 	else
 		printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
-	printf("Module rows                  %d\n", data[5]);
-	printf("Module data width            %d bits\n", (data[7] << 8) | data[6]);
+
+	switch (type) {
+	case DDR2:
+		printf("Number of ranks              %d\n",
+		       (data[5] & 0x07) + 1);
+		break;
+	default:
+		printf("Module rows                  %d\n", data[5]);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("Module data width            %d bits\n", data[6]);
+		break;
+	default:
+		printf("Module data width            %d bits\n",
+		       (data[7] << 8) | data[6]);
+		break;
+	}
+
 	puts ("Interface signal levels      ");
 	switch(data[8]) {
-		case 0:  puts ("5.0v/TTL\n");	break;
+		case 0:  puts ("TTL 5.0 V\n");	break;
 		case 1:  puts ("LVTTL\n");	break;
-		case 2:  puts ("HSTL 1.5\n");	break;
-		case 3:  puts ("SSTL 3.3\n");	break;
-		case 4:  puts ("SSTL 2.5\n");	break;
-		case 5:  puts ("SSTL 1.8\n");	break;
+		case 2:  puts ("HSTL 1.5 V\n");	break;
+		case 3:  puts ("SSTL 3.3 V\n");	break;
+		case 4:  puts ("SSTL 2.5 V\n");	break;
+		case 5:  puts ("SSTL 1.8 V\n");	break;
 		default: puts ("unknown\n");	break;
 	}
-	printf("SDRAM cycle time             %d.%d nS\n",
-		(data[9] >> 4) & 0x0F, data[9] & 0x0F);
-	printf("SDRAM access time            %d.%d nS\n",
-		(data[10] >> 4) & 0x0F, data[10] & 0x0F);
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM cycle time             %d.",
+		       (data[9] >> 4) & 0x0F);
+		switch (data[9] & 0x0F) {
+		case 0x0:
+		case 0x1:
+		case 0x2:
+		case 0x3:
+		case 0x4:
+		case 0x5:
+		case 0x6:
+		case 0x7:
+		case 0x8:
+		case 0x9:
+			printf("%d ns\n", data[9] & 0x0F);
+			break;
+		case 0xA:
+			puts("25 ns\n");
+			break;
+		case 0xB:
+			puts("33 ns\n");
+			break;
+		case 0xC:
+			puts("66 ns\n");
+			break;
+		case 0xD:
+			puts("75 ns\n");
+			break;
+		default:
+			puts("?? ns\n");
+			break;
+		}
+		break;
+	default:
+		printf("SDRAM cycle time             %d.%d nS\n",
+		       (data[9] >> 4) & 0x0F, data[9] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM access time            0.%d%d ns\n",
+		       (data[10] >> 4) & 0x0F, data[10] & 0x0F);
+		break;
+	default:
+		printf("SDRAM access time            %d.%d nS\n",
+		       (data[10] >> 4) & 0x0F, data[10] & 0x0F);
+		break;
+	}
+
 	puts ("EDC configuration            ");
 	switch(data[11]) {
 		case 0:  puts ("None\n");	break;
  
  
  
@@ -739,28 +819,51 @@
 	else
 		puts ("Self refresh, rate           ");
 	switch(data[12] & 0x7F) {
-		case 0:  puts ("15.625uS\n");	break;
-		case 1:  puts ("3.9uS\n");	break;
-		case 2:  puts ("7.8uS\n");	break;
-		case 3:  puts ("31.3uS\n");	break;
-		case 4:  puts ("62.5uS\n");	break;
-		case 5:  puts ("125uS\n");	break;
+		case 0:  puts ("15.625 uS\n");	break;
+		case 1:  puts ("3.9 uS\n");	break;
+		case 2:  puts ("7.8 uS \n");	break;
+		case 3:  puts ("31.3 uS\n");	break;
+		case 4:  puts ("62.5 uS\n");	break;
+		case 5:  puts ("125 uS\n");	break;
 		default: puts ("unknown\n");	break;
 	}
-	printf("SDRAM width (primary)        %d\n", data[13] & 0x7F);
-	if ((data[13] & 0x80) != 0) {
-		printf("  (second bank)              %d\n",
-			2 * (data[13] & 0x7F));
-	}
-	if (data[14] != 0) {
-		printf("EDC width                    %d\n",
-			data[14] & 0x7F);
-		if ((data[14] & 0x80) != 0)
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM width (primary)        %d\n", data[13]);
+		break;
+	default:
+		printf("SDRAM width (primary)        %d\n", data[13] & 0x7F);
+		if ((data[13] & 0x80) != 0) {
 			printf("  (second bank)              %d\n",
-				2 * (data[14] & 0x7F));
+			       2 * (data[13] & 0x7F));
+		}
+		break;
 	}
-	printf("Min clock delay, back-to-back random column addresses %d\n",
-		data[15]);
+
+	switch (type) {
+	case DDR2:
+		if (data[14] != 0)
+			printf("EDC width                    %d\n", data[14]);
+		break;
+	default:
+		if (data[14] != 0) {
+			printf("EDC width                    %d\n",
+			       data[14] & 0x7F);
+
+			if ((data[14] & 0x80) != 0) {
+				printf("  (second bank)              %d\n",
+				       2 * (data[14] & 0x7F));
+			}
+		}
+		break;
+	}
+
+	if (DDR2 != type ) {
+		printf("Min clock delay, back-to-back random column addresses "
+		       "%d\n", data[15]);
+	}
+
 	puts ("Burst length(s)             ");
 	if (data[16] & 0x80) puts (" Page");
 	if (data[16] & 0x08) puts (" 8");
  
@@ -769,91 +872,363 @@
 	if (data[16] & 0x01) puts (" 1");
 	putc ('\n');
 	printf("Number of banks              %d\n", data[17]);
-	puts ("CAS latency(s)              ");
-	if (data[18] & 0x80) puts (" TBD");
-	if (data[18] & 0x40) puts (" 7");
-	if (data[18] & 0x20) puts (" 6");
-	if (data[18] & 0x10) puts (" 5");
-	if (data[18] & 0x08) puts (" 4");
-	if (data[18] & 0x04) puts (" 3");
-	if (data[18] & 0x02) puts (" 2");
-	if (data[18] & 0x01) puts (" 1");
-	putc ('\n');
-	puts ("CS latency(s)               ");
-	if (data[19] & 0x80) puts (" TBD");
-	if (data[19] & 0x40) puts (" 6");
-	if (data[19] & 0x20) puts (" 5");
-	if (data[19] & 0x10) puts (" 4");
-	if (data[19] & 0x08) puts (" 3");
-	if (data[19] & 0x04) puts (" 2");
-	if (data[19] & 0x02) puts (" 1");
-	if (data[19] & 0x01) puts (" 0");
-	putc ('\n');
-	puts ("WE latency(s)               ");
-	if (data[20] & 0x80) puts (" TBD");
-	if (data[20] & 0x40) puts (" 6");
-	if (data[20] & 0x20) puts (" 5");
-	if (data[20] & 0x10) puts (" 4");
-	if (data[20] & 0x08) puts (" 3");
-	if (data[20] & 0x04) puts (" 2");
-	if (data[20] & 0x02) puts (" 1");
-	if (data[20] & 0x01) puts (" 0");
-	putc ('\n');
-	puts ("Module attributes:\n");
-	if (!data[21])       puts ("  (none)\n");
-	if (data[21] & 0x80) puts ("  TBD (bit 7)\n");
-	if (data[21] & 0x40) puts ("  Redundant row address\n");
-	if (data[21] & 0x20) puts ("  Differential clock input\n");
-	if (data[21] & 0x10) puts ("  Registerd DQMB inputs\n");
-	if (data[21] & 0x08) puts ("  Buffered DQMB inputs\n");
-	if (data[21] & 0x04) puts ("  On-card PLL\n");
-	if (data[21] & 0x02) puts ("  Registered address/control lines\n");
-	if (data[21] & 0x01) puts ("  Buffered address/control lines\n");
-	puts ("Device attributes:\n");
-	if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
-	if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
-	if (data[22] & 0x20) puts ("  Upper Vcc tolerance 5%\n");
-	else                 puts ("  Upper Vcc tolerance 10%\n");
-	if (data[22] & 0x10) puts ("  Lower Vcc tolerance 5%\n");
-	else                 puts ("  Lower Vcc tolerance 10%\n");
-	if (data[22] & 0x08) puts ("  Supports write1/read burst\n");
-	if (data[22] & 0x04) puts ("  Supports precharge all\n");
-	if (data[22] & 0x02) puts ("  Supports auto precharge\n");
-	if (data[22] & 0x01) puts ("  Supports early RAS# precharge\n");
-	printf("SDRAM cycle time (2nd highest CAS latency)        %d.%d nS\n",
-		(data[23] >> 4) & 0x0F, data[23] & 0x0F);
-	printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n",
-		(data[24] >> 4) & 0x0F, data[24] & 0x0F);
-	printf("SDRAM cycle time (3rd highest CAS latency)        %d.%d nS\n",
-		(data[25] >> 4) & 0x0F, data[25] & 0x0F);
-	printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n",
-		(data[26] >> 4) & 0x0F, data[26] & 0x0F);
-	printf("Minimum row precharge        %d nS\n", data[27]);
-	printf("Row active to row active min %d nS\n", data[28]);
-	printf("RAS to CAS delay min         %d nS\n", data[29]);
+
+	switch (type) {
+	case DDR2:
+		puts ("CAS latency(s)              ");
+		if (data[18] & 0x83) puts (" TBD");
+		if (data[18] & 0x40) puts (" 6");
+		if (data[18] & 0x20) puts (" 5");
+		if (data[18] & 0x10) puts (" 4");
+		if (data[18] & 0x08) puts (" 3");
+		if (data[18] & 0x04) puts (" 2");
+		putc ('\n');
+		break;
+	default:
+		puts ("CAS latency(s)              ");
+		if (data[18] & 0x80) puts (" TBD");
+		if (data[18] & 0x40) puts (" 7");
+		if (data[18] & 0x20) puts (" 6");
+		if (data[18] & 0x10) puts (" 5");
+		if (data[18] & 0x08) puts (" 4");
+		if (data[18] & 0x04) puts (" 3");
+		if (data[18] & 0x02) puts (" 2");
+		if (data[18] & 0x01) puts (" 1");
+		putc ('\n');
+		break;
+	}
+
+	if (DDR2 != type) {
+		puts ("CS latency(s)               ");
+		if (data[19] & 0x80) puts (" TBD");
+		if (data[19] & 0x40) puts (" 6");
+		if (data[19] & 0x20) puts (" 5");
+		if (data[19] & 0x10) puts (" 4");
+		if (data[19] & 0x08) puts (" 3");
+		if (data[19] & 0x04) puts (" 2");
+		if (data[19] & 0x02) puts (" 1");
+		if (data[19] & 0x01) puts (" 0");
+		putc ('\n');
+	}
+
+	if (DDR2 != type) {
+		puts ("WE latency(s)               ");
+		if (data[20] & 0x80) puts (" TBD");
+		if (data[20] & 0x40) puts (" 6");
+		if (data[20] & 0x20) puts (" 5");
+		if (data[20] & 0x10) puts (" 4");
+		if (data[20] & 0x08) puts (" 3");
+		if (data[20] & 0x04) puts (" 2");
+		if (data[20] & 0x02) puts (" 1");
+		if (data[20] & 0x01) puts (" 0");
+		putc ('\n');
+	}
+
+	switch (type) {
+	case DDR2:
+		puts ("Module attributes:\n");
+		if (data[21] & 0x80)
+			puts ("  TBD (bit 7)\n");
+		if (data[21] & 0x40)
+			puts ("  Analysis probe installed\n");
+		if (data[21] & 0x20)
+			puts ("  TBD (bit 5)\n");
+		if (data[21] & 0x10)
+			puts ("  FET switch external enable\n");
+		printf("  %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
+		if (data[20] & 0x11) {
+			printf("  %d active registers on DIMM\n",
+			       (data[21] & 0x03) + 1);
+		}
+		break;
+	default:
+		puts ("Module attributes:\n");
+		if (!data[21])
+			puts ("  (none)\n");
+		if (data[21] & 0x80)
+			puts ("  TBD (bit 7)\n");
+		if (data[21] & 0x40)
+			puts ("  Redundant row address\n");
+		if (data[21] & 0x20)
+			puts ("  Differential clock input\n");
+		if (data[21] & 0x10)
+			puts ("  Registerd DQMB inputs\n");
+		if (data[21] & 0x08)
+			puts ("  Buffered DQMB inputs\n");
+		if (data[21] & 0x04)
+			puts ("  On-card PLL\n");
+		if (data[21] & 0x02)
+			puts ("  Registered address/control lines\n");
+		if (data[21] & 0x01)
+			puts ("  Buffered address/control lines\n");
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
+		if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
+		if (data[22] & 0x20) puts ("  TBD (bit 5)\n");
+		if (data[22] & 0x10) puts ("  TBD (bit 4)\n");
+		if (data[22] & 0x08) puts ("  TBD (bit 3)\n");
+		if (data[22] & 0x04)
+			puts ("  Supports parital array self refresh\n");
+		if (data[22] & 0x02)
+			puts ("  Supports 50 ohm ODT\n");
+		if (data[22] & 0x01)
+			puts ("  Supports weak driver\n");
+		break;
+	default:
+		puts ("Device attributes:\n");
+		if (data[22] & 0x80) puts ("  TBD (bit 7)\n");
+		if (data[22] & 0x40) puts ("  TBD (bit 6)\n");
+		if (data[22] & 0x20) puts ("  Upper Vcc tolerance 5%\n");
+		else                 puts ("  Upper Vcc tolerance 10%\n");
+		if (data[22] & 0x10) puts ("  Lower Vcc tolerance 5%\n");
+		else                 puts ("  Lower Vcc tolerance 10%\n");
+		if (data[22] & 0x08) puts ("  Supports write1/read burst\n");
+		if (data[22] & 0x04) puts ("  Supports precharge all\n");
+		if (data[22] & 0x02) puts ("  Supports auto precharge\n");
+		if (data[22] & 0x01) puts ("  Supports early RAS# precharge\n");
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM cycle time (2nd highest CAS latency)        %d.",
+		       (data[23] >> 4) & 0x0F);
+
+		switch (data[23] & 0x0F) {
+		case 0x0:
+		case 0x1:
+		case 0x2:
+		case 0x3:
+		case 0x4:
+		case 0x5:
+		case 0x6:
+		case 0x7:
+		case 0x8:
+		case 0x9:
+			printf("%d ns\n", data[23] & 0x0F);
+			break;
+		case 0xA:
+			puts("25 ns\n");
+			break;
+		case 0xB:
+			puts("33 ns\n");
+			break;
+		case 0xC:
+			puts("66 ns\n");
+			break;
+		case 0xD:
+			puts("75 ns\n");
+			break;
+		default:
+			puts("?? ns\n");
+			break;
+		}
+		break;
+	default:
+		printf("SDRAM cycle time (2nd highest CAS latency)        %d."
+		       "%d nS\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM access from clock (2nd highest CAS latency) 0."
+		       "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+		break;
+	default:
+		printf("SDRAM access from clock (2nd highest CAS latency) %d."
+		       "%d nS\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM cycle time (3rd highest CAS latency)        %d.",
+		       (data[25] >> 4) & 0x0F);
+
+		switch (data[25] & 0x0F) {
+		case 0x0:
+		case 0x1:
+		case 0x2:
+		case 0x3:
+		case 0x4:
+		case 0x5:
+		case 0x6:
+		case 0x7:
+		case 0x8:
+		case 0x9:
+			printf("%d ns\n", data[25] & 0x0F);
+			break;
+		case 0xA:
+			puts("25 ns\n");
+			break;
+		case 0xB:
+			puts("33 ns\n");
+			break;
+		case 0xC:
+			puts("66 ns\n");
+			break;
+		case 0xD:
+			puts("75 ns\n");
+			break;
+		default:
+			puts("?? ns\n");
+			break;
+		}
+		break;
+	default:
+		printf("SDRAM cycle time (3rd highest CAS latency)        %d."
+		       "%d nS\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("SDRAM access from clock (3rd highest CAS latency) 0."
+		       "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+		break;
+	default:
+		printf("SDRAM access from clock (3rd highest CAS latency) %d."
+		       "%d nS\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("Minimum row precharge        %d", data[27] >> 2);
+		switch (data[27] & 0x03) {
+			case 0x0: puts(".00 ns\n"); break;
+			case 0x1: puts(".25 ns\n"); break;
+			case 0x2: puts(".50 ns\n"); break;
+			case 0x3: puts(".75 ns\n"); break;
+		}
+		break;
+	default:
+		printf("Minimum row precharge        %d nS\n", data[27]);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("Row active to row active min %d", data[28] >> 2);
+		switch (data[28] & 0x03) {
+			case 0x0: puts(".00 ns\n"); break;
+			case 0x1: puts(".25 ns\n"); break;
+			case 0x2: puts(".50 ns\n"); break;
+			case 0x3: puts(".75 ns\n"); break;
+		}
+		break;
+	default:
+		printf("Row active to row active min %d nS\n", data[28]);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("RAS to CAS delay min         %d", data[29] >> 2);
+		switch (data[29] & 0x03) {
+			case 0x0: puts(".00 ns\n"); break;
+			case 0x1: puts(".25 ns\n"); break;
+			case 0x2: puts(".50 ns\n"); break;
+			case 0x3: puts(".75 ns\n"); break;
+		}
+		break;
+	default:
+		printf("RAS to CAS delay min         %d nS\n", data[29]);
+		break;
+	}
+
 	printf("Minimum RAS pulse width      %d nS\n", data[30]);
-	puts ("Density of each row         ");
-	if (data[31] & 0x80) puts (" 512");
-	if (data[31] & 0x40) puts (" 256");
-	if (data[31] & 0x20) puts (" 128");
-	if (data[31] & 0x10) puts (" 64");
-	if (data[31] & 0x08) puts (" 32");
-	if (data[31] & 0x04) puts (" 16");
-	if (data[31] & 0x02) puts (" 8");
-	if (data[31] & 0x01) puts (" 4");
-	puts ("MByte\n");
-	printf("Command and Address setup    %c%d.%d nS\n",
-		(data[32] & 0x80) ? '-' : '+',
-		(data[32] >> 4) & 0x07, data[32] & 0x0F);
-	printf("Command and Address hold     %c%d.%d nS\n",
-		(data[33] & 0x80) ? '-' : '+',
-		(data[33] >> 4) & 0x07, data[33] & 0x0F);
-	printf("Data signal input setup      %c%d.%d nS\n",
-		(data[34] & 0x80) ? '-' : '+',
-		(data[34] >> 4) & 0x07, data[34] & 0x0F);
-	printf("Data signal input hold       %c%d.%d nS\n",
-		(data[35] & 0x80) ? '-' : '+',
-		(data[35] >> 4) & 0x07, data[35] & 0x0F);
+
+	switch (type) {
+	case DDR2:
+		puts ("Density of each row         ");
+		if (data[31] & 0x80) puts (" 512 MiB\n");
+		if (data[31] & 0x40) puts (" 256 MiB\n");
+		if (data[31] & 0x20) puts (" 128 MiB\n");
+		if (data[31] & 0x10) puts (" 16 GiB\n");
+		if (data[31] & 0x08) puts (" 8 GiB\n");
+		if (data[31] & 0x04) puts (" 4 GiB\n");
+		if (data[31] & 0x02) puts (" 2 GiB\n");
+		if (data[31] & 0x01) puts (" 1 GiB\n");
+		break;
+	default:
+		puts ("Density of each row         ");
+		if (data[31] & 0x80) puts (" 512 MiB\n");
+		if (data[31] & 0x40) puts (" 256 MiB\n");
+		if (data[31] & 0x20) puts (" 128 MiB\n");
+		if (data[31] & 0x10) puts (" 64 MiB\n");
+		if (data[31] & 0x08) puts (" 32 MiB\n");
+		if (data[31] & 0x04) puts (" 16 MiB\n");
+		if (data[31] & 0x02) puts (" 8 MiB\n");
+		if (data[31] & 0x01) puts (" 4 MiB\n");
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		puts("Command and Address setup    ");
+		if (data[32] >= 0xA0) {
+			printf("1.%d%d ns\n",
+			       ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
+		} else {
+			printf("0.%d%d ns\n",
+			       ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
+		}
+		break;
+	default:
+		printf("Command and Address setup    %c%d.%d nS\n",
+		       (data[32] & 0x80) ? '-' : '+',
+		       (data[32] >> 4) & 0x07, data[32] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		puts("Command and Address hold     ");
+		if (data[33] >= 0xA0) {
+			printf("1.%d%d ns\n",
+			       ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
+		} else {
+			printf("0.%d%d ns\n",
+			       ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
+		}
+		break;
+	default:
+		printf("Command and Address hold     %c%d.%d nS\n",
+		       (data[33] & 0x80) ? '-' : '+',
+		       (data[33] >> 4) & 0x07, data[33] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("Data signal input setup      0.%d%d ns\n",
+		       (data[34] >> 4) & 0x0F, data[34] & 0x0F);
+		break;
+	default:
+		printf("Data signal input setup      %c%d.%d nS\n",
+		       (data[34] & 0x80) ? '-' : '+',
+		       (data[34] >> 4) & 0x07, data[34] & 0x0F);
+		break;
+	}
+
+	switch (type) {
+	case DDR2:
+		printf("Data signal input hold       0.%d%d ns\n",
+		       (data[35] >> 4) & 0x0F, data[35] & 0x0F);
+		break;
+	default:
+		printf("Data signal input hold       %c%d.%d nS\n",
+		       (data[35] & 0x80) ? '-' : '+',
+		       (data[35] >> 4) & 0x07, data[35] & 0x0F);
+		break;
+	}
+
 	puts ("Manufacturer's JEDEC ID      ");
 	for (j = 64; j <= 71; j++)
 		printf("%02X ", data[j]);
  
@@ -869,9 +1244,11 @@
 	for (j = 95; j <= 98; j++)
 		printf("%02X ", data[j]);
 	putc ('\n');
-	printf("Speed rating                 PC%d\n",
-		data[126] == 0x66 ? 66 : data[126]);
  
+	if (DDR2 != type) {
+		printf("Speed rating                 PC%d\n",
+		       data[126] == 0x66 ? 66 : data[126]);
+	}
 	return 0;
 }
 #endif
...	...	@@ -662,6 +662,7 @@
662	662	*/
663	663	int do_sdram ( cmd_tbl_t cmdtp, int flag, int argc, char argv[])
664	664	{
	665	+ enum {unknown, EDO, SDRAM, DDR2} type;
665	666	u_char chip;
666	667	u_char data[128];
667	668	u_char cksum;
...	...	@@ -696,10 +697,22 @@
696	697	printf("Serial memory size 0x%02X\n", 1 << data[1]);
697	698	puts ("Memory type ");
698	699	switch(data[2]) {
699		- case 2: puts ("EDO\n"); break;
700		- case 4: puts ("SDRAM\n"); break;
701		- case 8: puts ("DDR2\n"); break;
702		- default: puts ("unknown\n"); break;
	700	+ case 2:
	701	+ type = EDO;
	702	+ puts ("EDO\n");
	703	+ break;
	704	+ case 4:
	705	+ type = SDRAM;
	706	+ puts ("SDRAM\n");
	707	+ break;
	708	+ case 8:
	709	+ type = DDR2;
	710	+ puts ("DDR2\n");
	711	+ break;
	712	+ default:
	713	+ type = unknown;
	714	+ puts ("unknown\n");
	715	+ break;
703	716	}
704	717	puts ("Row address bits ");
705	718	if ((data[3] & 0x00F0) == 0)
706	719
707	720
708	721
...	...	@@ -711,22 +724,89 @@
711	724	printf("%d\n", data[4] & 0x0F);
712	725	else
713	726	printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F);
714		- printf("Module rows %d\n", data[5]);
715		- printf("Module data width %d bits\n", (data[7] << 8) \| data[6]);
	727	+
	728	+ switch (type) {
	729	+ case DDR2:
	730	+ printf("Number of ranks %d\n",
	731	+ (data[5] & 0x07) + 1);
	732	+ break;
	733	+ default:
	734	+ printf("Module rows %d\n", data[5]);
	735	+ break;
	736	+ }
	737	+
	738	+ switch (type) {
	739	+ case DDR2:
	740	+ printf("Module data width %d bits\n", data[6]);
	741	+ break;
	742	+ default:
	743	+ printf("Module data width %d bits\n",
	744	+ (data[7] << 8) \| data[6]);
	745	+ break;
	746	+ }
	747	+
716	748	puts ("Interface signal levels ");
717	749	switch(data[8]) {
718		- case 0: puts ("5.0v/TTL\n"); break;
	750	+ case 0: puts ("TTL 5.0 V\n"); break;
719	751	case 1: puts ("LVTTL\n"); break;
720		- case 2: puts ("HSTL 1.5\n"); break;
721		- case 3: puts ("SSTL 3.3\n"); break;
722		- case 4: puts ("SSTL 2.5\n"); break;
723		- case 5: puts ("SSTL 1.8\n"); break;
	752	+ case 2: puts ("HSTL 1.5 V\n"); break;
	753	+ case 3: puts ("SSTL 3.3 V\n"); break;
	754	+ case 4: puts ("SSTL 2.5 V\n"); break;
	755	+ case 5: puts ("SSTL 1.8 V\n"); break;
724	756	default: puts ("unknown\n"); break;
725	757	}
726		- printf("SDRAM cycle time %d.%d nS\n",
727		- (data[9] >> 4) & 0x0F, data[9] & 0x0F);
728		- printf("SDRAM access time %d.%d nS\n",
729		- (data[10] >> 4) & 0x0F, data[10] & 0x0F);
	758	+
	759	+ switch (type) {
	760	+ case DDR2:
	761	+ printf("SDRAM cycle time %d.",
	762	+ (data[9] >> 4) & 0x0F);
	763	+ switch (data[9] & 0x0F) {
	764	+ case 0x0:
	765	+ case 0x1:
	766	+ case 0x2:
	767	+ case 0x3:
	768	+ case 0x4:
	769	+ case 0x5:
	770	+ case 0x6:
	771	+ case 0x7:
	772	+ case 0x8:
	773	+ case 0x9:
	774	+ printf("%d ns\n", data[9] & 0x0F);
	775	+ break;
	776	+ case 0xA:
	777	+ puts("25 ns\n");
	778	+ break;
	779	+ case 0xB:
	780	+ puts("33 ns\n");
	781	+ break;
	782	+ case 0xC:
	783	+ puts("66 ns\n");
	784	+ break;
	785	+ case 0xD:
	786	+ puts("75 ns\n");
	787	+ break;
	788	+ default:
	789	+ puts("?? ns\n");
	790	+ break;
	791	+ }
	792	+ break;
	793	+ default:
	794	+ printf("SDRAM cycle time %d.%d nS\n",
	795	+ (data[9] >> 4) & 0x0F, data[9] & 0x0F);
	796	+ break;
	797	+ }
	798	+
	799	+ switch (type) {
	800	+ case DDR2:
	801	+ printf("SDRAM access time 0.%d%d ns\n",
	802	+ (data[10] >> 4) & 0x0F, data[10] & 0x0F);
	803	+ break;
	804	+ default:
	805	+ printf("SDRAM access time %d.%d nS\n",
	806	+ (data[10] >> 4) & 0x0F, data[10] & 0x0F);
	807	+ break;
	808	+ }
	809	+
730	810	puts ("EDC configuration ");
731	811	switch(data[11]) {
732	812	case 0: puts ("None\n"); break;
733	813
734	814
735	815
...	...	@@ -739,28 +819,51 @@
739	819	else
740	820	puts ("Self refresh, rate ");
741	821	switch(data[12] & 0x7F) {
742		- case 0: puts ("15.625uS\n"); break;
743		- case 1: puts ("3.9uS\n"); break;
744		- case 2: puts ("7.8uS\n"); break;
745		- case 3: puts ("31.3uS\n"); break;
746		- case 4: puts ("62.5uS\n"); break;
747		- case 5: puts ("125uS\n"); break;
	822	+ case 0: puts ("15.625 uS\n"); break;
	823	+ case 1: puts ("3.9 uS\n"); break;
	824	+ case 2: puts ("7.8 uS \n"); break;
	825	+ case 3: puts ("31.3 uS\n"); break;
	826	+ case 4: puts ("62.5 uS\n"); break;
	827	+ case 5: puts ("125 uS\n"); break;
748	828	default: puts ("unknown\n"); break;
749	829	}
750		- printf("SDRAM width (primary) %d\n", data[13] & 0x7F);
751		- if ((data[13] & 0x80) != 0) {
752		- printf(" (second bank) %d\n",
753		- 2 * (data[13] & 0x7F));
754		- }
755		- if (data[14] != 0) {
756		- printf("EDC width %d\n",
757		- data[14] & 0x7F);
758		- if ((data[14] & 0x80) != 0)
	830	+
	831	+ switch (type) {
	832	+ case DDR2:
	833	+ printf("SDRAM width (primary) %d\n", data[13]);
	834	+ break;
	835	+ default:
	836	+ printf("SDRAM width (primary) %d\n", data[13] & 0x7F);
	837	+ if ((data[13] & 0x80) != 0) {
759	838	printf(" (second bank) %d\n",
760		- 2 * (data[14] & 0x7F));
	839	+ 2 * (data[13] & 0x7F));
	840	+ }
	841	+ break;
761	842	}
762		- printf("Min clock delay, back-to-back random column addresses %d\n",
763		- data[15]);
	843	+
	844	+ switch (type) {
	845	+ case DDR2:
	846	+ if (data[14] != 0)
	847	+ printf("EDC width %d\n", data[14]);
	848	+ break;
	849	+ default:
	850	+ if (data[14] != 0) {
	851	+ printf("EDC width %d\n",
	852	+ data[14] & 0x7F);
	853	+
	854	+ if ((data[14] & 0x80) != 0) {
	855	+ printf(" (second bank) %d\n",
	856	+ 2 * (data[14] & 0x7F));
	857	+ }
	858	+ }
	859	+ break;
	860	+ }
	861	+
	862	+ if (DDR2 != type ) {
	863	+ printf("Min clock delay, back-to-back random column addresses "
	864	+ "%d\n", data[15]);
	865	+ }
	866	+
764	867	puts ("Burst length(s) ");
765	868	if (data[16] & 0x80) puts (" Page");
766	869	if (data[16] & 0x08) puts (" 8");
767	870
...	...	@@ -769,91 +872,363 @@
769	872	if (data[16] & 0x01) puts (" 1");
770	873	putc ('\n');
771	874	printf("Number of banks %d\n", data[17]);
772		- puts ("CAS latency(s) ");
773		- if (data[18] & 0x80) puts (" TBD");
774		- if (data[18] & 0x40) puts (" 7");
775		- if (data[18] & 0x20) puts (" 6");
776		- if (data[18] & 0x10) puts (" 5");
777		- if (data[18] & 0x08) puts (" 4");
778		- if (data[18] & 0x04) puts (" 3");
779		- if (data[18] & 0x02) puts (" 2");
780		- if (data[18] & 0x01) puts (" 1");
781		- putc ('\n');
782		- puts ("CS latency(s) ");
783		- if (data[19] & 0x80) puts (" TBD");
784		- if (data[19] & 0x40) puts (" 6");
785		- if (data[19] & 0x20) puts (" 5");
786		- if (data[19] & 0x10) puts (" 4");
787		- if (data[19] & 0x08) puts (" 3");
788		- if (data[19] & 0x04) puts (" 2");
789		- if (data[19] & 0x02) puts (" 1");
790		- if (data[19] & 0x01) puts (" 0");
791		- putc ('\n');
792		- puts ("WE latency(s) ");
793		- if (data[20] & 0x80) puts (" TBD");
794		- if (data[20] & 0x40) puts (" 6");
795		- if (data[20] & 0x20) puts (" 5");
796		- if (data[20] & 0x10) puts (" 4");
797		- if (data[20] & 0x08) puts (" 3");
798		- if (data[20] & 0x04) puts (" 2");
799		- if (data[20] & 0x02) puts (" 1");
800		- if (data[20] & 0x01) puts (" 0");
801		- putc ('\n');
802		- puts ("Module attributes:\n");
803		- if (!data[21]) puts (" (none)\n");
804		- if (data[21] & 0x80) puts (" TBD (bit 7)\n");
805		- if (data[21] & 0x40) puts (" Redundant row address\n");
806		- if (data[21] & 0x20) puts (" Differential clock input\n");
807		- if (data[21] & 0x10) puts (" Registerd DQMB inputs\n");
808		- if (data[21] & 0x08) puts (" Buffered DQMB inputs\n");
809		- if (data[21] & 0x04) puts (" On-card PLL\n");
810		- if (data[21] & 0x02) puts (" Registered address/control lines\n");
811		- if (data[21] & 0x01) puts (" Buffered address/control lines\n");
812		- puts ("Device attributes:\n");
813		- if (data[22] & 0x80) puts (" TBD (bit 7)\n");
814		- if (data[22] & 0x40) puts (" TBD (bit 6)\n");
815		- if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
816		- else puts (" Upper Vcc tolerance 10%\n");
817		- if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
818		- else puts (" Lower Vcc tolerance 10%\n");
819		- if (data[22] & 0x08) puts (" Supports write1/read burst\n");
820		- if (data[22] & 0x04) puts (" Supports precharge all\n");
821		- if (data[22] & 0x02) puts (" Supports auto precharge\n");
822		- if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
823		- printf("SDRAM cycle time (2nd highest CAS latency) %d.%d nS\n",
824		- (data[23] >> 4) & 0x0F, data[23] & 0x0F);
825		- printf("SDRAM access from clock (2nd highest CAS latency) %d.%d nS\n",
826		- (data[24] >> 4) & 0x0F, data[24] & 0x0F);
827		- printf("SDRAM cycle time (3rd highest CAS latency) %d.%d nS\n",
828		- (data[25] >> 4) & 0x0F, data[25] & 0x0F);
829		- printf("SDRAM access from clock (3rd highest CAS latency) %d.%d nS\n",
830		- (data[26] >> 4) & 0x0F, data[26] & 0x0F);
831		- printf("Minimum row precharge %d nS\n", data[27]);
832		- printf("Row active to row active min %d nS\n", data[28]);
833		- printf("RAS to CAS delay min %d nS\n", data[29]);
	875	+
	876	+ switch (type) {
	877	+ case DDR2:
	878	+ puts ("CAS latency(s) ");
	879	+ if (data[18] & 0x83) puts (" TBD");
	880	+ if (data[18] & 0x40) puts (" 6");
	881	+ if (data[18] & 0x20) puts (" 5");
	882	+ if (data[18] & 0x10) puts (" 4");
	883	+ if (data[18] & 0x08) puts (" 3");
	884	+ if (data[18] & 0x04) puts (" 2");
	885	+ putc ('\n');
	886	+ break;
	887	+ default:
	888	+ puts ("CAS latency(s) ");
	889	+ if (data[18] & 0x80) puts (" TBD");
	890	+ if (data[18] & 0x40) puts (" 7");
	891	+ if (data[18] & 0x20) puts (" 6");
	892	+ if (data[18] & 0x10) puts (" 5");
	893	+ if (data[18] & 0x08) puts (" 4");
	894	+ if (data[18] & 0x04) puts (" 3");
	895	+ if (data[18] & 0x02) puts (" 2");
	896	+ if (data[18] & 0x01) puts (" 1");
	897	+ putc ('\n');
	898	+ break;
	899	+ }
	900	+
	901	+ if (DDR2 != type) {
	902	+ puts ("CS latency(s) ");
	903	+ if (data[19] & 0x80) puts (" TBD");
	904	+ if (data[19] & 0x40) puts (" 6");
	905	+ if (data[19] & 0x20) puts (" 5");
	906	+ if (data[19] & 0x10) puts (" 4");
	907	+ if (data[19] & 0x08) puts (" 3");
	908	+ if (data[19] & 0x04) puts (" 2");
	909	+ if (data[19] & 0x02) puts (" 1");
	910	+ if (data[19] & 0x01) puts (" 0");
	911	+ putc ('\n');
	912	+ }
	913	+
	914	+ if (DDR2 != type) {
	915	+ puts ("WE latency(s) ");
	916	+ if (data[20] & 0x80) puts (" TBD");
	917	+ if (data[20] & 0x40) puts (" 6");
	918	+ if (data[20] & 0x20) puts (" 5");
	919	+ if (data[20] & 0x10) puts (" 4");
	920	+ if (data[20] & 0x08) puts (" 3");
	921	+ if (data[20] & 0x04) puts (" 2");
	922	+ if (data[20] & 0x02) puts (" 1");
	923	+ if (data[20] & 0x01) puts (" 0");
	924	+ putc ('\n');
	925	+ }
	926	+
	927	+ switch (type) {
	928	+ case DDR2:
	929	+ puts ("Module attributes:\n");
	930	+ if (data[21] & 0x80)
	931	+ puts (" TBD (bit 7)\n");
	932	+ if (data[21] & 0x40)
	933	+ puts (" Analysis probe installed\n");
	934	+ if (data[21] & 0x20)
	935	+ puts (" TBD (bit 5)\n");
	936	+ if (data[21] & 0x10)
	937	+ puts (" FET switch external enable\n");
	938	+ printf(" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03);
	939	+ if (data[20] & 0x11) {
	940	+ printf(" %d active registers on DIMM\n",
	941	+ (data[21] & 0x03) + 1);
	942	+ }
	943	+ break;
	944	+ default:
	945	+ puts ("Module attributes:\n");
	946	+ if (!data[21])
	947	+ puts (" (none)\n");
	948	+ if (data[21] & 0x80)
	949	+ puts (" TBD (bit 7)\n");
	950	+ if (data[21] & 0x40)
	951	+ puts (" Redundant row address\n");
	952	+ if (data[21] & 0x20)
	953	+ puts (" Differential clock input\n");
	954	+ if (data[21] & 0x10)
	955	+ puts (" Registerd DQMB inputs\n");
	956	+ if (data[21] & 0x08)
	957	+ puts (" Buffered DQMB inputs\n");
	958	+ if (data[21] & 0x04)
	959	+ puts (" On-card PLL\n");
	960	+ if (data[21] & 0x02)
	961	+ puts (" Registered address/control lines\n");
	962	+ if (data[21] & 0x01)
	963	+ puts (" Buffered address/control lines\n");
	964	+ break;
	965	+ }
	966	+
	967	+ switch (type) {
	968	+ case DDR2:
	969	+ if (data[22] & 0x80) puts (" TBD (bit 7)\n");
	970	+ if (data[22] & 0x40) puts (" TBD (bit 6)\n");
	971	+ if (data[22] & 0x20) puts (" TBD (bit 5)\n");
	972	+ if (data[22] & 0x10) puts (" TBD (bit 4)\n");
	973	+ if (data[22] & 0x08) puts (" TBD (bit 3)\n");
	974	+ if (data[22] & 0x04)
	975	+ puts (" Supports parital array self refresh\n");
	976	+ if (data[22] & 0x02)
	977	+ puts (" Supports 50 ohm ODT\n");
	978	+ if (data[22] & 0x01)
	979	+ puts (" Supports weak driver\n");
	980	+ break;
	981	+ default:
	982	+ puts ("Device attributes:\n");
	983	+ if (data[22] & 0x80) puts (" TBD (bit 7)\n");
	984	+ if (data[22] & 0x40) puts (" TBD (bit 6)\n");
	985	+ if (data[22] & 0x20) puts (" Upper Vcc tolerance 5%\n");
	986	+ else puts (" Upper Vcc tolerance 10%\n");
	987	+ if (data[22] & 0x10) puts (" Lower Vcc tolerance 5%\n");
	988	+ else puts (" Lower Vcc tolerance 10%\n");
	989	+ if (data[22] & 0x08) puts (" Supports write1/read burst\n");
	990	+ if (data[22] & 0x04) puts (" Supports precharge all\n");
	991	+ if (data[22] & 0x02) puts (" Supports auto precharge\n");
	992	+ if (data[22] & 0x01) puts (" Supports early RAS# precharge\n");
	993	+ break;
	994	+ }
	995	+
	996	+ switch (type) {
	997	+ case DDR2:
	998	+ printf("SDRAM cycle time (2nd highest CAS latency) %d.",
	999	+ (data[23] >> 4) & 0x0F);
	1000	+
	1001	+ switch (data[23] & 0x0F) {
	1002	+ case 0x0:
	1003	+ case 0x1:
	1004	+ case 0x2:
	1005	+ case 0x3:
	1006	+ case 0x4:
	1007	+ case 0x5:
	1008	+ case 0x6:
	1009	+ case 0x7:
	1010	+ case 0x8:
	1011	+ case 0x9:
	1012	+ printf("%d ns\n", data[23] & 0x0F);
	1013	+ break;
	1014	+ case 0xA:
	1015	+ puts("25 ns\n");
	1016	+ break;
	1017	+ case 0xB:
	1018	+ puts("33 ns\n");
	1019	+ break;
	1020	+ case 0xC:
	1021	+ puts("66 ns\n");
	1022	+ break;
	1023	+ case 0xD:
	1024	+ puts("75 ns\n");
	1025	+ break;
	1026	+ default:
	1027	+ puts("?? ns\n");
	1028	+ break;
	1029	+ }
	1030	+ break;
	1031	+ default:
	1032	+ printf("SDRAM cycle time (2nd highest CAS latency) %d."
	1033	+ "%d nS\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F);
	1034	+ break;
	1035	+ }
	1036	+
	1037	+ switch (type) {
	1038	+ case DDR2:
	1039	+ printf("SDRAM access from clock (2nd highest CAS latency) 0."
	1040	+ "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
	1041	+ break;
	1042	+ default:
	1043	+ printf("SDRAM access from clock (2nd highest CAS latency) %d."
	1044	+ "%d nS\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F);
	1045	+ break;
	1046	+ }
	1047	+
	1048	+ switch (type) {
	1049	+ case DDR2:
	1050	+ printf("SDRAM cycle time (3rd highest CAS latency) %d.",
	1051	+ (data[25] >> 4) & 0x0F);
	1052	+
	1053	+ switch (data[25] & 0x0F) {
	1054	+ case 0x0:
	1055	+ case 0x1:
	1056	+ case 0x2:
	1057	+ case 0x3:
	1058	+ case 0x4:
	1059	+ case 0x5:
	1060	+ case 0x6:
	1061	+ case 0x7:
	1062	+ case 0x8:
	1063	+ case 0x9:
	1064	+ printf("%d ns\n", data[25] & 0x0F);
	1065	+ break;
	1066	+ case 0xA:
	1067	+ puts("25 ns\n");
	1068	+ break;
	1069	+ case 0xB:
	1070	+ puts("33 ns\n");
	1071	+ break;
	1072	+ case 0xC:
	1073	+ puts("66 ns\n");
	1074	+ break;
	1075	+ case 0xD:
	1076	+ puts("75 ns\n");
	1077	+ break;
	1078	+ default:
	1079	+ puts("?? ns\n");
	1080	+ break;
	1081	+ }
	1082	+ break;
	1083	+ default:
	1084	+ printf("SDRAM cycle time (3rd highest CAS latency) %d."
	1085	+ "%d nS\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F);
	1086	+ break;
	1087	+ }
	1088	+
	1089	+ switch (type) {
	1090	+ case DDR2:
	1091	+ printf("SDRAM access from clock (3rd highest CAS latency) 0."
	1092	+ "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
	1093	+ break;
	1094	+ default:
	1095	+ printf("SDRAM access from clock (3rd highest CAS latency) %d."
	1096	+ "%d nS\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F);
	1097	+ break;
	1098	+ }
	1099	+
	1100	+ switch (type) {
	1101	+ case DDR2:
	1102	+ printf("Minimum row precharge %d", data[27] >> 2);
	1103	+ switch (data[27] & 0x03) {
	1104	+ case 0x0: puts(".00 ns\n"); break;
	1105	+ case 0x1: puts(".25 ns\n"); break;
	1106	+ case 0x2: puts(".50 ns\n"); break;
	1107	+ case 0x3: puts(".75 ns\n"); break;
	1108	+ }
	1109	+ break;
	1110	+ default:
	1111	+ printf("Minimum row precharge %d nS\n", data[27]);
	1112	+ break;
	1113	+ }
	1114	+
	1115	+ switch (type) {
	1116	+ case DDR2:
	1117	+ printf("Row active to row active min %d", data[28] >> 2);
	1118	+ switch (data[28] & 0x03) {
	1119	+ case 0x0: puts(".00 ns\n"); break;
	1120	+ case 0x1: puts(".25 ns\n"); break;
	1121	+ case 0x2: puts(".50 ns\n"); break;
	1122	+ case 0x3: puts(".75 ns\n"); break;
	1123	+ }
	1124	+ break;
	1125	+ default:
	1126	+ printf("Row active to row active min %d nS\n", data[28]);
	1127	+ break;
	1128	+ }
	1129	+
	1130	+ switch (type) {
	1131	+ case DDR2:
	1132	+ printf("RAS to CAS delay min %d", data[29] >> 2);
	1133	+ switch (data[29] & 0x03) {
	1134	+ case 0x0: puts(".00 ns\n"); break;
	1135	+ case 0x1: puts(".25 ns\n"); break;
	1136	+ case 0x2: puts(".50 ns\n"); break;
	1137	+ case 0x3: puts(".75 ns\n"); break;
	1138	+ }
	1139	+ break;
	1140	+ default:
	1141	+ printf("RAS to CAS delay min %d nS\n", data[29]);
	1142	+ break;
	1143	+ }
	1144	+
834	1145	printf("Minimum RAS pulse width %d nS\n", data[30]);
835		- puts ("Density of each row ");
836		- if (data[31] & 0x80) puts (" 512");
837		- if (data[31] & 0x40) puts (" 256");
838		- if (data[31] & 0x20) puts (" 128");
839		- if (data[31] & 0x10) puts (" 64");
840		- if (data[31] & 0x08) puts (" 32");
841		- if (data[31] & 0x04) puts (" 16");
842		- if (data[31] & 0x02) puts (" 8");
843		- if (data[31] & 0x01) puts (" 4");
844		- puts ("MByte\n");
845		- printf("Command and Address setup %c%d.%d nS\n",
846		- (data[32] & 0x80) ? '-' : '+',
847		- (data[32] >> 4) & 0x07, data[32] & 0x0F);
848		- printf("Command and Address hold %c%d.%d nS\n",
849		- (data[33] & 0x80) ? '-' : '+',
850		- (data[33] >> 4) & 0x07, data[33] & 0x0F);
851		- printf("Data signal input setup %c%d.%d nS\n",
852		- (data[34] & 0x80) ? '-' : '+',
853		- (data[34] >> 4) & 0x07, data[34] & 0x0F);
854		- printf("Data signal input hold %c%d.%d nS\n",
855		- (data[35] & 0x80) ? '-' : '+',
856		- (data[35] >> 4) & 0x07, data[35] & 0x0F);
	1146	+
	1147	+ switch (type) {
	1148	+ case DDR2:
	1149	+ puts ("Density of each row ");
	1150	+ if (data[31] & 0x80) puts (" 512 MiB\n");
	1151	+ if (data[31] & 0x40) puts (" 256 MiB\n");
	1152	+ if (data[31] & 0x20) puts (" 128 MiB\n");
	1153	+ if (data[31] & 0x10) puts (" 16 GiB\n");
	1154	+ if (data[31] & 0x08) puts (" 8 GiB\n");
	1155	+ if (data[31] & 0x04) puts (" 4 GiB\n");
	1156	+ if (data[31] & 0x02) puts (" 2 GiB\n");
	1157	+ if (data[31] & 0x01) puts (" 1 GiB\n");
	1158	+ break;
	1159	+ default:
	1160	+ puts ("Density of each row ");
	1161	+ if (data[31] & 0x80) puts (" 512 MiB\n");
	1162	+ if (data[31] & 0x40) puts (" 256 MiB\n");
	1163	+ if (data[31] & 0x20) puts (" 128 MiB\n");
	1164	+ if (data[31] & 0x10) puts (" 64 MiB\n");
	1165	+ if (data[31] & 0x08) puts (" 32 MiB\n");
	1166	+ if (data[31] & 0x04) puts (" 16 MiB\n");
	1167	+ if (data[31] & 0x02) puts (" 8 MiB\n");
	1168	+ if (data[31] & 0x01) puts (" 4 MiB\n");
	1169	+ break;
	1170	+ }
	1171	+
	1172	+ switch (type) {
	1173	+ case DDR2:
	1174	+ puts("Command and Address setup ");
	1175	+ if (data[32] >= 0xA0) {
	1176	+ printf("1.%d%d ns\n",
	1177	+ ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F);
	1178	+ } else {
	1179	+ printf("0.%d%d ns\n",
	1180	+ ((data[32] >> 4) & 0x0F), data[32] & 0x0F);
	1181	+ }
	1182	+ break;
	1183	+ default:
	1184	+ printf("Command and Address setup %c%d.%d nS\n",
	1185	+ (data[32] & 0x80) ? '-' : '+',
	1186	+ (data[32] >> 4) & 0x07, data[32] & 0x0F);
	1187	+ break;
	1188	+ }
	1189	+
	1190	+ switch (type) {
	1191	+ case DDR2:
	1192	+ puts("Command and Address hold ");
	1193	+ if (data[33] >= 0xA0) {
	1194	+ printf("1.%d%d ns\n",
	1195	+ ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F);
	1196	+ } else {
	1197	+ printf("0.%d%d ns\n",
	1198	+ ((data[33] >> 4) & 0x0F), data[33] & 0x0F);
	1199	+ }
	1200	+ break;
	1201	+ default:
	1202	+ printf("Command and Address hold %c%d.%d nS\n",
	1203	+ (data[33] & 0x80) ? '-' : '+',
	1204	+ (data[33] >> 4) & 0x07, data[33] & 0x0F);
	1205	+ break;
	1206	+ }
	1207	+
	1208	+ switch (type) {
	1209	+ case DDR2:
	1210	+ printf("Data signal input setup 0.%d%d ns\n",
	1211	+ (data[34] >> 4) & 0x0F, data[34] & 0x0F);
	1212	+ break;
	1213	+ default:
	1214	+ printf("Data signal input setup %c%d.%d nS\n",
	1215	+ (data[34] & 0x80) ? '-' : '+',
	1216	+ (data[34] >> 4) & 0x07, data[34] & 0x0F);
	1217	+ break;
	1218	+ }
	1219	+
	1220	+ switch (type) {
	1221	+ case DDR2:
	1222	+ printf("Data signal input hold 0.%d%d ns\n",
	1223	+ (data[35] >> 4) & 0x0F, data[35] & 0x0F);
	1224	+ break;
	1225	+ default:
	1226	+ printf("Data signal input hold %c%d.%d nS\n",
	1227	+ (data[35] & 0x80) ? '-' : '+',
	1228	+ (data[35] >> 4) & 0x07, data[35] & 0x0F);
	1229	+ break;
	1230	+ }
	1231	+
857	1232	puts ("Manufacturer's JEDEC ID ");
858	1233	for (j = 64; j <= 71; j++)
859	1234	printf("%02X ", data[j]);
860	1235
...	...	@@ -869,9 +1244,11 @@
869	1244	for (j = 95; j <= 98; j++)
870	1245	printf("%02X ", data[j]);
871	1246	putc ('\n');
872		- printf("Speed rating PC%d\n",
873		- data[126] == 0x66 ? 66 : data[126]);
874	1247
	1248	+ if (DDR2 != type) {
	1249	+ printf("Speed rating PC%d\n",
	1250	+ data[126] == 0x66 ? 66 : data[126]);
	1251	+ }
875	1252	return 0;
876	1253	}
877	1254	#endif