Commit 0e3ece33801e377be67ffa29f083421ad820f28b
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Prepare 2009.01-rc2
Update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
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CHANGELOG
1 | +commit e92c9a860e44c14513c8909ce4299e253a775eeb | |
2 | +Author: Wolfgang Denk <wd@denx.de> | |
3 | +Date: Wed Jan 14 22:35:30 2009 +0100 | |
4 | + | |
5 | + cpu/mpc824x/Makefile: fix warning with parallel builds | |
6 | + | |
7 | + Parallel builds would occasionally issue this build warning: | |
8 | + | |
9 | + ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists | |
10 | + | |
11 | + Use "ln -sf" as quick work around for the issue. | |
12 | + | |
13 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
14 | + | |
15 | +commit b5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 | |
16 | +Author: Haiying Wang <Haiying.Wang@freescale.com> | |
17 | +Date: Tue Jan 13 16:29:28 2009 -0500 | |
18 | + | |
19 | + Some changes of TLB entry setting for MPC8572DS | |
20 | + | |
21 | + - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, | |
22 | + all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 | |
23 | + can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) | |
24 | + | |
25 | + - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. | |
26 | + | |
27 | + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> | |
28 | + | |
29 | +commit 950264317eb9594b2b5ee2fb65206200a1c6007a | |
30 | +Author: Haiying Wang <Haiying.Wang@freescale.com> | |
31 | +Date: Tue Jan 13 16:29:22 2009 -0500 | |
32 | + | |
33 | + Change DDR tlb start entry to CONFIG param for 85xx | |
34 | + | |
35 | + So that we can locate the DDR tlb start entry to the value other than 8. By | |
36 | + default, it is still 8. | |
37 | + | |
38 | + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> | |
39 | + | |
40 | +commit 6d3a10f73ece7ffb736890c10e023222612a4aa0 | |
41 | +Author: Roy Zang <tie-fei.zang@freescale.com> | |
42 | +Date: Fri Jan 9 16:02:35 2009 +0800 | |
43 | + | |
44 | + Change PCIE1&2 deciide logic on MPC8544DS board more readable | |
45 | + | |
46 | + The IO port selection for MPC8544DS board: | |
47 | + Port cfg_io_ports | |
48 | + PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 | |
49 | + PCIE2 0x4, 0x5, 0x6, 0x7 | |
50 | + PCIE3 0x6, 0x7 | |
51 | + This patch changes the PCIE12 and PCIE2 logic more readable. | |
52 | + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> | |
53 | + | |
54 | +commit 028e116811d28a031660f1ad9e20ac1293b3c5c7 | |
55 | +Author: Roy Zang <tie-fei.zang@freescale.com> | |
56 | +Date: Fri Jan 9 16:01:52 2009 +0800 | |
57 | + | |
58 | + PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit | |
59 | + | |
60 | + PCIE2 and PCIE3 should be decided by corresponing bit in devdisr instead of | |
61 | + PCIE1 bit. | |
62 | + On MPC8572DS board, PCIE refers to PCIE1. | |
63 | + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> | |
64 | + | |
65 | +commit 9afc2ef0307aecf52482df67c31b75d5f9e66b47 | |
66 | +Author: Roy Zang <tie-fei.zang@freescale.com> | |
67 | +Date: Fri Jan 9 16:00:55 2009 +0800 | |
68 | + | |
69 | + Fix IO port selection issue on MPC8544DS and MPC8572DS boards | |
70 | + | |
71 | + The IO port selection is not correct on MPC8572DS and MPC8544DS board. | |
72 | + This patch fixes this issue. | |
73 | + For MPC8572 | |
74 | + Port cfg_io_ports | |
75 | + PCIE1 0x2, 0x3, 0x7, 0xb, 0xc, 0xf | |
76 | + PCIE2 0x3, 0x7 | |
77 | + PCIE3 0x7 | |
78 | + | |
79 | + For MPC8544 | |
80 | + Port cfg_io_ports | |
81 | + PCIE1 0x2, 0x3, 0x4, 0x5, 0x6, 0x7 | |
82 | + PCIE2 0x4, 0x5, 0x6, 0x7 | |
83 | + PCIE3 0x6, 0x7 | |
84 | + Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> | |
85 | + | |
86 | +commit 3e3fffe3baf3befde287fec1fcbfe55052fb8946 | |
87 | +Author: Becky Bruce <beckyb@kernel.crashing.org> | |
88 | +Date: Wed Dec 3 22:36:44 2008 -0600 | |
89 | + | |
90 | + mpc8610hpcd: Fix PCI mapping concepts | |
91 | + | |
92 | + Rename _BASE to _BUS, as it's actually a PCI bus address, | |
93 | + separate virtual and physical addresses into _VIRT and _PHYS, | |
94 | + and use each appopriately. This makes the code easier to read | |
95 | + and understand, and facilitates mapping changes going forward. | |
96 | + | |
97 | + Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> | |
98 | + | |
99 | +commit 79e436cad3b4a7db88408c3f05175028f30d700d | |
100 | +Author: Becky Bruce <beckyb@kernel.crashing.org> | |
101 | +Date: Wed Dec 3 22:36:26 2008 -0600 | |
102 | + | |
103 | + sbc8641d: Fix PCI mapping concepts | |
104 | + | |
105 | + Rename _BASE to _BUS, as it's actually a PCI bus address, | |
106 | + separate virtual and physical addresses into _VIRT and _PHYS, | |
107 | + and use each appopriately. This makes the code easier to read | |
108 | + and understand, and facilitates mapping changes going forward. | |
109 | + | |
110 | + Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> | |
111 | + | |
112 | +commit a9f3acbcd07da72b5446ce557531a3ed8b8beff0 | |
113 | +Author: Wolfgang Denk <wd@denx.de> | |
114 | +Date: Mon Jan 12 14:50:35 2009 +0100 | |
115 | + | |
116 | + MPC86xx: fix build warnings | |
117 | + | |
118 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
119 | + | |
120 | +commit 032a1c934ef4dc003281f57302b6e693062c1868 | |
121 | +Author: Mike Frysinger <vapier@gentoo.org> | |
122 | +Date: Mon Jan 5 16:09:44 2009 -0500 | |
123 | + | |
124 | + bf537-stamp/nand: fix board_nand_init prototype | |
125 | + | |
126 | + The board_nand_init() function should return an int, not void. | |
127 | + | |
128 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
129 | + | |
130 | +commit 687f952e4119594ab913be11c90f7f018c2a7a79 | |
131 | +Author: Mike Frysinger <vapier@gentoo.org> | |
132 | +Date: Thu Dec 11 07:04:48 2008 -0500 | |
133 | + | |
134 | + Blackfin: drop CONFIG_SPI handling in board init | |
135 | + | |
136 | + The eeprom SPI init functions are duplicated as the common code already | |
137 | + executes these for us. | |
138 | + | |
139 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
140 | + | |
141 | +commit e7e684b10d73a303902208594c7c3e7e0d753282 | |
142 | +Author: Mike Frysinger <vapier@gentoo.org> | |
143 | +Date: Fri Oct 24 17:51:57 2008 -0400 | |
144 | + | |
145 | + Blackfin: fix out-of-tree building with ldscripts | |
146 | + | |
147 | + Many of the Blackfin board linker scripts are preprocessed, so make sure we | |
148 | + output the linker script into the build tree rather than the source tree. | |
149 | + | |
150 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
151 | + | |
152 | +commit b9eecc342f767b50e1476fbc1aad7d88dd4ce5eb | |
153 | +Author: Mike Frysinger <vapier@gentoo.org> | |
154 | +Date: Fri Oct 24 17:48:54 2008 -0400 | |
155 | + | |
156 | + Blackfin: fix linker scripts to work with --gc-sections | |
157 | + | |
158 | + Make sure all .text sections get pulled in and the entry point is properly | |
159 | + referenced so they don't get discarded when linking with --gc-sections. | |
160 | + | |
161 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
162 | + | |
163 | +commit 509fc553bc6087a6f705b3bf52f3950d7d1eaa58 | |
164 | +Author: Mike Frysinger <vapier@gentoo.org> | |
165 | +Date: Sat Oct 11 20:45:44 2008 -0400 | |
166 | + | |
167 | + Blackfin: set proper LDRFLAGS for parallel booting LDRs | |
168 | + | |
169 | + In order to boot an LDR out of parallel flash, the ldr utility needs a few | |
170 | + flags to tell it to generate the right header. | |
171 | + | |
172 | + Signed-off-by: Mike Frysinger <vapier@gentoo.org> | |
173 | + | |
174 | +commit 3dd9395a0d7ce69a335d0e743c04b9caedd681d3 | |
175 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
176 | +Date: Tue Jan 6 21:41:59 2009 +0100 | |
177 | + | |
178 | + at91rm9200: move define from lowlevel_init to header | |
179 | + | |
180 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
181 | + | |
182 | +commit 8a48686fac2030287765f1970ea046bd5734b733 | |
183 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
184 | +Date: Sat Jan 3 17:22:26 2009 +0100 | |
185 | + | |
186 | + m501sk: move to the common memory setup | |
187 | + | |
188 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
189 | + | |
190 | +commit d481c80d78f954133c035dae6c7d22de3625795d | |
191 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
192 | +Date: Sat Jan 3 17:22:25 2009 +0100 | |
193 | + | |
194 | + at91rm9200: rename lowlevel init value to CONFIG_SYS_ | |
195 | + | |
196 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
197 | + | |
198 | +commit 4e170b16625291aa10d0d9abc3f34e8a5945d157 | |
199 | +Author: Nicolas Ferre <nicolas.ferre@atmel.com> | |
200 | +Date: Tue Jan 6 21:13:14 2009 +0100 | |
201 | + | |
202 | + at91: add at91sam9xeek board support | |
203 | + | |
204 | + At91sam9xe is basically an at91sam9260 with embedded flash. We can manage | |
205 | + it as another entry for at91sam9260 in the Makefile. | |
206 | + | |
207 | + Check documentation at : | |
208 | + http://www.atmel.com/dyn/products/product_card.asp?part_id=4263 | |
209 | + | |
210 | + Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> | |
211 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
212 | + | |
213 | +commit 9ffd53db870a7da134f9a1ae76894a6b31237be5 | |
214 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
215 | +Date: Tue Jan 6 21:15:57 2009 +0100 | |
216 | + | |
217 | + fix bmp_logo.h make dependencies to allow parallel build | |
218 | + | |
219 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
220 | + | |
221 | +commit e12d9a8fb48d24176efffccc072b445e60a3afe4 | |
222 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
223 | +Date: Sat Jan 3 17:22:24 2009 +0100 | |
224 | + | |
225 | + at91: Fix Atmel's at91sam9 boards out of tree build | |
226 | + | |
227 | + introduced in commit 89a7a87f084c | |
228 | + | |
229 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
230 | + | |
231 | +commit 0668236bafaa1c11c521652a2facebc74beecbf0 | |
232 | +Author: Wolfgang Denk <wd@denx.de> | |
233 | +Date: Tue Dec 30 22:56:11 2008 +0100 | |
234 | + | |
235 | + README: update mailing list name and hits to patch submission. | |
236 | + | |
237 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
238 | + | |
239 | +commit d9011f9b75561a0bd9254934c2bb2bc799d4f645 | |
240 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
241 | +Date: Tue Dec 23 16:32:01 2008 -0600 | |
242 | + | |
243 | + 85xx: Enable inbound PCI config cycles for X-ES boards cleanup | |
244 | + | |
245 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
246 | + | |
247 | +commit 1f03cbfae221b24ba1341a0a3f62ff01c5c874df | |
248 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
249 | +Date: Tue Dec 23 16:32:00 2008 -0600 | |
250 | + | |
251 | + XPedite5200 board support cleanup | |
252 | + | |
253 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
254 | + | |
255 | +commit fea91edee8ae0295e3c30b1ff544df51f4d668e1 | |
256 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
257 | +Date: Tue Dec 2 21:58:04 2008 +0100 | |
258 | + | |
259 | + usb_kbd: fix usb_kbd_deregister when DEVICE_DEREGISTER not enable | |
260 | + | |
261 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
262 | + Signed-off-by: Remy Bรถhmer <linux@bohmer.net> | |
263 | + | |
264 | +commit ada591d2a0ecff5f9bc5ed1ebf310f439c3d0a28 | |
265 | +Author: Trent Piepho <tpiepho@freescale.com> | |
266 | +Date: Wed Dec 3 15:16:37 2008 -0800 | |
267 | + | |
268 | + mpc8[56]xx: Put localbus clock in sysinfo and gd | |
269 | + | |
270 | + Currently MPC85xx and MPC86xx boards just calculate the localbus frequency | |
271 | + and print it out, but don't save it. | |
272 | + | |
273 | + This changes where its calculated and stored to be more consistent with the | |
274 | + CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. | |
275 | + | |
276 | + The localbus frequency is added to sysinfo and calculated when sysinfo is | |
277 | + set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. | |
278 | + | |
279 | + get_clocks() copies the frequency into the global data, as the other | |
280 | + frequencies are, into a new field that is only enabled for MPC85xx and | |
281 | + MPC86xx. | |
282 | + | |
283 | + checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency | |
284 | + from sysinfo, like the other frequencies, instead of calculating it on the | |
285 | + spot. | |
286 | + | |
287 | + Signed-off-by: Trent Piepho <tpiepho@freescale.com> | |
288 | + Acked-by: Kumar Gala <galak@kernel.crashing.org> | |
289 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
290 | + | |
291 | +commit 9863d6aca11405e1e0d8aba2045d78aeec4d4ee7 | |
292 | +Author: Trent Piepho <tpiepho@freescale.com> | |
293 | +Date: Wed Dec 3 15:16:36 2008 -0800 | |
294 | + | |
295 | + mpc86xx: Double local bus clock divider | |
296 | + | |
297 | + The local bus clock divider should be doubled for both 8610 and 8641. | |
298 | + | |
299 | + Signed-off-by: Trent Piepho <tpiepho@freescale.com> | |
300 | + Acked-by: Kumar Gala <galak@kernel.crashing.org> | |
301 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
302 | + | |
303 | +commit 446c381e3e16f19857b72ea0d06241267b8b9d58 | |
304 | +Author: Trent Piepho <tpiepho@freescale.com> | |
305 | +Date: Wed Dec 3 15:16:35 2008 -0800 | |
306 | + | |
307 | + mpc8568: Double local bus clock divider | |
308 | + | |
309 | + The clock divider for the MPC8568 local bus should be doubled, like the | |
310 | + other newer MPC85xx chips. | |
311 | + | |
312 | + Since there are now more chips with a 2x divider than a 1x, and any new | |
313 | + 85xx chips will probably be 2x, invert the sense of the #if so that it | |
314 | + lists the 1x chips instead of the 2x ones. | |
315 | + | |
316 | + Signed-off-by: Trent Piepho <tpiepho@freescale.com> | |
317 | + Acked-by: Kumar Gala <galak@kernel.crashing.org> | |
318 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
319 | + | |
320 | +commit f51f07eb58fad12de9294ba4ee6c09a0ddeaee03 | |
321 | +Author: Dave Liu <daveliu@freescale.com> | |
322 | +Date: Tue Dec 16 12:09:27 2008 +0800 | |
323 | + | |
324 | + 85xx: Fix the boot window issue | |
325 | + | |
326 | + If one custom board is using the 8MB flash, it is set | |
327 | + as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. | |
328 | + The current start.S code will be broken at switch_as. | |
329 | + | |
330 | + It is because the TLB1[15] is set as 16MB page size, | |
331 | + EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. | |
332 | + | |
333 | + For the 8MB flash case, the EPN = 0xefxxxxxx, | |
334 | + RPN = 0xffxxxxxx. Assume the virt address of switch_as | |
335 | + is 0xef7ff18c, the real address of the instruction at | |
336 | + switch_as should be 0xff7ff18c. the 0xff7ff18c is out | |
337 | + of the range of the default 8MB boot LAW window | |
338 | + 0xff800000 - 0xffffffff. | |
339 | + | |
340 | + So when we switch to AS1 address space at switch_as, | |
341 | + the core can't fetch the instruction at switch_as any | |
342 | + more. It will cause broken issue. | |
343 | + | |
344 | + Signed-off-by: Dave Liu <daveliu@freescale.com> | |
345 | + | |
346 | +commit 58da8890d5fbd074746037722a423de9ac408616 | |
347 | +Author: Paul Gortmaker <paul.gortmaker@windriver.com> | |
348 | +Date: Thu Dec 11 15:47:50 2008 -0500 | |
349 | + | |
350 | + sbc8548: use proper PHY address | |
351 | + | |
352 | + The values given for the PHY address were wrong, so the code | |
353 | + read no valid PHY ID, and fell through to the generic PHY | |
354 | + support, which would work on 1000M but would not auto negotiate | |
355 | + down to 100M or 10M. | |
356 | + | |
357 | + Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> | |
358 | + | |
359 | +commit ad22f9273c6f24fbfa917e867680e9688e0c59c5 | |
360 | +Author: Paul Gortmaker <paul.gortmaker@windriver.com> | |
361 | +Date: Thu Dec 11 15:47:51 2008 -0500 | |
362 | + | |
363 | + sbc8548: enable command line editing by default. | |
364 | + | |
365 | + Lets make things a bit more user friendly. It isn't 1985 anymore. | |
366 | + | |
367 | + Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> | |
368 | + | |
369 | +commit bd93105fa171184a71ca8b22be03dc2705cfbd3f | |
370 | +Author: Paul Gortmaker <paul.gortmaker@windriver.com> | |
371 | +Date: Thu Dec 11 15:47:49 2008 -0500 | |
372 | + | |
373 | + sbc8548: don't enable the 3rd and 4th eTSEC | |
374 | + | |
375 | + These interfaces don't have usable connectors on the board, so don't | |
376 | + bother enumerating or configuring them. | |
377 | + | |
378 | + Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> | |
379 | + | |
380 | +commit 181a3650113883728927928b3ac81ad6dade4b2c | |
381 | +Author: Haiying Wang <Haiying.Wang@freescale.com> | |
382 | +Date: Wed Dec 3 10:08:19 2008 -0500 | |
383 | + | |
384 | + Set IVPR to kenrel entry point in second core boot page | |
385 | + | |
386 | + Assuming the OSes exception vectors start from the base of kernel address, and | |
387 | + the kernel physical starting address can be relocated to an non-zero address. | |
388 | + This patch enables the second core to have a valid IVPR for debugger before | |
389 | + kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid | |
390 | + value for second core which runs kernel at different physical address other | |
391 | + than 0x0. | |
392 | + | |
393 | + Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> | |
394 | + | |
395 | +commit a5d212a263c58cc746481bf1fc878510533ce7d6 | |
396 | +Author: Trent Piepho <tpiepho@freescale.com> | |
397 | +Date: Wed Dec 3 15:16:34 2008 -0800 | |
398 | + | |
399 | + mpc8xxx: LCRR[CLKDIV] is sometimes five bits | |
400 | + | |
401 | + On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits | |
402 | + instead of four. | |
403 | + | |
404 | + In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It | |
405 | + should be safe as the fifth bit was defined as reserved and set to 0. | |
406 | + | |
407 | + Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. | |
408 | + | |
409 | + Signed-off-by: Trent Piepho <tpiepho@freescale.com> | |
410 | + Acked-by: Kumar Gala <galak@kernel.crashing.org> | |
411 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
412 | + | |
413 | +commit 58ec4866ed916c7e422f5107bb27b0822084728e | |
414 | +Author: Trent Piepho <tpiepho@freescale.com> | |
415 | +Date: Wed Dec 3 15:16:38 2008 -0800 | |
416 | + | |
417 | + mpc8[56]xx: Put localbus clock in device tree | |
418 | + | |
419 | + Export the localbus frequency in the device tree, the same way the CPU, TB, | |
420 | + CCB, and various other frequencies are exported in their respective device | |
421 | + tree nodes. | |
422 | + | |
423 | + Some localbus devices need this information to be programed correctly, so | |
424 | + it makes sense to export it along with the other frequencies. | |
425 | + | |
426 | + Unfortunately, when someone wrote the localbus dts bindings, they didn't | |
427 | + bother to define what the "compatible" property should be. So it seems no | |
428 | + one was quite sure what to put in their dts files. | |
429 | + | |
430 | + Based on current existing dts files in the kernel source, I've used | |
431 | + "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all | |
432 | + of the 85xx devices, and are looked for by the Linux code. The eLBC is | |
433 | + apparently not entirely backward compatible with the pq3 LBC and so eLBC | |
434 | + equipped platforms like 8572 won't use pq3-localbus. | |
435 | + | |
436 | + For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems | |
437 | + and is also looked for by the Linux code. On MPC8641, I've also used | |
438 | + "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of | |
439 | + which don't use "fsl,elbc" or any other acceptable name to match on. | |
440 | + | |
441 | + Signed-off-by: Trent Piepho <tpiepho@freescale.com> | |
442 | + Acked-by: Kumar Gala <galak@kernel.crashing.org> | |
443 | + Acked-by: Jon Loeliger <jdl@freescale.com> | |
444 | + | |
445 | +commit 9d94aff699eed38b286814fcbb335f3eb8516a0e | |
446 | +Author: Kumar Gala <galak@kernel.crashing.org> | |
447 | +Date: Tue Dec 16 14:59:22 2008 -0600 | |
448 | + | |
449 | + NAND FSL elbc: Use virt_to_phys to determine which bank is in use | |
450 | + | |
451 | + The current code that determines which bank/chipselect is used for a | |
452 | + given NAND instance only worked for 32-bit addresses and assumed | |
453 | + a 1:1 mapping. This breaks in 36-bit physical configs. | |
454 | + | |
455 | + The proper way to handle this is to use the virt_to_phys() and | |
456 | + BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address | |
457 | + with the the virtual address the NAND code uses. | |
458 | + | |
459 | + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | |
460 | + Acked-by: Scott Wood <scottwood@freescale.com> | |
461 | + | |
462 | +commit 77c8115b1f1871811633eae77a5a700fac1f0e50 | |
463 | +Author: Kumar Gala <galak@kernel.crashing.org> | |
464 | +Date: Tue Dec 16 14:59:21 2008 -0600 | |
465 | + | |
466 | + ppc: Use addrmap in virt_to_phys and map_physmem. | |
467 | + | |
468 | + If we have addr map support enabled use the mapping functions to | |
469 | + implement virt_to_phys() and map_physmem(). | |
470 | + | |
471 | + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | |
472 | + | |
473 | +commit ecf5b98c7a6a2e2256dfddd48fab26678dcd6b90 | |
474 | +Author: Kumar Gala <galak@kernel.crashing.org> | |
475 | +Date: Tue Dec 16 14:59:20 2008 -0600 | |
476 | + | |
477 | + 85xx: Add support to populate addr map based on TLB settings | |
478 | + | |
479 | + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | |
480 | + | |
481 | +commit 78bbc5ce151c5a484bb51bf1866b4a993ffc16ec | |
482 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
483 | +Date: Mon Dec 1 13:47:13 2008 -0600 | |
484 | + | |
485 | + XPedite5200 board support | |
486 | + | |
487 | + Initial support for Extreme Engineering Solutions XPedite5200 - | |
488 | + a MPC8548-based PMC single board computer. | |
489 | + | |
490 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
491 | + | |
492 | +commit 487dcb4fb89be0992bc06ec1341090017bd9cf2f | |
493 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
494 | +Date: Wed Oct 29 12:39:27 2008 -0500 | |
495 | + | |
496 | + 85xx: Enable inbound PCI config cycles for X-ES boards | |
497 | + | |
498 | + Update X-ES Freescale boards to allow inbound PCI configuration | |
499 | + cycles when configured as agent/endpoint. | |
500 | + | |
501 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
502 | + | |
503 | +commit ccf0fdd02b97323f8caae18d06cc9daeac2f192f | |
504 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
505 | +Date: Wed Dec 17 16:36:23 2008 -0600 | |
506 | + | |
507 | + XPedite5370 board support | |
508 | + | |
509 | + Initial support for Extreme Engineering Solutions XPedite5370 - | |
510 | + a MPC8572-based 3U VPX single board computer with a PMC/XMC | |
511 | + site. | |
512 | + | |
513 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
514 | + | |
515 | +commit e92739d34e2d6b6aca93b2598248210710897ce8 | |
516 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
517 | +Date: Wed Dec 17 16:36:21 2008 -0600 | |
518 | + | |
519 | + Add support for PCA953x I2C gpio devices | |
520 | + | |
521 | + Initial support for NXP's 4 and 8 bit I2C gpio expanders | |
522 | + (eg pca9537, pca9557, etc). The CONFIG_PCA953X define | |
523 | + enables support for the devices while the CONFIG_CMD_PCA953X | |
524 | + define enables the pca953x command. The CONFIG_CMD_PCA953X_INFO | |
525 | + define enables an 'info' sub-command which provides summary | |
526 | + information for the given pca953x device. | |
527 | + | |
528 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
529 | + | |
530 | +commit 7a8979591171676417ab36852d8811a8c46accd8 | |
531 | +Author: Peter Tyser <ptyser@xes-inc.com> | |
532 | +Date: Wed Oct 29 12:39:26 2008 -0500 | |
533 | + | |
534 | + pci/fsl_pci_init: Enable inbound PCI config cycles | |
535 | + | |
536 | + Add fsl_pci_config_unlock() function to enable a | |
537 | + PCI/PCIe interface configured in agent/endpoint mode to | |
538 | + respond to inbound PCI configuration cycles. | |
539 | + | |
540 | + Signed-off-by: Peter Tyser <ptyser@xes-inc.com> | |
541 | + | |
542 | +commit b616f2b545f73757669b37386f0b37bb61fc6797 | |
543 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
544 | +Date: Mon Sep 8 22:27:18 2008 +0200 | |
545 | + | |
546 | + MIPS: qemu_mips: update doc to generate and to use qemu flash, ide file | |
547 | + | |
548 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
549 | + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | |
550 | + | |
551 | +commit 16cdf816779f5b602a9b3b4d2ea4dea05095c35b | |
552 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
553 | +Date: Tue Dec 16 22:10:31 2008 +0100 | |
554 | + | |
555 | + MIPS: qemu_mips: update doc to use all disk and boot linux kernel | |
556 | + | |
557 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
558 | + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | |
559 | + | |
560 | +commit 13095b2f07dacb1f863772266c1789d47a523a8a | |
561 | +Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
562 | +Date: Tue Dec 16 22:10:30 2008 +0100 | |
563 | + | |
564 | + MIPS: qemu_mips: move env storage just after u-boot | |
565 | + | |
566 | + Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
567 | + Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> | |
568 | + | |
569 | +commit aced78d852d0b009e8aaa1445af8cb40861ee549 | |
570 | +Author: Wolfgang Denk <wd@denx.de> | |
571 | +Date: Tue Dec 16 23:48:27 2008 +0100 | |
572 | + | |
573 | + Prepare 2009.01-rc1 | |
574 | + | |
575 | + Signed-off-by: Wolfgang Denk <wd@denx.de> | |
576 | + | |
1 | 577 | commit 9e2a79b4c585ad31138fb90b68fd0234d64a8da8 |
2 | 578 | Author: Wolfgang Denk <wd@denx.de> |
3 | 579 | Date: Tue Dec 16 23:13:46 2008 +0100 |
... | ... | @@ -20,6 +596,18 @@ |
20 | 596 | so this is not worth the effort. |
21 | 597 | |
22 | 598 | Signed-off-by: Wolfgang Denk <wd@denx.de> |
599 | + | |
600 | +commit ff49ea8977b56916edd5b1766d9939010e30b181 | |
601 | +Author: Scott Wood <scottwood@freescale.com> | |
602 | +Date: Tue Dec 16 14:24:16 2008 -0600 | |
603 | + | |
604 | + NAND: Mark the BBT as scanned prior to calling scan_bbt. | |
605 | + | |
606 | + Otherwise, recursion can occur if scan_bbt does not find a bad block | |
607 | + table, and tries to write one, and the attempt to erase the BBT area | |
608 | + causes a bad block check. | |
609 | + | |
610 | + Signed-off-by: Scott Wood <scottwood@freescale.com> | |
23 | 611 | |
24 | 612 | commit 584eedab66d0828f2d571a24b10526c4e65f547b |
25 | 613 | Author: Ilya Yanok <yanok@emcraft.com> |