Eric Lee / smarc-uboot

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Commit 0e4da3033f6c2a1b5f4711430723fcc41d482c93

Authored by Ye Li
1 parent b283cf33ed
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18461-2 mx7ulp_arm2: Add 10x10 and 14x14 ARM2 support 

Porting the iMX7ULP 10x10 ARM2 and 14x14 ARM2 board codes from v2017.03.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 8 changed files with 1172 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/mx7ulp/Kconfig
Diff comments   View file @ 0e4da30
... ... @@ -17,12 +17,21 @@
17 17 prompt "MX7ULP board select"
18 18 optional
19 19  
  20 +config TARGET_MX7ULP_10X10_ARM2
  21 + bool "Support mx7ulp 10x10 validation board"
  22 + select MX7ULP
  23 +
  24 +config TARGET_MX7ULP_14X14_ARM2
  25 + bool "Support mx7ulp 14x14 validation board"
  26 + select MX7ULP
  27 +
20 28 config TARGET_MX7ULP_EVK
21 29 bool "Support mx7ulp EVK board"
22 30 select MX7ULP
23 31  
24 32 endchoice
25 33  
  34 +source "board/freescale/mx7ulp_arm2/Kconfig"
26 35 source "board/freescale/mx7ulp_evk/Kconfig"
27 36  
28 37 endif
board/freescale/mx7ulp_arm2/Kconfig
Diff comments   View file @ 0e4da30
  1 +if TARGET_MX7ULP_10X10_ARM2 || TARGET_MX7ULP_14X14_ARM2
  2 +
  3 +config SYS_BOARD
  4 + default "mx7ulp_arm2"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "mx7ulp_arm2"
  11 +
  12 +endif
board/freescale/mx7ulp_arm2/Makefile
Diff comments   View file @ 0e4da30
  1 +# (C) Copyright 2016 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx7ulp_arm2.o
board/freescale/mx7ulp_arm2/imximage.cfg
Diff comments   View file @ 0e4da30
  1 +/*
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +/*
  35 + * Device Configuration Data (DCD)
  36 + *
  37 + * Each entry must have the format:
  38 + * Addr-type Address Value
  39 + *
  40 + * where:
  41 + * Addr-type register length (1,2 or 4 bytes)
  42 + * Address absolute address of the register
  43 + * value value to be stored in the register
  44 + */
  45 +DATA 4 0x403f00e0 0x00000000
  46 +DATA 4 0x403e0040 0x01000020
  47 +DATA 4 0x403e0500 0x01000000
  48 +DATA 4 0x403e050c 0x80808080
  49 +DATA 4 0x403e0508 0x00160002
  50 +DATA 4 0x403E0510 0x00000000
  51 +DATA 4 0x403E0514 0x00000001
  52 +DATA 4 0x403e0500 0x00000001
  53 +CHECK_BITS_SET 4 0x403e0500 0x01000000
  54 +DATA 4 0x403e050c 0x80808019
  55 +CHECK_BITS_SET 4 0x403e050c 0x00000040
  56 +DATA 4 0x403E0030 0x00000001
  57 +DATA 4 0x403e0040 0x11000020
  58 +DATA 4 0x403f00e0 0x42000000
  59 +
  60 +DATA 4 0x40B300AC 0x40000000
  61 +
  62 +DATA 4 0x40AD0128 0x00040000
  63 +DATA 4 0x40AD00F8 0x00000000
  64 +DATA 4 0x40AD00D8 0x00000180
  65 +DATA 4 0x40AD0108 0x00000180
  66 +DATA 4 0x40AD0104 0x00000180
  67 +DATA 4 0x40AD0124 0x00010000
  68 +DATA 4 0x40AD0080 0x0000018C
  69 +DATA 4 0x40AD0084 0x0000018C
  70 +DATA 4 0x40AD0088 0x0000018C
  71 +DATA 4 0x40AD008C 0x0000018C
  72 +
  73 +DATA 4 0x40AD0120 0x00010000
  74 +DATA 4 0x40AD010C 0x00000180
  75 +DATA 4 0x40AD0110 0x00000180
  76 +DATA 4 0x40AD0114 0x00000180
  77 +DATA 4 0x40AD0118 0x00000180
  78 +DATA 4 0x40AD0090 0x00000180
  79 +DATA 4 0x40AD0094 0x00000180
  80 +DATA 4 0x40AD0098 0x00000180
  81 +DATA 4 0x40AD009C 0x00000180
  82 +
  83 +DATA 4 0x40AD00E0 0x00040000
  84 +DATA 4 0x40AD00E4 0x00040000
  85 +
  86 +DATA 4 0x40AB001C 0x00008000
  87 +DATA 4 0x40AB0800 0xA1390003
  88 +DATA 4 0x40AB085C 0x0D3900A0
  89 +DATA 4 0x40AB0890 0x00400000
  90 +
  91 +DATA 4 0x40AB0848 0x39373939
  92 +DATA 4 0x40AB0850 0x2F313D36
  93 +DATA 4 0x40AB081C 0x33333333
  94 +DATA 4 0x40AB0820 0x33333333
  95 +DATA 4 0x40AB0824 0x33333333
  96 +DATA 4 0x40AB0828 0x33333333
  97 +
  98 +DATA 4 0x40AB08C0 0x24922492
  99 +DATA 4 0x40AB08B8 0x00000800
  100 +
  101 +DATA 4 0x40AB0004 0x00020052
  102 +DATA 4 0x40AB000C 0x424642F3
  103 +DATA 4 0x40AB0010 0x00100A22
  104 +DATA 4 0x40AB0038 0x00120556
  105 +DATA 4 0x40AB0014 0x00C700DA
  106 +DATA 4 0x40AB0018 0x00211718
  107 +DATA 4 0x40AB002C 0x0F9F26D2
  108 +DATA 4 0x40AB0030 0x009F0E10
  109 +DATA 4 0x40AB0040 0x0000004F
  110 +DATA 4 0x40AB0000 0x84190000
  111 +
  112 +DATA 4 0x40AB001C 0x00008010
  113 +DATA 4 0x40AB001C 0x003F8030
  114 +DATA 4 0x40AB001C 0xFF0A8030
  115 +DATA 4 0x40AB001C 0x04028030
  116 +DATA 4 0x40AB001C 0x83018030
  117 +DATA 4 0x40AB001C 0x01038030
  118 +
  119 +DATA 4 0x40AB083C 0x20000000
  120 +
  121 +DATA 4 0x40AB0020 0x00001800
  122 +DATA 4 0x40AB0800 0xA1310003
  123 +DATA 4 0x40AB001C 0x00000000
  124 +
  125 +#endif
board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
Diff comments   View file @ 0e4da30
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * spi/sd/nand/onenand, qspi/nor
  22 + */
  23 +
  24 +BOOT_FROM sd
  25 +
  26 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  27 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  28 +PLUGIN board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
  29 +#else
  30 +
  31 +#ifdef CONFIG_SECURE_BOOT
  32 +CSF CONFIG_CSF_SIZE
  33 +#endif
  34 +/*
  35 + * Device Configuration Data (DCD)
  36 + *
  37 + * Each entry must have the format:
  38 + * Addr-type Address Value
  39 + *
  40 + * where:
  41 + * Addr-type register length (1,2 or 4 bytes)
  42 + * Address absolute address of the register
  43 + * value value to be stored in the register
  44 + */
  45 +DATA 4 0x403f00e0 0x00000000
  46 +DATA 4 0x403e0040 0x01000020
  47 +DATA 4 0x403e0500 0x01000000
  48 +DATA 4 0x403e050c 0x80808080
  49 +DATA 4 0x403e0508 0x00160002
  50 +DATA 4 0x403E0510 0x00000000
  51 +DATA 4 0x403E0514 0x00000001
  52 +DATA 4 0x403e0500 0x00000001
  53 +CHECK_BITS_SET 4 0x403e0500 0x01000000
  54 +DATA 4 0x403e050c 0x80808019
  55 +CHECK_BITS_SET 4 0x403e050c 0x00000040
  56 +DATA 4 0x403E0030 0x00000001
  57 +DATA 4 0x403e0040 0x11000020
  58 +DATA 4 0x403f00e0 0x42000000
  59 +
  60 +DATA 4 0x40B300AC 0x40000000
  61 +
  62 +DATA 4 0x40AD0128 0x00040000
  63 +DATA 4 0x40AD00F8 0x00000000
  64 +DATA 4 0x40AD00D8 0x0000018C
  65 +DATA 4 0x40AD0108 0x00000180
  66 +DATA 4 0x40AD0104 0x00000180
  67 +DATA 4 0x40AD0124 0x00010000
  68 +DATA 4 0x40AD0080 0x0000018C
  69 +DATA 4 0x40AD0084 0x0000018C
  70 +DATA 4 0x40AD0088 0x0000018C
  71 +DATA 4 0x40AD008C 0x0000018C
  72 +
  73 +DATA 4 0x40AD0120 0x00010000
  74 +DATA 4 0x40AD010C 0x00000180
  75 +DATA 4 0x40AD0110 0x00000180
  76 +DATA 4 0x40AD0114 0x00000180
  77 +DATA 4 0x40AD0118 0x00000180
  78 +DATA 4 0x40AD0090 0x00000180
  79 +DATA 4 0x40AD0094 0x00000180
  80 +DATA 4 0x40AD0098 0x00000180
  81 +DATA 4 0x40AD009C 0x00000180
  82 +
  83 +DATA 4 0x40AD00E0 0x00040000
  84 +DATA 4 0x40AD00E4 0x00040000
  85 +
  86 +DATA 4 0x40AB001C 0x00008000
  87 +DATA 4 0x40AB0800 0xA1390003
  88 +DATA 4 0x40AB085C 0x0D3900A0
  89 +DATA 4 0x40AB0890 0x00400000
  90 +
  91 +DATA 4 0x40AB0848 0x40404040
  92 +DATA 4 0x40AB0850 0x40404040
  93 +DATA 4 0x40AB081C 0x33333333
  94 +DATA 4 0x40AB0820 0x33333333
  95 +DATA 4 0x40AB0824 0x33333333
  96 +DATA 4 0x40AB0828 0x33333333
  97 +
  98 +DATA 4 0x40AB08C0 0x24922492
  99 +DATA 4 0x40AB08B8 0x00000800
  100 +
  101 +DATA 4 0x40AB0004 0x00020052
  102 +DATA 4 0x40AB000C 0x292C42F3
  103 +DATA 4 0x40AB0010 0x00100A22
  104 +DATA 4 0x40AB0038 0x00120556
  105 +DATA 4 0x40AB0014 0x00C700DB
  106 +DATA 4 0x40AB0018 0x00211708
  107 +DATA 4 0x40AB002C 0x0F9F26D2
  108 +DATA 4 0x40AB0030 0x009F0E10
  109 +DATA 4 0x40AB0040 0x0000003F
  110 +DATA 4 0x40AB0000 0xC3110000
  111 +
  112 +DATA 4 0x40AB001C 0x00008010
  113 +DATA 4 0x40AB001C 0x00008018
  114 +DATA 4 0x40AB001C 0x003F8030
  115 +DATA 4 0x40AB001C 0x003F8038
  116 +DATA 4 0x40AB001C 0xFF0A8030
  117 +DATA 4 0x40AB001C 0xFF0A8038
  118 +DATA 4 0x40AB001C 0x04028030
  119 +DATA 4 0x40AB001C 0x04028038
  120 +DATA 4 0x40AB001C 0x82018030
  121 +DATA 4 0x40AB001C 0x82018038
  122 +DATA 4 0x40AB001C 0x01038030
  123 +DATA 4 0x40AB001C 0x01038038
  124 +
  125 +DATA 4 0x40AB083C 0x20000000
  126 +
  127 +DATA 4 0x40AB0020 0x00001800
  128 +DATA 4 0x40AB0800 0xA1390003
  129 +DATA 4 0x40AB0004 0x00020052
  130 +DATA 4 0x40AB0404 0x00011006
  131 +DATA 4 0x40AB001C 0x00000000
  132 +
  133 +#endif
board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
Diff comments   View file @ 0e4da30
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <asm/io.h>
  9 +#include <asm/arch/clock.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/arch/mx7ulp-pins.h>
  12 +#include <asm/arch/iomux.h>
  13 +#include <asm/gpio.h>
  14 +#include <fsl_esdhc.h>
  15 +#include <mmc.h>
  16 +#include <usb.h>
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +#define ESDHC_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE)
  21 +#define ESDHC_CD_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_PUS_UP)
  22 +
  23 +#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
  24 +
  25 +#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
  26 +
  27 +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE)
  28 +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE)
  29 +
  30 +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE)
  31 +
  32 +#define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \
  33 + | PAD_CTL_OBE_ENABLE)
  34 +
  35 +
  36 +int dram_init(void)
  37 +{
  38 + gd->ram_size = PHYS_SDRAM_SIZE;
  39 +
  40 + return 0;
  41 +}
  42 +
  43 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  44 +/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 ARM2, depends on rework*/
  45 +static iomux_cfg_t const lpuart6_pads[] = {
  46 + MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  47 + MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  48 +};
  49 +#else
  50 +static iomux_cfg_t const lpuart4_pads[] = {
  51 + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  52 + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  53 +};
  54 +#endif
  55 +
  56 +static void setup_iomux_uart(void)
  57 +{
  58 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  59 + mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads));
  60 +#else
  61 + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
  62 +#endif
  63 +}
  64 +
  65 +#ifdef CONFIG_USB_EHCI_MX7
  66 +
  67 +static iomux_cfg_t const usb_otg1_pads[] = {
  68 +
  69 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  70 + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */
  71 + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */
  72 +#else
  73 + /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/
  74 + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */
  75 + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */
  76 +#endif
  77 +};
  78 +
  79 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  80 +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 0)
  81 +#define OTG0_PWR_EN IMX_GPIO_NR(3, 1)
  82 +#else
  83 +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 18)
  84 +#define OTG0_PWR_EN IMX_GPIO_NR(1, 31)
  85 +#endif
  86 +static void setup_usb(void)
  87 +{
  88 + mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
  89 + ARRAY_SIZE(usb_otg1_pads));
  90 +
  91 + gpio_request(OTG0_ID_GPIO, "otg_id");
  92 + gpio_direction_input(OTG0_ID_GPIO);
  93 +}
  94 +
  95 +/*Needs to override the ehci power if controlled by GPIO */
  96 +int board_ehci_power(int port, int on)
  97 +{
  98 + switch (port) {
  99 + case 0:
  100 + if (on)
  101 + gpio_direction_output(OTG0_PWR_EN, 1);
  102 + else
  103 + gpio_direction_output(OTG0_PWR_EN, 0);
  104 + break;
  105 + default:
  106 + printf("MXC USB port %d not yet supported\n", port);
  107 + return -EINVAL;
  108 + }
  109 +
  110 + return 0;
  111 +}
  112 +
  113 +int board_usb_phy_mode(int port)
  114 +{
  115 + int ret = 0;
  116 +
  117 + if (port == 0) {
  118 + ret = gpio_get_value(OTG0_ID_GPIO);
  119 +
  120 + if (ret)
  121 + return USB_INIT_DEVICE;
  122 + else
  123 + return USB_INIT_HOST;
  124 + }
  125 +
  126 + return USB_INIT_HOST;
  127 +}
  128 +
  129 +#endif
  130 +
  131 +
  132 +int board_early_init_f(void)
  133 +{
  134 + setup_iomux_uart();
  135 +
  136 + return 0;
  137 +}
  138 +
  139 +#ifdef CONFIG_FSL_QSPI
  140 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  141 +static iomux_cfg_t const quadspi_pads[] = {
  142 + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  143 + MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  144 + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  145 + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  146 + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  147 + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  148 + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  149 +
  150 + MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  151 +};
  152 +
  153 +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 5)
  154 +#else
  155 +/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/
  156 +static iomux_cfg_t const quadspi_pads[] = {
  157 + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  158 + MX7ULP_PAD_PTB9__QSPIA_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  159 + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
  160 + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  161 + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  162 + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  163 + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  164 +
  165 + MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  166 +};
  167 +
  168 +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 12)
  169 +
  170 +#endif
  171 +int board_qspi_init(void)
  172 +{
  173 + u32 val;
  174 + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
  175 + /* enable clock */
  176 + val = readl(PCC1_RBASE + 0x94);
  177 +
  178 + if (!(val & 0x20000000)) {
  179 + writel(0x03000003, (PCC1_RBASE + 0x94));
  180 + writel(0x43000003, (PCC1_RBASE + 0x94));
  181 + }
  182 +
  183 + /* Enable QSPI as a wakeup source on B0 */
  184 + if (soc_rev() >= CHIP_REV_2_0)
  185 + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
  186 +
  187 + gpio_request(QSPI_RST_GPIO, "qspi_reset");
  188 + gpio_direction_output(QSPI_RST_GPIO, 0);
  189 + mdelay(10);
  190 + gpio_direction_output(QSPI_RST_GPIO, 1);
  191 + return 0;
  192 +}
  193 +#endif
  194 +
  195 +int board_init(void)
  196 +{
  197 + /* address of boot parameters */
  198 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  199 +
  200 +#ifdef CONFIG_USB_EHCI_MX7
  201 + setup_usb();
  202 +#endif
  203 +
  204 +#ifdef CONFIG_FSL_QSPI
  205 + board_qspi_init();
  206 +#endif
  207 +
  208 + return 0;
  209 +}
  210 +
  211 +#ifndef CONFIG_DM_MMC
  212 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  213 + {USDHC0_RBASE, 0, 8},
  214 + {USDHC1_RBASE, 0},
  215 +};
  216 +
  217 +static iomux_cfg_t const usdhc0_emmc_pads[] = {
  218 + MX7ULP_PAD_PTD0__SDHC0_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  219 + MX7ULP_PAD_PTD1__SDHC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  220 + MX7ULP_PAD_PTD2__SDHC0_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  221 + MX7ULP_PAD_PTD3__SDHC0_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  222 + MX7ULP_PAD_PTD4__SDHC0_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  223 + MX7ULP_PAD_PTD5__SDHC0_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  224 + MX7ULP_PAD_PTD6__SDHC0_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  225 + MX7ULP_PAD_PTD7__SDHC0_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  226 + MX7ULP_PAD_PTD8__SDHC0_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  227 + MX7ULP_PAD_PTD9__SDHC0_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  228 + MX7ULP_PAD_PTD10__SDHC0_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  229 + MX7ULP_PAD_PTD11__SDHC0_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  230 +};
  231 +
  232 +static iomux_cfg_t const usdhc1_pads[] = {
  233 + MX7ULP_PAD_PTE11__SDHC1_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  234 + MX7ULP_PAD_PTE3__SDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  235 + MX7ULP_PAD_PTE2__SDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  236 + MX7ULP_PAD_PTE9__SDHC1_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  237 + MX7ULP_PAD_PTE8__SDHC1_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  238 + MX7ULP_PAD_PTE7__SDHC1_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  239 + MX7ULP_PAD_PTE6__SDHC1_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  240 + MX7ULP_PAD_PTE4__SDHC1_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  241 + MX7ULP_PAD_PTE5__SDHC1_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  242 + MX7ULP_PAD_PTE0__SDHC1_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  243 + MX7ULP_PAD_PTE1__SDHC1_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  244 + MX7ULP_PAD_PTE10__SDHC1_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  245 +
  246 + MX7ULP_PAD_PTE13__PTE13 | MUX_PAD_CTRL(ESDHC_CD_GPIO_PAD_CTRL), /*CD*/
  247 +};
  248 +
  249 +#define USDHC0_CD_GPIO IMX_GPIO_NR(5, 13)
  250 +
  251 +int board_mmc_init(bd_t *bis)
  252 +{
  253 + int i, ret;
  254 + /*
  255 + * According to the board_mmc_init() the following map is done:
  256 + * (U-Boot device node) (Physical Port)
  257 + * mmc0 USDHC0
  258 + * mmc1 USDHC1
  259 + */
  260 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  261 + switch (i) {
  262 + case 0:
  263 + mx7ulp_iomux_setup_multiple_pads(usdhc0_emmc_pads, ARRAY_SIZE(usdhc0_emmc_pads));
  264 + init_clk_usdhc(0);
  265 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  266 +
  267 + break;
  268 + case 1:
  269 + mx7ulp_iomux_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  270 + init_clk_usdhc(1);
  271 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  272 +
  273 + gpio_request(USDHC0_CD_GPIO, "usdhc1_cd");
  274 + gpio_direction_input(USDHC0_CD_GPIO);
  275 + break;
  276 + default:
  277 + printf("Warning: you configured more USDHC controllers"
  278 + "(%d) than supported by the board\n", i + 1);
  279 + return -EINVAL;
  280 + }
  281 +
  282 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  283 + if (ret)
  284 + return ret;
  285 + }
  286 +
  287 + return 0;
  288 +}
  289 +
  290 +int board_mmc_getcd(struct mmc *mmc)
  291 +{
  292 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  293 + int ret = 0;
  294 +
  295 + switch (cfg->esdhc_base) {
  296 + case USDHC0_RBASE:
  297 + ret = 1;
  298 + break;
  299 + case USDHC1_RBASE:
  300 + ret = !gpio_get_value(USDHC0_CD_GPIO);
  301 + break;
  302 + }
  303 + return ret;
  304 +}
  305 +#endif
  306 +
  307 +
  308 +int board_late_init(void)
  309 +{
  310 + return 0;
  311 +}
  312 +
  313 +int checkboard(void)
  314 +{
  315 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  316 + printf("Board: i.MX7ULP 10x10 ARM2 board\n");
  317 +#else
  318 + printf("Board: i.MX7ULP 14x14 ARM2 board\n");
  319 +#endif
  320 + return 0;
  321 +}
board/freescale/mx7ulp_arm2/plugin.S
Diff comments   View file @ 0e4da30
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <config.h>
  9 +
  10 +.macro imx7ulp_ddr_freq_decrease
  11 + ldr r2, =0x403f0000
  12 + ldr r3, =0x00000000
  13 + str r3, [r2, #0xe0]
  14 +
  15 + ldr r2, =0x403e0000
  16 + ldr r3, =0x01000020
  17 + str r3, [r2, #0x40]
  18 + ldr r3, =0x01000000
  19 + str r3, [r2, #0x500]
  20 +
  21 + ldr r3, =0x80808080
  22 + str r3, [r2, #0x50c]
  23 + ldr r3, =0x00160002
  24 + str r3, [r2, #0x508]
  25 + ldr r3, =0x00000000
  26 + str r3, [r2, #0x510]
  27 + ldr r3, =0x00000001
  28 + str r3, [r2, #0x514]
  29 + ldr r3, =0x00000001
  30 + str r3, [r2, #0x500]
  31 +
  32 + ldr r3, =0x01000000
  33 +wait1:
  34 + ldr r4, [r2, #0x500]
  35 + and r4, r3
  36 + cmp r4, r3
  37 + bne wait1
  38 +
  39 + ldr r3, =0x80808019
  40 + str r3, [r2, #0x50c]
  41 +
  42 + ldr r3, =0x00000040
  43 +wait2:
  44 + ldr r4, [r2, #0x50c]
  45 + and r4, r3
  46 + cmp r4, r3
  47 + bne wait2
  48 +
  49 + ldr r3, =0x00000001
  50 + str r3, [r2, #0x30]
  51 + ldr r3, =0x11000020
  52 + str r3, [r2, #0x40]
  53 +
  54 + ldr r2, =0x403f0000
  55 + ldr r3, =0x42000000
  56 + str r3, [r2, #0xe0]
  57 +
  58 +.endm
  59 +
  60 +.macro imx7ulp_arm2_lpddr3_setting
  61 +
  62 + imx7ulp_ddr_freq_decrease
  63 +
  64 + /* Enable MMDC PCC clock */
  65 + ldr r2, =0x40b30000
  66 + ldr r3, =0x40000000
  67 + str r3, [r2, #0xac]
  68 +
  69 + /* Configure DDR pad */
  70 + ldr r0, =0x40ad0000
  71 + ldr r1, =0x00040000
  72 + str r1, [r0, #0x128]
  73 + ldr r1, =0x0
  74 + str r1, [r0, #0xf8]
  75 + ldr r1, =0x00000180
  76 + str r1, [r0, #0xd8]
  77 + ldr r1, =0x00000180
  78 + str r1, [r0, #0x108]
  79 + ldr r1, =0x00000180
  80 + str r1, [r0, #0x104]
  81 + ldr r1, =0x00010000
  82 + str r1, [r0, #0x124]
  83 + ldr r1, =0x0000018C
  84 + str r1, [r0, #0x80]
  85 + ldr r1, =0x0000018C
  86 + str r1, [r0, #0x84]
  87 + ldr r1, =0x0000018C
  88 + str r1, [r0, #0x88]
  89 + ldr r1, =0x0000018C
  90 + str r1, [r0, #0x8c]
  91 +
  92 + ldr r1, =0x00010000
  93 + str r1, [r0, #0x120]
  94 + ldr r1, =0x00000180
  95 + str r1, [r0, #0x10c]
  96 + ldr r1, =0x00000180
  97 + str r1, [r0, #0x110]
  98 + ldr r1, =0x00000180
  99 + str r1, [r0, #0x114]
  100 + ldr r1, =0x00000180
  101 + str r1, [r0, #0x118]
  102 + ldr r1, =0x00000180
  103 + str r1, [r0, #0x90]
  104 + ldr r1, =0x00000180
  105 + str r1, [r0, #0x94]
  106 + ldr r1, =0x00000180
  107 + str r1, [r0, #0x98]
  108 + ldr r1, =0x00000180
  109 + str r1, [r0, #0x9c]
  110 + ldr r1, =0x00040000
  111 + str r1, [r0, #0xe0]
  112 + ldr r1, =0x00040000
  113 + str r1, [r0, #0xe4]
  114 +
  115 + ldr r0, =0x40ab0000
  116 + ldr r1, =0x00008000
  117 + str r1, [r0, #0x1c]
  118 + ldr r1, =0xA1390003
  119 + str r1, [r0, #0x800]
  120 + ldr r1, =0x0D3900A0
  121 + str r1, [r0, #0x85c]
  122 + ldr r1, =0x00400000
  123 + str r1, [r0, #0x890]
  124 +
  125 + ldr r1, =0x39373939
  126 + str r1, [r0, #0x848]
  127 + ldr r1, =0x2F313D36
  128 + str r1, [r0, #0x850]
  129 + ldr r1, =0x33333333
  130 + str r1, [r0, #0x81c]
  131 + ldr r1, =0x33333333
  132 + str r1, [r0, #0x820]
  133 + ldr r1, =0x33333333
  134 + str r1, [r0, #0x824]
  135 + ldr r1, =0x33333333
  136 + str r1, [r0, #0x828]
  137 +
  138 + ldr r1, =0x24922492
  139 + str r1, [r0, #0x8c0]
  140 + ldr r1, =0x00000800
  141 + str r1, [r0, #0x8b8]
  142 +
  143 + ldr r1, =0x00020052
  144 + str r1, [r0, #0x4]
  145 + ldr r1, =0x424642F3
  146 + str r1, [r0, #0xc]
  147 + ldr r1, =0x00100A22
  148 + str r1, [r0, #0x10]
  149 + ldr r1, =0x00120556
  150 + str r1, [r0, #0x38]
  151 + ldr r1, =0x00C700DA
  152 + str r1, [r0, #0x14]
  153 + ldr r1, =0x00211718
  154 + str r1, [r0, #0x18]
  155 +
  156 + ldr r1, =0x0F9F26D2
  157 + str r1, [r0, #0x2c]
  158 + ldr r1, =0x009F0E10
  159 + str r1, [r0, #0x30]
  160 + ldr r1, =0x0000004F
  161 + str r1, [r0, #0x40]
  162 + ldr r1, =0x84190000
  163 + str r1, [r0, #0x0]
  164 +
  165 + ldr r1, =0x00008010
  166 + str r1, [r0, #0x1c]
  167 + ldr r1, =0x003F8030
  168 + str r1, [r0, #0x1c]
  169 + ldr r1, =0xFF0A8030
  170 + str r1, [r0, #0x1c]
  171 + ldr r1, =0x04028030
  172 + str r1, [r0, #0x1c]
  173 + ldr r1, =0x83018030
  174 + str r1, [r0, #0x1c]
  175 + ldr r1, =0x01038030
  176 + str r1, [r0, #0x1c]
  177 +
  178 + ldr r1, =0x20000000
  179 + str r1, [r0, #0x83c]
  180 +
  181 + ldr r1, =0x00001800
  182 + str r1, [r0, #0x20]
  183 + ldr r1, =0xA1310003
  184 + str r1, [r0, #0x800]
  185 + ldr r1, =0x00000000
  186 + str r1, [r0, #0x1c]
  187 +
  188 +.endm
  189 +
  190 +.macro imx7ulp_arm2_lpddr2_setting
  191 +
  192 + imx7ulp_ddr_freq_decrease
  193 +
  194 + /* Enable MMDC PCC clock */
  195 + ldr r2, =0x40b30000
  196 + ldr r3, =0x40000000
  197 + str r3, [r2, #0xac]
  198 +
  199 + /* Configure DDR pad */
  200 + ldr r0, =0x40ad0000
  201 + ldr r1, =0x00040000
  202 + str r1, [r0, #0x128]
  203 + ldr r1, =0x0
  204 + str r1, [r0, #0xf8]
  205 + ldr r1, =0x0000018C
  206 + str r1, [r0, #0xd8]
  207 + ldr r1, =0x00000180
  208 + str r1, [r0, #0x108]
  209 + ldr r1, =0x00000180
  210 + str r1, [r0, #0x104]
  211 + ldr r1, =0x00010000
  212 + str r1, [r0, #0x124]
  213 + ldr r1, =0x0000018C
  214 + str r1, [r0, #0x80]
  215 + ldr r1, =0x0000018C
  216 + str r1, [r0, #0x84]
  217 + ldr r1, =0x0000018C
  218 + str r1, [r0, #0x88]
  219 + ldr r1, =0x0000018C
  220 + str r1, [r0, #0x8c]
  221 +
  222 + ldr r1, =0x00010000
  223 + str r1, [r0, #0x120]
  224 + ldr r1, =0x00000180
  225 + str r1, [r0, #0x10c]
  226 + ldr r1, =0x00000180
  227 + str r1, [r0, #0x110]
  228 + ldr r1, =0x00000180
  229 + str r1, [r0, #0x114]
  230 + ldr r1, =0x00000180
  231 + str r1, [r0, #0x118]
  232 + ldr r1, =0x00000180
  233 + str r1, [r0, #0x90]
  234 + ldr r1, =0x00000180
  235 + str r1, [r0, #0x94]
  236 + ldr r1, =0x00000180
  237 + str r1, [r0, #0x98]
  238 + ldr r1, =0x00000180
  239 + str r1, [r0, #0x9c]
  240 + ldr r1, =0x00040000
  241 + str r1, [r0, #0xe0]
  242 + ldr r1, =0x00040000
  243 + str r1, [r0, #0xe4]
  244 +
  245 + ldr r0, =0x40ab0000
  246 + ldr r1, =0x00008000
  247 + str r1, [r0, #0x1c]
  248 + ldr r1, =0xA1390003
  249 + str r1, [r0, #0x800]
  250 + ldr r1, =0x0D3900A0
  251 + str r1, [r0, #0x85c]
  252 + ldr r1, =0x00400000
  253 + str r1, [r0, #0x890]
  254 +
  255 + ldr r1, =0x40404040
  256 + str r1, [r0, #0x848]
  257 + ldr r1, =0x40404040
  258 + str r1, [r0, #0x850]
  259 + ldr r1, =0x33333333
  260 + str r1, [r0, #0x81c]
  261 + ldr r1, =0x33333333
  262 + str r1, [r0, #0x820]
  263 + ldr r1, =0x33333333
  264 + str r1, [r0, #0x824]
  265 + ldr r1, =0x33333333
  266 + str r1, [r0, #0x828]
  267 +
  268 + ldr r1, =0x24922492
  269 + str r1, [r0, #0x8c0]
  270 + ldr r1, =0x00000800
  271 + str r1, [r0, #0x8b8]
  272 +
  273 + ldr r1, =0x00020052
  274 + str r1, [r0, #0x4]
  275 + ldr r1, =0x292C42F3
  276 + str r1, [r0, #0xc]
  277 + ldr r1, =0x00100A22
  278 + str r1, [r0, #0x10]
  279 + ldr r1, =0x00120556
  280 + str r1, [r0, #0x38]
  281 + ldr r1, =0x00C700DB
  282 + str r1, [r0, #0x14]
  283 + ldr r1, =0x00211708
  284 + str r1, [r0, #0x18]
  285 +
  286 + ldr r1, =0x0F9F26D2
  287 + str r1, [r0, #0x2c]
  288 + ldr r1, =0x009F0E10
  289 + str r1, [r0, #0x30]
  290 + ldr r1, =0x0000003F
  291 + str r1, [r0, #0x40]
  292 + ldr r1, =0xC3110000
  293 + str r1, [r0, #0x0]
  294 +
  295 + ldr r1, =0x00008010
  296 + str r1, [r0, #0x1c]
  297 + ldr r1, =0x00008018
  298 + str r1, [r0, #0x1c]
  299 + ldr r1, =0x003F8030
  300 + str r1, [r0, #0x1c]
  301 + ldr r1, =0x003F8038
  302 + str r1, [r0, #0x1c]
  303 + ldr r1, =0xFF0A8030
  304 + str r1, [r0, #0x1c]
  305 + ldr r1, =0xFF0A8038
  306 + str r1, [r0, #0x1c]
  307 + ldr r1, =0x04028030
  308 + str r1, [r0, #0x1c]
  309 + ldr r1, =0x04028038
  310 + str r1, [r0, #0x1c]
  311 + ldr r1, =0x82018030
  312 + str r1, [r0, #0x1c]
  313 + ldr r1, =0x82018038
  314 + str r1, [r0, #0x1c]
  315 + ldr r1, =0x01038030
  316 + str r1, [r0, #0x1c]
  317 + ldr r1, =0x01038038
  318 + str r1, [r0, #0x1c]
  319 +
  320 + ldr r1, =0x20000000
  321 + str r1, [r0, #0x83c]
  322 +
  323 + ldr r1, =0x00001800
  324 + str r1, [r0, #0x20]
  325 + ldr r1, =0xA1390003
  326 + str r1, [r0, #0x800]
  327 + ldr r1, =0x00020052
  328 + str r1, [r0, #0x4]
  329 + ldr r1, =0x00011006
  330 + str r1, [r0, #0x404]
  331 + ldr r1, =0x00000000
  332 + str r1, [r0, #0x1c]
  333 +
  334 +.endm
  335 +
  336 +
  337 +.macro imx7ulp_clock_gating
  338 +.endm
  339 +
  340 +.macro imx7ulp_qos_setting
  341 +.endm
  342 +
  343 +.macro imx7ulp_ddr_setting
  344 +#if defined (CONFIG_TARGET_MX7ULP_10X10_ARM2)
  345 + imx7ulp_arm2_lpddr2_setting
  346 +#else
  347 + imx7ulp_arm2_lpddr3_setting
  348 +#endif
  349 +.endm
  350 +
  351 +/* include the common plugin code here */
  352 +#include <asm/arch/mx7ulp_plugin.S>
include/configs/mx7ulp_arm2.h
Diff comments   View file @ 0e4da30
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX7ULP ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX7ULP_ARM2_CONFIG_H
  10 +#define __MX7ULP_ARM2_CONFIG_H
  11 +
  12 +#include <linux/sizes.h>
  13 +#include <asm/arch/imx-regs.h>
  14 +
  15 +#ifdef CONFIG_SECURE_BOOT
  16 +#ifndef CONFIG_CSF_SIZE
  17 +#define CONFIG_CSF_SIZE 0x4000
  18 +#endif
  19 +#endif
  20 +
  21 +#define CONFIG_BOARD_POSTCLK_INIT
  22 +#define CONFIG_SYS_BOOTM_LEN 0x1000000
  23 +
  24 +#define SRC_BASE_ADDR CMC1_RBASE
  25 +#define IRAM_BASE_ADDR OCRAM_0_BASE
  26 +#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
  27 +
  28 +/* Fuses */
  29 +#define CONFIG_CMD_FUSE
  30 +#define CONFIG_MXC_OCOTP
  31 +
  32 +#define CONFIG_BOUNCE_BUFFER
  33 +#define CONFIG_FSL_ESDHC
  34 +#define CONFIG_FSL_USDHC
  35 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  36 +
  37 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  38 +
  39 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  40 +#ifndef CONFIG_DM_MMC
  41 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  42 +#else
  43 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */
  44 +#endif
  45 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  46 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  47 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  48 +
  49 +#define CONFIG_ENV_OFFSET (14 * SZ_64K)
  50 +#define CONFIG_ENV_SIZE SZ_8K
  51 +
  52 +/* Using ULP WDOG for reset */
  53 +#define WDOG_BASE_ADDR WDG1_RBASE
  54 +
  55 +
  56 +#define CONFIG_SYS_ARCH_TIMER
  57 +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
  58 +
  59 +#define CONFIG_INITRD_TAG
  60 +#define CONFIG_CMDLINE_TAG
  61 +#define CONFIG_SETUP_MEMORY_TAGS
  62 +/*#define CONFIG_REVISION_TAG*/
  63 +
  64 +/* Size of malloc() pool */
  65 +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
  66 +
  67 +/* UART */
  68 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  69 +#define LPUART_BASE LPUART6_RBASE
  70 +#else
  71 +#define LPUART_BASE LPUART4_RBASE
  72 +#endif
  73 +
  74 +/* allow to overwrite serial and ethaddr */
  75 +#define CONFIG_ENV_OVERWRITE
  76 +#define CONFIG_CONS_INDEX 1
  77 +#define CONFIG_BAUDRATE 115200
  78 +
  79 +#define CONFIG_SYS_CACHELINE_SIZE 64
  80 +
  81 +/* Miscellaneous configurable options */
  82 +#define CONFIG_SYS_PROMPT "=> "
  83 +#define CONFIG_SYS_CBSIZE 512
  84 +
  85 +/* Print Buffer Size */
  86 +#define CONFIG_SYS_MAXARGS 256
  87 +
  88 +/* Physical Memory Map */
  89 +#define CONFIG_NR_DRAM_BANKS 1
  90 +
  91 +#define CONFIG_SYS_TEXT_BASE 0x67800000
  92 +#define PHYS_SDRAM 0x60000000
  93 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  94 +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/
  95 +#define CONFIG_SYS_MEMTEST_END 0x9E000000
  96 +#else
  97 +#define PHYS_SDRAM_SIZE SZ_512M
  98 +#define CONFIG_SYS_MEMTEST_END 0x7E000000
  99 +#endif
  100 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  101 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
  102 +
  103 +#define CONFIG_LOADADDR 0x60800000
  104 +
  105 +#define CONFIG_CMD_MEMTEST
  106 +
  107 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  108 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-10x10-arm2.dtb"
  109 +#else
  110 +#define CONFIG_DEFAULT_FDT_FILE "imx7ulp-14x14-arm2.dtb"
  111 +#endif
  112 +
  113 +#define CONFIG_MFG_ENV_SETTINGS \
  114 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  115 + "rdinit=/linuxrc " \
  116 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  117 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  118 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  119 + "g_mass_storage.iSerialNumber=\"\" "\
  120 + "\0" \
  121 + "initrd_addr=0x63800000\0" \
  122 + "initrd_high=0xffffffff\0" \
  123 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  124 +
  125 +
  126 +#define CONFIG_EXTRA_ENV_SETTINGS \
  127 + CONFIG_MFG_ENV_SETTINGS \
  128 + "script=boot.scr\0" \
  129 + "image=zImage\0" \
  130 + "console=ttyLP0\0" \
  131 + "fdt_high=0xffffffff\0" \
  132 + "initrd_high=0xffffffff\0" \
  133 + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
  134 + "fdt_addr=0x63000000\0" \
  135 + "boot_fdt=try\0" \
  136 + "earlycon=lpuart32,0x402D0010\0" \
  137 + "ip_dyn=yes\0" \
  138 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  139 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  140 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  141 + "mmcautodetect=yes\0" \
  142 + "mmcargs=setenv bootargs console=${console},${baudrate} " \
  143 + "root=${mmcroot}\0" \
  144 + "loadbootscript=" \
  145 + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  146 + "bootscript=echo Running bootscript from mmc ...; " \
  147 + "source\0" \
  148 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  149 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  150 + "mmcboot=echo Booting from mmc ...; " \
  151 + "run mmcargs; " \
  152 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  153 + "if run loadfdt; then " \
  154 + "bootz ${loadaddr} - ${fdt_addr}; " \
  155 + "else " \
  156 + "if test ${boot_fdt} = try; then " \
  157 + "bootz; " \
  158 + "else " \
  159 + "echo WARN: Cannot load the DT; " \
  160 + "fi; " \
  161 + "fi; " \
  162 + "else " \
  163 + "bootz; " \
  164 + "fi;\0" \
  165 +
  166 +#define CONFIG_BOOTCOMMAND \
  167 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  168 + "if run loadbootscript; then " \
  169 + "run bootscript; " \
  170 + "else " \
  171 + "if run loadimage; then " \
  172 + "run mmcboot; " \
  173 + "fi; " \
  174 + "fi; " \
  175 + "fi"
  176 +
  177 +
  178 +#define CONFIG_SYS_HZ 1000
  179 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  180 +
  181 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
  182 +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K
  183 +
  184 +#define CONFIG_SYS_INIT_SP_OFFSET \
  185 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  186 +#define CONFIG_SYS_INIT_SP_ADDR \
  187 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  188 +
  189 +#ifndef CONFIG_SYS_DCACHE_OFF
  190 +#define CONFIG_CMD_CACHE
  191 +#endif
  192 +
  193 +/* USB Configs */
  194 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  195 +
  196 +/* QSPI configs */
  197 +#ifdef CONFIG_FSL_QSPI
  198 +#define CONFIG_SYS_FSL_QSPI_AHB
  199 +#define CONFIG_SF_DEFAULT_BUS 0
  200 +#define CONFIG_SF_DEFAULT_CS 0
  201 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  202 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  203 +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
  204 +#define FSL_QSPI_FLASH_NUM 2
  205 +#define FSL_QSPI_FLASH_SIZE SZ_32M
  206 +#else
  207 +#define FSL_QSPI_FLASH_NUM 1
  208 +#define FSL_QSPI_FLASH_SIZE SZ_64M
  209 +#endif
  210 +#define QSPI0_BASE_ADDR 0x410A5000
  211 +#define QSPI0_AMBA_BASE 0xC0000000
  212 +#endif
  213 +
  214 +#endif /* __CONFIG_H */