Eric Lee / smarc-uboot

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Commit 0f27307122e4d22b4dca37fd95cf495e74e410a1

Authored by Eric Lee
1 parent 7b055443be
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

update memory config to the latest release

Showing 3 changed files with 33 additions and 3 deletions Inline Diff

board/embedian/smarcfimx7/ddr3l/mx7d_2x_k4b4g1646q.cfg
Diff comments   View file @ 0f27307
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 * Refer docs/README.imxmage for more details about how-to configure 6 * Refer docs/README.imxmage for more details about how-to configure
7 * and create imximage boot image 7 * and create imximage boot image
8 * 8 *
9 * The syntax is taken as close as possible with the kwbimage 9 * The syntax is taken as close as possible with the kwbimage
10 */ 10 */
11 11
12 #define __ASSEMBLY__ 12 #define __ASSEMBLY__
13 #include <config.h> 13 #include <config.h>
14 14
15 /* image version */ 15 /* image version */
16 16
17 IMAGE_VERSION 2 17 IMAGE_VERSION 2
18 18
19 /* 19 /*
20 * Boot Device : one of 20 * Boot Device : one of
21 * spi/sd/nand/onenand, qspi/nor 21 * spi/sd/nand/onenand, qspi/nor
22 */ 22 */
23 23
24 BOOT_FROM spi 24 BOOT_FROM sd
25 25
26 #ifdef CONFIG_USE_IMXIMG_PLUGIN
27 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
28 PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
29 #else
26 /* 30 /*
27 * Secure boot support 31 * Secure boot support
28 */ 32 */
29 #ifdef CONFIG_SECURE_BOOT 33 #ifdef CONFIG_SECURE_BOOT
30 CSF CONFIG_CSF_SIZE 34 CSF CONFIG_CSF_SIZE
31 #endif 35 #endif
32 36
33 /* 37 /*
34 * Device Configuration Data (DCD) 38 * Device Configuration Data (DCD)
35 * 39 *
36 * Each entry must have the format: 40 * Each entry must have the format:
37 * Addr-type Address Value 41 * Addr-type Address Value
38 * 42 *
39 * where: 43 * where:
40 * Addr-type register length (1,2 or 4 bytes) 44 * Addr-type register length (1,2 or 4 bytes)
41 * Address absolute address of the register 45 * Address absolute address of the register
42 * value value to be stored in the register 46 * value value to be stored in the register
43 */ 47 */
44 48
49 #ifdef CONFIG_IMX_OPTEE
50 DATA 4 0x30340024 0x1
51 CHECK_BITS_SET 4 0x30340024 0x1
52 #endif
45 /* IOMUXC_GPR_GPR1 */ 53 /* IOMUXC_GPR_GPR1 */
46 DATA 4 0x30340004 0x4F400005 54 DATA 4 0x30340004 0x4F400005
47 /* Clear then set bit30 to ensure exit from DDR retention */ 55 /* Clear then set bit30 to ensure exit from DDR retention */
48 DATA 4 0x30360388 0x40000000 56 DATA 4 0x30360388 0x40000000
49 DATA 4 0x30360384 0x40000000 57 DATA 4 0x30360384 0x40000000
50 /* SRC_DDRC_RCR */ 58 /* SRC_DDRC_RCR */
51 DATA 4 0x30391000 0x00000002 59 DATA 4 0x30391000 0x00000002
52 /* DDRC_MSTR */ 60 /* DDRC_MSTR */
53 DATA 4 0x307a0000 0x01040001 61 DATA 4 0x307a0000 0x01040001
54 /* DDRC_DFIUPD0 */ 62 /* DDRC_DFIUPD0 */
55 DATA 4 0x307a01a0 0x80400003 63 DATA 4 0x307a01a0 0x80400003
56 /* DDRC_DFIUPD1 */ 64 /* DDRC_DFIUPD1 */
57 DATA 4 0x307a01a4 0x00100020 65 DATA 4 0x307a01a4 0x00100020
58 /* DDRC_DFIUPD2 */ 66 /* DDRC_DFIUPD2 */
59 DATA 4 0x307a01a8 0x80100004 67 DATA 4 0x307a01a8 0x80100004
60 /* DDRC_RFSHTMG */ 68 /* DDRC_RFSHTMG */
61 DATA 4 0x307a0064 0x00400046 69 DATA 4 0x307a0064 0x00400046
62 /* DDRC_MP_PCTRL_0 */ 70 /* DDRC_MP_PCTRL_0 */
63 DATA 4 0x307a0490 0x00000001 71 DATA 4 0x307a0490 0x00000001
64 /* DDRC_INIT0 */ 72 /* DDRC_INIT0 */
65 DATA 4 0x307a00d0 0x00020083 73 DATA 4 0x307a00d0 0x00020083
66 /* DDRC_INIT1 */ 74 /* DDRC_INIT1 */
67 DATA 4 0x307a00d4 0x00690000 75 DATA 4 0x307a00d4 0x00690000
68 /* DDRC_INIT3 MR0/MR1 */ 76 /* DDRC_INIT3 MR0/MR1 */
69 DATA 4 0x307a00dc 0x09300004 77 DATA 4 0x307a00dc 0x09300004
70 /* DDRC_INIT4 MR2/MR3 */ 78 /* DDRC_INIT4 MR2/MR3 */
71 DATA 4 0x307a00e0 0x04080000 79 DATA 4 0x307a00e0 0x04080000
72 /* DDRC_INIT5 */ 80 /* DDRC_INIT5 */
73 DATA 4 0x307a00e4 0x00100004 81 DATA 4 0x307a00e4 0x00100004
74 /* DDRC_RANKCTL */ 82 /* DDRC_RANKCTL */
75 DATA 4 0x307a00f4 0x0000033f 83 DATA 4 0x307a00f4 0x0000033f
76 /* DDRC_DRAMTMG0 */ 84 /* DDRC_DRAMTMG0 */
77 DATA 4 0x307a0100 0x09081109 85 DATA 4 0x307a0100 0x09081109
78 /* DDRC_DRAMTMG1 */ 86 /* DDRC_DRAMTMG1 */
79 DATA 4 0x307a0104 0x0007020d 87 DATA 4 0x307a0104 0x0007020d
80 /* DDRC_DRAMTMG2 */ 88 /* DDRC_DRAMTMG2 */
81 DATA 4 0x307a0108 0x03040407 89 DATA 4 0x307a0108 0x03040407
82 /* DDRC_DRAMTMG3 */ 90 /* DDRC_DRAMTMG3 */
83 DATA 4 0x307a010c 0x00002006 91 DATA 4 0x307a010c 0x00002006
84 /* DDRC_DRAMTMG4 */ 92 /* DDRC_DRAMTMG4 */
85 DATA 4 0x307a0110 0x04020205 93 DATA 4 0x307a0110 0x04020205
86 /* DDRC_DRAMTMG5 */ 94 /* DDRC_DRAMTMG5 */
87 DATA 4 0x307a0114 0x03030202 95 DATA 4 0x307a0114 0x03030202
88 /* DDRC_DRAMTMG8 */ 96 /* DDRC_DRAMTMG8 */
89 DATA 4 0x307a0120 0x00000803 97 DATA 4 0x307a0120 0x00000803
90 /* DDRC_ZQCTL0 */ 98 /* DDRC_ZQCTL0 */
91 DATA 4 0x307a0180 0x00800020 99 DATA 4 0x307a0180 0x00800020
92 /* DDRC_ZQCTL1 */ 100 /* DDRC_ZQCTL1 */
93 DATA 4 0x307a0184 0x02001000 101 DATA 4 0x307a0184 0x02001000
94 /* DDRC_DFITMG0 */ 102 /* DDRC_DFITMG0 */
95 DATA 4 0x307a0190 0x02098204 103 DATA 4 0x307a0190 0x02098204
96 /* DDRC_DFITMG1 */ 104 /* DDRC_DFITMG1 */
97 DATA 4 0x307a0194 0x00030303 105 DATA 4 0x307a0194 0x00030303
98 /* DDRC_ADDRMAP0 */ 106 /* DDRC_ADDRMAP0 */
99 DATA 4 0x307a0200 0x0000001f 107 DATA 4 0x307a0200 0x0000001f
100 /* DDRC_ADDRMAP1 */ 108 /* DDRC_ADDRMAP1 */
101 DATA 4 0x307a0204 0x00080808 109 DATA 4 0x307a0204 0x00080808
102 /* DDRC_ADDRMAP4 */ 110 /* DDRC_ADDRMAP4 */
103 DATA 4 0x307a0210 0x00000f0f 111 DATA 4 0x307a0210 0x00000f0f
104 /* DDRC_ADDRMAP5 */ 112 /* DDRC_ADDRMAP5 */
105 DATA 4 0x307a0214 0x07070707 113 DATA 4 0x307a0214 0x07070707
106 /* DDRC_ADDRMAP6 */ 114 /* DDRC_ADDRMAP6 */
107 DATA 4 0x307a0218 0x0f070707 115 DATA 4 0x307a0218 0x0f070707
108 /* DDRC_ODTCFG */ 116 /* DDRC_ODTCFG */
109 DATA 4 0x307a0240 0x06000604 117 DATA 4 0x307a0240 0x06000604
110 /* DDRC_ODTMAP */ 118 /* DDRC_ODTMAP */
111 DATA 4 0x307a0244 0x00000001 119 DATA 4 0x307a0244 0x00000001
112 /* SRC_DDRC_RCR */ 120 /* SRC_DDRC_RCR */
113 DATA 4 0x30391000 0x00000000 121 DATA 4 0x30391000 0x00000000
114 /* DDR_PHY_PHY_CON0 */ 122 /* DDR_PHY_PHY_CON0 */
115 DATA 4 0x30790000 0x17420f40 123 DATA 4 0x30790000 0x17420f40
116 /* DDR_PHY_PHY_CON1 */ 124 /* DDR_PHY_PHY_CON1 */
117 DATA 4 0x30790004 0x10210100 125 DATA 4 0x30790004 0x10210100
118 /* DDR_PHY_PHY_CON4 */ 126 /* DDR_PHY_PHY_CON4 */
119 DATA 4 0x30790010 0x00060807 127 DATA 4 0x30790010 0x00060807
120 /* DDR_PHY_MDLL_CON0 */ 128 /* DDR_PHY_MDLL_CON0 */
121 DATA 4 0x307900b0 0x1010007e 129 DATA 4 0x307900b0 0x1010007e
122 /* DDR_PHY_DRVDS_CON0 */ 130 /* DDR_PHY_DRVDS_CON0 */
123 DATA 4 0x3079009c 0x00000d6e 131 DATA 4 0x3079009c 0x00000d6e
124 /* DDR_PHY_OFFSET_RD_CON0 */ 132 /* DDR_PHY_OFFSET_RD_CON0 */
125 DATA 4 0x30790020 0x0a0a0a0a 133 DATA 4 0x30790020 0x0a0a0a0a
126 /* DDR_PHY_OFFSET_WR_CON0 */ 134 /* DDR_PHY_OFFSET_WR_CON0 */
127 DATA 4 0x30790030 0x04040404 135 DATA 4 0x30790030 0x04040404
128 /* DDR_PHY_OFFSETD_CON0 */ 136 /* DDR_PHY_OFFSETD_CON0 */
129 DATA 4 0x30790050 0x01000010 137 DATA 4 0x30790050 0x01000010
130 DATA 4 0x30790050 0x00000010 138 DATA 4 0x30790050 0x00000010
131 139
132 /* DDR_PHY_ZQ_CON0 */ 140 /* DDR_PHY_ZQ_CON0 */
133 DATA 4 0x307900c0 0x0e407304 141 DATA 4 0x307900c0 0x0e407304
134 DATA 4 0x307900c0 0x0e447304 142 DATA 4 0x307900c0 0x0e447304
135 DATA 4 0x307900c0 0x0e447306 143 DATA 4 0x307900c0 0x0e447306
136 144
137 /* DDR_PHY_ZQ_CON1 */ 145 /* DDR_PHY_ZQ_CON1 */
138 CHECK_BITS_SET 4 0x307900c4 0x1 146 CHECK_BITS_SET 4 0x307900c4 0x1
139 147
140 /* DDR_PHY_ZQ_CON0 */ 148 /* DDR_PHY_ZQ_CON0 */
141 DATA 4 0x307900c0 0x0e447304 149 DATA 4 0x307900c0 0x0e447304
142 DATA 4 0x307900c0 0x0e407304 150 DATA 4 0x307900c0 0x0e407304
143 151
144 /* CCM_CCGRn */ 152 /* CCM_CCGRn */
145 DATA 4 0x30384130 0x00000000 153 DATA 4 0x30384130 0x00000000
146 /* IOMUXC_GPR_GPR8 */ 154 /* IOMUXC_GPR_GPR8 */
147 DATA 4 0x30340020 0x00000178 155 DATA 4 0x30340020 0x00000178
148 /* CCM_CCGRn */ 156 /* CCM_CCGRn */
149 DATA 4 0x30384130 0x00000002 157 DATA 4 0x30384130 0x00000002
150 /* DDR_PHY_LP_CON0 */ 158 /* DDR_PHY_LP_CON0 */
151 DATA 4 0x30790018 0x0000000f 159 DATA 4 0x30790018 0x0000000f
152 160
153 /* DDRC_STAT */ 161 /* DDRC_STAT */
154 CHECK_BITS_SET 4 0x307a0004 0x1 162 CHECK_BITS_SET 4 0x307a0004 0x1
163
164 #endif
155 165
board/embedian/smarcfimx7/ddr3l/mx7d_2x_mt41k512m16ha.cfg
Diff comments   View file @ 0f27307
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 * Refer docs/README.imxmage for more details about how-to configure 6 * Refer docs/README.imxmage for more details about how-to configure
7 * and create imximage boot image 7 * and create imximage boot image
8 * 8 *
9 * The syntax is taken as close as possible with the kwbimage 9 * The syntax is taken as close as possible with the kwbimage
10 */ 10 */
11 11
12 #define __ASSEMBLY__ 12 #define __ASSEMBLY__
13 #include <config.h> 13 #include <config.h>
14 14
15 /* image version */ 15 /* image version */
16 16
17 IMAGE_VERSION 2 17 IMAGE_VERSION 2
18 18
19 /* 19 /*
20 * Boot Device : one of 20 * Boot Device : one of
21 * spi/sd/nand/onenand, qspi/nor 21 * spi/sd/nand/onenand, qspi/nor
22 */ 22 */
23 23
24 BOOT_FROM spi 24 BOOT_FROM sd
25 25
26 #ifdef CONFIG_USE_IMXIMG_PLUGIN
27 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
28 PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
29 #else
26 /* 30 /*
27 * Secure boot support 31 * Secure boot support
28 */ 32 */
29 #ifdef CONFIG_SECURE_BOOT 33 #ifdef CONFIG_SECURE_BOOT
30 CSF CONFIG_CSF_SIZE 34 CSF CONFIG_CSF_SIZE
31 #endif 35 #endif
32 36
33 /* 37 /*
34 * Device Configuration Data (DCD) 38 * Device Configuration Data (DCD)
35 * 39 *
36 * Each entry must have the format: 40 * Each entry must have the format:
37 * Addr-type Address Value 41 * Addr-type Address Value
38 * 42 *
39 * where: 43 * where:
40 * Addr-type register length (1,2 or 4 bytes) 44 * Addr-type register length (1,2 or 4 bytes)
41 * Address absolute address of the register 45 * Address absolute address of the register
42 * value value to be stored in the register 46 * value value to be stored in the register
43 */ 47 */
44 48
49 #ifdef CONFIG_IMX_OPTEE
50 DATA 4 0x30340024 0x1
51 CHECK_BITS_SET 4 0x30340024 0x1
52 #endif
45 /* IOMUXC_GPR_GPR1 */ 53 /* IOMUXC_GPR_GPR1 */
46 DATA 4 0x30340004 0x4F400005 54 DATA 4 0x30340004 0x4F400005
47 /* Clear then set bit30 to ensure exit from DDR retention */ 55 /* Clear then set bit30 to ensure exit from DDR retention */
48 DATA 4 0x30360388 0x40000000 56 DATA 4 0x30360388 0x40000000
49 DATA 4 0x30360384 0x40000000 57 DATA 4 0x30360384 0x40000000
50 /* SRC_DDRC_RCR */ 58 /* SRC_DDRC_RCR */
51 DATA 4 0x30391000 0x00000002 59 DATA 4 0x30391000 0x00000002
52 /* DDRC_MSTR */ 60 /* DDRC_MSTR */
53 DATA 4 0x307a0000 0x01040001 61 DATA 4 0x307a0000 0x01040001
54 /* DDRC_DFIUPD0 */ 62 /* DDRC_DFIUPD0 */
55 DATA 4 0x307a01a0 0x80400003 63 DATA 4 0x307a01a0 0x80400003
56 /* DDRC_DFIUPD1 */ 64 /* DDRC_DFIUPD1 */
57 DATA 4 0x307a01a4 0x00100020 65 DATA 4 0x307a01a4 0x00100020
58 /* DDRC_DFIUPD2 */ 66 /* DDRC_DFIUPD2 */
59 DATA 4 0x307a01a8 0x80100004 67 DATA 4 0x307a01a8 0x80100004
60 /* DDRC_RFSHTMG */ 68 /* DDRC_RFSHTMG */
61 DATA 4 0x307a0064 0x0040005e 69 DATA 4 0x307a0064 0x0040005e
62 /* DDRC_MP_PCTRL_0 */ 70 /* DDRC_MP_PCTRL_0 */
63 DATA 4 0x307a0490 0x00000001 71 DATA 4 0x307a0490 0x00000001
64 /* DDRC_INIT0 */ 72 /* DDRC_INIT0 */
65 DATA 4 0x307a00d0 0x00020083 73 DATA 4 0x307a00d0 0x00020083
66 /* DDRC_INIT1 */ 74 /* DDRC_INIT1 */
67 DATA 4 0x307a00d4 0x00690000 75 DATA 4 0x307a00d4 0x00690000
68 /* DDRC_INIT2 */ 76 /* DDRC_INIT2 */
69 DATA 4 0x307a00d8 0x00000000 77 DATA 4 0x307a00d8 0x00000000
70 /* DDRC_INIT3 MR0/MR1 */ 78 /* DDRC_INIT3 MR0/MR1 */
71 DATA 4 0x307a00dc 0x09300004 79 DATA 4 0x307a00dc 0x09300004
72 /* DDRC_INIT4 MR2/MR3 */ 80 /* DDRC_INIT4 MR2/MR3 */
73 DATA 4 0x307a00e0 0x04080000 81 DATA 4 0x307a00e0 0x04080000
74 /* DDRC_INIT5 */ 82 /* DDRC_INIT5 */
75 DATA 4 0x307a00e4 0x00100004 83 DATA 4 0x307a00e4 0x00100004
76 /* DDRC_RANKCTL */ 84 /* DDRC_RANKCTL */
77 DATA 4 0x307a00f4 0x0000033f 85 DATA 4 0x307a00f4 0x0000033f
78 /* DDRC_DRAMTMG0 */ 86 /* DDRC_DRAMTMG0 */
79 DATA 4 0x307a0100 0x090a1109 87 DATA 4 0x307a0100 0x090a1109
80 /* DDRC_DRAMTMG1 */ 88 /* DDRC_DRAMTMG1 */
81 DATA 4 0x307a0104 0x0007020d 89 DATA 4 0x307a0104 0x0007020d
82 /* DDRC_DRAMTMG2 */ 90 /* DDRC_DRAMTMG2 */
83 DATA 4 0x307a0108 0x03040407 91 DATA 4 0x307a0108 0x03040407
84 /* DDRC_DRAMTMG3 */ 92 /* DDRC_DRAMTMG3 */
85 DATA 4 0x307a010c 0x00002006 93 DATA 4 0x307a010c 0x00002006
86 /* DDRC_DRAMTMG4 */ 94 /* DDRC_DRAMTMG4 */
87 DATA 4 0x307a0110 0x04020205 95 DATA 4 0x307a0110 0x04020205
88 /* DDRC_DRAMTMG5 */ 96 /* DDRC_DRAMTMG5 */
89 DATA 4 0x307a0114 0x03030202 97 DATA 4 0x307a0114 0x03030202
90 /* DDRC_DRAMTMG8 */ 98 /* DDRC_DRAMTMG8 */
91 DATA 4 0x307a0120 0x00000803 99 DATA 4 0x307a0120 0x00000803
92 /* DDRC_ZQCTL0 */ 100 /* DDRC_ZQCTL0 */
93 DATA 4 0x307a0180 0x00800020 101 DATA 4 0x307a0180 0x00800020
94 /* DDRC_DFITMG0 */ 102 /* DDRC_DFITMG0 */
95 DATA 4 0x307a0190 0x02098204 103 DATA 4 0x307a0190 0x02098204
96 /* DDRC_DFITMG1 */ 104 /* DDRC_DFITMG1 */
97 DATA 4 0x307a0194 0x00030303 105 DATA 4 0x307a0194 0x00030303
98 /* DDRC_ADDRMAP0 */ 106 /* DDRC_ADDRMAP0 */
99 DATA 4 0x307a0200 0x0000001f 107 DATA 4 0x307a0200 0x0000001f
100 /* DDRC_ADDRMAP1 */ 108 /* DDRC_ADDRMAP1 */
101 DATA 4 0x307a0204 0x00181818 109 DATA 4 0x307a0204 0x00181818
102 /* DDRC_ADDRMAP4 */ 110 /* DDRC_ADDRMAP4 */
103 DATA 4 0x307a0210 0x00000f0f 111 DATA 4 0x307a0210 0x00000f0f
104 /* DDRC_ADDRMAP5 */ 112 /* DDRC_ADDRMAP5 */
105 DATA 4 0x307a0214 0x04040404 113 DATA 4 0x307a0214 0x04040404
106 /* DDRC_ADDRMAP6 */ 114 /* DDRC_ADDRMAP6 */
107 DATA 4 0x307a0218 0x04040404 115 DATA 4 0x307a0218 0x04040404
108 /* DDRC_ODTCFG */ 116 /* DDRC_ODTCFG */
109 DATA 4 0x307a0240 0x06000604 117 DATA 4 0x307a0240 0x06000604
110 /* DDRC_ODTMAP */ 118 /* DDRC_ODTMAP */
111 DATA 4 0x307a0244 0x00000001 119 DATA 4 0x307a0244 0x00000001
112 /* SRC_DDRC_RCR */ 120 /* SRC_DDRC_RCR */
113 DATA 4 0x30391000 0x00000000 121 DATA 4 0x30391000 0x00000000
114 /* DDR_PHY_PHY_CON0 */ 122 /* DDR_PHY_PHY_CON0 */
115 DATA 4 0x30790000 0x17420f40 123 DATA 4 0x30790000 0x17420f40
116 /* DDR_PHY_PHY_CON1 */ 124 /* DDR_PHY_PHY_CON1 */
117 DATA 4 0x30790004 0x10210100 125 DATA 4 0x30790004 0x10210100
118 /* DDR_PHY_PHY_CON4 */ 126 /* DDR_PHY_PHY_CON4 */
119 DATA 4 0x30790010 0x00060807 127 DATA 4 0x30790010 0x00060807
120 /* DDR_PHY_MDLL_CON0 */ 128 /* DDR_PHY_MDLL_CON0 */
121 DATA 4 0x307900b0 0x1010007e 129 DATA 4 0x307900b0 0x1010007e
122 /* DDR_PHY_DRVDS_CON0 */ 130 /* DDR_PHY_DRVDS_CON0 */
123 DATA 4 0x3079009c 0x00000d6e 131 DATA 4 0x3079009c 0x00000d6e
124 /* DDR_PHY_OFFSET_RD_CON0 */ 132 /* DDR_PHY_OFFSET_RD_CON0 */
125 DATA 4 0x30790020 0x0c0c0c0c 133 DATA 4 0x30790020 0x0c0c0c0c
126 /* DDR_PHY_OFFSET_WR_CON0 */ 134 /* DDR_PHY_OFFSET_WR_CON0 */
127 DATA 4 0x30790030 0x04040404 135 DATA 4 0x30790030 0x04040404
128 /* DDR_PHY_OFFSETD_CON0 */ 136 /* DDR_PHY_OFFSETD_CON0 */
129 DATA 4 0x30790050 0x01000010 137 DATA 4 0x30790050 0x01000010
130 DATA 4 0x30790050 0x00000010 138 DATA 4 0x30790050 0x00000010
131 139
132 /* DDR_PHY_ZQ_CON0 */ 140 /* DDR_PHY_ZQ_CON0 */
133 DATA 4 0x307900c0 0x0e407304 141 DATA 4 0x307900c0 0x0e407304
134 DATA 4 0x307900c0 0x0e447304 142 DATA 4 0x307900c0 0x0e447304
135 DATA 4 0x307900c0 0x0e447306 143 DATA 4 0x307900c0 0x0e447306
136 144
137 /* DDR_PHY_ZQ_CON1 */ 145 /* DDR_PHY_ZQ_CON1 */
138 CHECK_BITS_SET 4 0x307900c4 0x1 146 CHECK_BITS_SET 4 0x307900c4 0x1
139 147
140 /* DDR_PHY_ZQ_CON0 */ 148 /* DDR_PHY_ZQ_CON0 */
141 DATA 4 0x307900c0 0x0e447304 149 DATA 4 0x307900c0 0x0e447304
142 DATA 4 0x307900c0 0x0e407304 150 DATA 4 0x307900c0 0x0e407304
143 151
144 /* CCM_CCGRn */ 152 /* CCM_CCGRn */
145 DATA 4 0x30384130 0x00000000 153 DATA 4 0x30384130 0x00000000
146 /* IOMUXC_GPR_GPR8 */ 154 /* IOMUXC_GPR_GPR8 */
147 DATA 4 0x30340020 0x00000178 155 DATA 4 0x30340020 0x00000178
148 /* CCM_CCGRn */ 156 /* CCM_CCGRn */
149 DATA 4 0x30384130 0x00000002 157 DATA 4 0x30384130 0x00000002
150 /* DDR_PHY_LP_CON0 */ 158 /* DDR_PHY_LP_CON0 */
151 DATA 4 0x30790018 0x0000000f 159 DATA 4 0x30790018 0x0000000f
152 160
153 /* DDRC_STAT */ 161 /* DDRC_STAT */
154 CHECK_BITS_SET 4 0x307a0004 0x1 162 CHECK_BITS_SET 4 0x307a0004 0x1
163
164 #endif
155 165
board/embedian/smarcfimx7/ddr3l/mx7s_2x_k4b2g1646q.cfg
Diff comments   View file @ 0f27307
1 /* 1 /*
2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. 2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 * Refer docs/README.imxmage for more details about how-to configure 6 * Refer docs/README.imxmage for more details about how-to configure
7 * and create imximage boot image 7 * and create imximage boot image
8 * 8 *
9 * The syntax is taken as close as possible with the kwbimage 9 * The syntax is taken as close as possible with the kwbimage
10 */ 10 */
11 11
12 #define __ASSEMBLY__ 12 #define __ASSEMBLY__
13 #include <config.h> 13 #include <config.h>
14 14
15 /* image version */ 15 /* image version */
16 16
17 IMAGE_VERSION 2 17 IMAGE_VERSION 2
18 18
19 /* 19 /*
20 * Boot Device : one of 20 * Boot Device : one of
21 * spi/sd/nand/onenand, qspi/nor 21 * spi/sd/nand/onenand, qspi/nor
22 */ 22 */
23 23
24 BOOT_FROM spi 24 BOOT_FROM sd
25 25
26 #ifdef CONFIG_USE_IMXIMG_PLUGIN
27 /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
28 PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
29 #else
26 /* 30 /*
27 * Secure boot support 31 * Secure boot support
28 */ 32 */
29 #ifdef CONFIG_SECURE_BOOT 33 #ifdef CONFIG_SECURE_BOOT
30 CSF CONFIG_CSF_SIZE 34 CSF CONFIG_CSF_SIZE
31 #endif 35 #endif
32 36
33 /* 37 /*
34 * Device Configuration Data (DCD) 38 * Device Configuration Data (DCD)
35 * 39 *
36 * Each entry must have the format: 40 * Each entry must have the format:
37 * Addr-type Address Value 41 * Addr-type Address Value
38 * 42 *
39 * where: 43 * where:
40 * Addr-type register length (1,2 or 4 bytes) 44 * Addr-type register length (1,2 or 4 bytes)
41 * Address absolute address of the register 45 * Address absolute address of the register
42 * value value to be stored in the register 46 * value value to be stored in the register
43 */ 47 */
44 48
49 #ifdef CONFIG_IMX_OPTEE
50 DATA 4 0x30340024 0x1
51 CHECK_BITS_SET 4 0x30340024 0x1
52 #endif
45 /* IOMUXC_GPR_GPR1 */ 53 /* IOMUXC_GPR_GPR1 */
46 DATA 4 0x30340004 0x4F400005 54 DATA 4 0x30340004 0x4F400005
47 /* Clear then set bit30 to ensure exit from DDR retention */ 55 /* Clear then set bit30 to ensure exit from DDR retention */
48 DATA 4 0x30360388 0x40000000 56 DATA 4 0x30360388 0x40000000
49 DATA 4 0x30360384 0x40000000 57 DATA 4 0x30360384 0x40000000
50 /* SRC_DDRC_RCR */ 58 /* SRC_DDRC_RCR */
51 DATA 4 0x30391000 0x00000002 59 DATA 4 0x30391000 0x00000002
52 /* DDRC_MSTR */ 60 /* DDRC_MSTR */
53 DATA 4 0x307a0000 0x01040001 61 DATA 4 0x307a0000 0x01040001
54 /* DDRC_DFIUPD0 */ 62 /* DDRC_DFIUPD0 */
55 DATA 4 0x307a01a0 0x80400003 63 DATA 4 0x307a01a0 0x80400003
56 /* DDRC_DFIUPD1 */ 64 /* DDRC_DFIUPD1 */
57 DATA 4 0x307a01a4 0x00100020 65 DATA 4 0x307a01a4 0x00100020
58 /* DDRC_DFIUPD2 */ 66 /* DDRC_DFIUPD2 */
59 DATA 4 0x307a01a8 0x80100004 67 DATA 4 0x307a01a8 0x80100004
60 /* DDRC_RFSHTMG */ 68 /* DDRC_RFSHTMG */
61 DATA 4 0x307a0064 0x00400046 69 DATA 4 0x307a0064 0x00400046
62 /* DDRC_MP_PCTRL_0 */ 70 /* DDRC_MP_PCTRL_0 */
63 DATA 4 0x307a0490 0x00000001 71 DATA 4 0x307a0490 0x00000001
64 /* DDRC_INIT0 */ 72 /* DDRC_INIT0 */
65 DATA 4 0x307a00d0 0x00020083 73 DATA 4 0x307a00d0 0x00020083
66 /* DDRC_INIT1 */ 74 /* DDRC_INIT1 */
67 DATA 4 0x307a00d4 0x00690000 75 DATA 4 0x307a00d4 0x00690000
68 /* DDRC_INIT3 MR0/MR1 */ 76 /* DDRC_INIT3 MR0/MR1 */
69 DATA 4 0x307a00dc 0x09300004 77 DATA 4 0x307a00dc 0x09300004
70 /* DDRC_INIT4 MR2/MR3 */ 78 /* DDRC_INIT4 MR2/MR3 */
71 DATA 4 0x307a00e0 0x04080000 79 DATA 4 0x307a00e0 0x04080000
72 /* DDRC_INIT5 */ 80 /* DDRC_INIT5 */
73 DATA 4 0x307a00e4 0x00100004 81 DATA 4 0x307a00e4 0x00100004
74 /* DDRC_RANKCTL */ 82 /* DDRC_RANKCTL */
75 DATA 4 0x307a00f4 0x0000033f 83 DATA 4 0x307a00f4 0x0000033f
76 /* DDRC_DRAMTMG0 */ 84 /* DDRC_DRAMTMG0 */
77 DATA 4 0x307a0100 0x09081109 85 DATA 4 0x307a0100 0x09081109
78 /* DDRC_DRAMTMG1 */ 86 /* DDRC_DRAMTMG1 */
79 DATA 4 0x307a0104 0x0007020d 87 DATA 4 0x307a0104 0x0007020d
80 /* DDRC_DRAMTMG2 */ 88 /* DDRC_DRAMTMG2 */
81 DATA 4 0x307a0108 0x03040407 89 DATA 4 0x307a0108 0x03040407
82 /* DDRC_DRAMTMG3 */ 90 /* DDRC_DRAMTMG3 */
83 DATA 4 0x307a010c 0x00002006 91 DATA 4 0x307a010c 0x00002006
84 /* DDRC_DRAMTMG4 */ 92 /* DDRC_DRAMTMG4 */
85 DATA 4 0x307a0110 0x04020205 93 DATA 4 0x307a0110 0x04020205
86 /* DDRC_DRAMTMG5 */ 94 /* DDRC_DRAMTMG5 */
87 DATA 4 0x307a0114 0x03030202 95 DATA 4 0x307a0114 0x03030202
88 /* DDRC_DRAMTMG8 */ 96 /* DDRC_DRAMTMG8 */
89 DATA 4 0x307a0120 0x00000803 97 DATA 4 0x307a0120 0x00000803
90 /* DDRC_ZQCTL0 */ 98 /* DDRC_ZQCTL0 */
91 DATA 4 0x307a0180 0x00800020 99 DATA 4 0x307a0180 0x00800020
92 /* DDRC_ZQCTL1 */ 100 /* DDRC_ZQCTL1 */
93 DATA 4 0x307a0184 0x02001000 101 DATA 4 0x307a0184 0x02001000
94 /* DDRC_DFITMG0 */ 102 /* DDRC_DFITMG0 */
95 DATA 4 0x307a0190 0x02098204 103 DATA 4 0x307a0190 0x02098204
96 /* DDRC_DFITMG1 */ 104 /* DDRC_DFITMG1 */
97 DATA 4 0x307a0194 0x00030303 105 DATA 4 0x307a0194 0x00030303
98 /* DDRC_ADDRMAP0 */ 106 /* DDRC_ADDRMAP0 */
99 DATA 4 0x307a0200 0x0000001f 107 DATA 4 0x307a0200 0x0000001f
100 /* DDRC_ADDRMAP1 */ 108 /* DDRC_ADDRMAP1 */
101 DATA 4 0x307a0204 0x00080808 109 DATA 4 0x307a0204 0x00080808
102 /* DDRC_ADDRMAP4 */ 110 /* DDRC_ADDRMAP4 */
103 DATA 4 0x307a0210 0x00000f0f 111 DATA 4 0x307a0210 0x00000f0f
104 /* DDRC_ADDRMAP5 */ 112 /* DDRC_ADDRMAP5 */
105 DATA 4 0x307a0214 0x07070707 113 DATA 4 0x307a0214 0x07070707
106 /* DDRC_ADDRMAP6 */ 114 /* DDRC_ADDRMAP6 */
107 DATA 4 0x307a0218 0x0f070707 115 DATA 4 0x307a0218 0x0f070707
108 /* DDRC_ODTCFG */ 116 /* DDRC_ODTCFG */
109 DATA 4 0x307a0240 0x06000604 117 DATA 4 0x307a0240 0x06000604
110 /* DDRC_ODTMAP */ 118 /* DDRC_ODTMAP */
111 DATA 4 0x307a0244 0x00000001 119 DATA 4 0x307a0244 0x00000001
112 /* SRC_DDRC_RCR */ 120 /* SRC_DDRC_RCR */
113 DATA 4 0x30391000 0x00000000 121 DATA 4 0x30391000 0x00000000
114 /* DDR_PHY_PHY_CON0 */ 122 /* DDR_PHY_PHY_CON0 */
115 DATA 4 0x30790000 0x17420f40 123 DATA 4 0x30790000 0x17420f40
116 /* DDR_PHY_PHY_CON1 */ 124 /* DDR_PHY_PHY_CON1 */
117 DATA 4 0x30790004 0x10210100 125 DATA 4 0x30790004 0x10210100
118 /* DDR_PHY_PHY_CON4 */ 126 /* DDR_PHY_PHY_CON4 */
119 DATA 4 0x30790010 0x00060807 127 DATA 4 0x30790010 0x00060807
120 /* DDR_PHY_MDLL_CON0 */ 128 /* DDR_PHY_MDLL_CON0 */
121 DATA 4 0x307900b0 0x1010007e 129 DATA 4 0x307900b0 0x1010007e
122 /* DDR_PHY_DRVDS_CON0 */ 130 /* DDR_PHY_DRVDS_CON0 */
123 DATA 4 0x3079009c 0x00000d6e 131 DATA 4 0x3079009c 0x00000d6e
124 /* DDR_PHY_OFFSET_RD_CON0 */ 132 /* DDR_PHY_OFFSET_RD_CON0 */
125 DATA 4 0x30790020 0x0c0c0c0c 133 DATA 4 0x30790020 0x0c0c0c0c
126 /* DDR_PHY_OFFSET_WR_CON0 */ 134 /* DDR_PHY_OFFSET_WR_CON0 */
127 DATA 4 0x30790030 0x04040404 135 DATA 4 0x30790030 0x04040404
128 /* DDR_PHY_OFFSETD_CON0 */ 136 /* DDR_PHY_OFFSETD_CON0 */
129 DATA 4 0x30790050 0x01000010 137 DATA 4 0x30790050 0x01000010
130 DATA 4 0x30790050 0x00000010 138 DATA 4 0x30790050 0x00000010
131 139
132 /* DDR_PHY_ZQ_CON0 */ 140 /* DDR_PHY_ZQ_CON0 */
133 DATA 4 0x307900c0 0x0e407304 141 DATA 4 0x307900c0 0x0e407304
134 DATA 4 0x307900c0 0x0e447304 142 DATA 4 0x307900c0 0x0e447304
135 DATA 4 0x307900c0 0x0e447306 143 DATA 4 0x307900c0 0x0e447306
136 144
137 /* DDR_PHY_ZQ_CON1 */ 145 /* DDR_PHY_ZQ_CON1 */
138 CHECK_BITS_SET 4 0x307900c4 0x1 146 CHECK_BITS_SET 4 0x307900c4 0x1
139 147
140 /* DDR_PHY_ZQ_CON0 */ 148 /* DDR_PHY_ZQ_CON0 */
141 DATA 4 0x307900c0 0x0e447304 149 DATA 4 0x307900c0 0x0e447304
142 DATA 4 0x307900c0 0x0e407304 150 DATA 4 0x307900c0 0x0e407304
143 151
144 /* CCM_CCGRn */ 152 /* CCM_CCGRn */
145 DATA 4 0x30384130 0x00000000 153 DATA 4 0x30384130 0x00000000
146 /* IOMUXC_GPR_GPR8 */ 154 /* IOMUXC_GPR_GPR8 */
147 DATA 4 0x30340020 0x00000178 155 DATA 4 0x30340020 0x00000178
148 /* CCM_CCGRn */ 156 /* CCM_CCGRn */
149 DATA 4 0x30384130 0x00000002 157 DATA 4 0x30384130 0x00000002
150 /* DDR_PHY_LP_CON0 */ 158 /* DDR_PHY_LP_CON0 */
151 DATA 4 0x30790018 0x0000000f 159 DATA 4 0x30790018 0x0000000f
152 160
153 /* DDRC_STAT */ 161 /* DDRC_STAT */
154 CHECK_BITS_SET 4 0x307a0004 0x1 162 CHECK_BITS_SET 4 0x307a0004 0x1
163
164 #endif
155 165