MLK-18591-8 android: iot: Add board support for imx6dl pico pi

Add board support for imx6dl pico pi, porting from v2017.03 Signed-off-by: Ye Li <ye.li@nxp.com>

MLK-18591-8 android: iot: Add board support for imx6dl pico pi
Add board support for imx6dl pico pi, porting from v2017.03 Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li
1 parent 1c7f8ef978
Showing 10 changed files with 1123 additions and 1 deletions Side-by-side Diff
arch/arm/mach-imx/mx6/Kconfig
arch/arm/mach-imx/mx6/clock.c
board/technexion/pico-imx6dl/Kconfig
board/technexion/pico-imx6dl/MAINTAINERS
board/technexion/pico-imx6dl/Makefile
board/technexion/pico-imx6dl/pico-imx6dl.c
board/technexion/pico-imx6dl/pico-imx6dl.cfg
configs/pico-imx6dl_defconfig
include/configs/pico-imx6dl.h
include/configs/pico-imx6dl_android_things.h
@@ -482,6 +482,14 @@
 	select SUPPORT_SPL
 	imply CMD_SATA
  
+config TARGET_PICO_IMX6DL
+    bool "Support pico-imx6dl"
+    select MX6QDL
+    select BOARD_LATE_INIT
+	select DM
+	select DM_THERMAL
+	select BOARD_EARLY_INIT_F
+
 config TARGET_PICO_IMX6UL
 	bool "PICO-IMX6UL-EMMC"
 	select MX6UL
@@ -631,6 +639,7 @@
 source "board/sks-kinkel/sksimx6/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
+source "board/technexion/pico-imx6dl/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/toradex/apalis_imx6/Kconfig"
@@ -1461,7 +1461,7 @@
 }
 #endif
  
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) || \
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) || \
 	defined(CONFIG_MX6S)
 static void disable_ldb_di_clock_sources(void)
 {
+if TARGET_PICO_IMX6DL
+
+config SYS_BOARD
+	default "pico-imx6dl"
+
+config SYS_VENDOR
+	default "technexion"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "pico-imx6dl"
+
+endif
+Technexion PICO-IMX6 board
+M:	Richard Hu <richard.hu@technexion.com>
+S:	Maintained
+F:	board/pico-imx6dl/
+F:	include/configs/pico-imx6dl.h
+F:	configs/pico-imx6dl_defconfig
+#
+# (C) Copyright 2015 Technexion Ltd.
+# (C) Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pico-imx6dl.o
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ * Copyright 2017 NXP
+ *
+ * Author: Richard Hu <richard.hu@technexion.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <phy.h>
+#include <input.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define BASEBOARD_USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define USDHC1_CD_GPIO		IMX_GPIO_NR(3, 9)
+#define USDHC3_CD_GPIO		IMX_GPIO_NR(1, 2)
+#define ETH_PHY_RESET		IMX_GPIO_NR(1, 26)
+#define WL_REG_ON		IMX_GPIO_NR(1, 7)
+#define BT_NRST			IMX_GPIO_NR(7, 12)
+#define LVDS0_EN			IMX_GPIO_NR(2, 8)
+#define LVDS0_BL_EN			IMX_GPIO_NR(2, 9)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
+	/* Carrier MicroSD Card Detect */
+	IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	/* SOM MicroSD Card Detect */
+	IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const lvds_pads[] = {
+	/* lvds */
+	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart1_pads);
+}
+
+static bool cpu_is_pop(void)
+{
+	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
+	u32 ddr_map;
+
+	/* BOOT_CFG3[4] and BOOT_CFG3[5] */
+	ddr_map = (soc_sbmr >> 20) & 0x3;
+
+	if (ddr_map == 0x2)
+		return true;
+	else
+		return false;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+   { USDHC3_BASE_ADDR, 0, 8 },
+    {USDHC1_BASE_ADDR, 0, 8 },
+};
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+        return dev_no + 2;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+	u32 index = 0;
+
+	/*
+	 * Following map is done:
+	 * (USDHC)	(Physical Port)
+	 * usdhc3	SOM MicroSD/MMC
+	 * usdhc1	Carrier board MicroSD
+	 * Always set boot USDHC as mmc0
+	 */
+
+	SETUP_IOMUX_PADS(usdhc3_pads);
+	gpio_direction_input(USDHC3_CD_GPIO);
+
+	SETUP_IOMUX_PADS(usdhc1_pads);
+	gpio_direction_input(USDHC1_CD_GPIO);
+
+	switch (get_boot_device()) {
+		case SD1_BOOT:
+			usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			break;
+
+		case SD3_BOOT:
+		default:
+			usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			usdhc_cfg[0].max_bus_width = 4;
+			usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			usdhc_cfg[1].max_bus_width = 4;
+			break;
+	}
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int check_mmc_autodetect(void)
+{
+	char *autodetect_str = env_get("mmcautodetect");
+
+	if ((autodetect_str != NULL) &&
+		(strcmp(autodetect_str, "yes") == 0)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+void board_late_mmc_init(void)
+{
+	char cmd[32];
+	char mmcblk[32];
+	u32 dev_no = mmc_get_env_dev();
+
+	if (!check_mmc_autodetect())
+		return;
+
+	env_set_ulong("mmcdev", dev_no);
+
+	/* Set mmcblk env */
+	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
+		mmc_map_to_kernel_blk(dev_no));
+	env_set("mmcroot", mmcblk);
+
+	sprintf(cmd, "mmc dev %d", dev_no);
+	run_command(cmd, 0);
+}
+
+static int mx6_rgmii_rework(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe7;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	mx6_rgmii_rework(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO_IPUV3)
+struct i2c_pads_info mx6q_i2c2_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+struct i2c_pads_info mx6dl_i2c2_pad_info = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 12)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
+			| MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(4, 13)
+	}
+};
+
+struct i2c_pads_info mx6q_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6Q_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+
+struct i2c_pads_info mx6dl_i2c3_pad_info = {
+	.scl = {
+		.i2c_mode = MX6DL_PAD_EIM_D17__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(3, 17)
+	},
+	.sda = {
+		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | MUX_PAD_CTRL(I2C_PAD_CTRL),
+		.gp = IMX_GPIO_NR(3, 18)
+	}
+};
+#endif
+
+#if defined(CONFIG_VIDEO_IPUV3)
+static iomux_v3_cfg_t const ej050na_pads[] = {
+	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+	IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04	| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+	IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
+	IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
+	IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
+	IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
+	IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
+	IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
+	IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+	IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
+};
+
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+	imx_enable_hdmi_phy();
+}
+
+static int detect_i2c(struct display_info_t const *dev)
+{
+	return (0 == i2c_set_bus_num(dev->bus)) &&
+			(0 == i2c_probe(dev->addr));
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+	struct iomuxc *iomux = (struct iomuxc *)
+				IOMUXC_BASE_ADDR;
+
+	/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
+	u32 reg = readl(&iomux->gpr[2]);
+	reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
+	writel(reg, &iomux->gpr[2]);
+
+	/* Enable Backlight - use GPIO for Brightness adjustment */
+	SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
+	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+
+	SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
+	gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
+}
+
+static void enable_ej050na(struct display_info_t const *dev)
+{
+	SETUP_IOMUX_PADS(ej050na_pads);
+
+	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
+	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
+}
+
+struct display_info_t const displays[] = {{
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt = IPU_PIX_FMT_RGB24,
+	.detect = NULL,
+	.enable = enable_lvds,
+	.mode	= {
+		.name		= "hj070na",
+		.refresh	= 60,
+		.xres		= 1024,
+		.yres		= 600,
+		.pixclock	= 15385,
+		.left_margin	= 220,
+		.right_margin	= 40,
+		.upper_margin	= 21,
+		.lower_margin	= 7,
+		.hsync_len	= 60,
+		.vsync_len	= 10,
+		.sync		= FB_SYNC_EXT,
+		.vmode		= FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= -1,
+	.addr	= 0,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_hdmi,
+	.enable	= do_enable_hdmi,
+	.mode	= {
+		.name           = "HDMI",
+		.refresh        = 60,
+		.xres           = 1024,
+		.yres           = 768,
+		.pixclock       = 15385,
+		.left_margin    = 220,
+		.right_margin   = 40,
+		.upper_margin   = 21,
+		.lower_margin   = 7,
+		.hsync_len      = 60,
+		.vsync_len      = 10,
+		.sync           = FB_SYNC_EXT,
+		.vmode          = FB_VMODE_NONINTERLACED
+} }, {
+	.bus	= 1,
+	.addr	= 0x38,
+	.pixfmt	= IPU_PIX_FMT_RGB24,
+	.detect	= detect_i2c,
+	.enable	= enable_ej050na,
+	.mode	= {
+		.name           = "EJ050NA",
+		.refresh        = 60,
+		.xres           = 800,
+		.yres           = 480,
+		.pixclock       = 29850,
+		.left_margin    = 89,
+		.right_margin   = 64,
+		.upper_margin   = 23,
+		.lower_margin   = 10,
+		.hsync_len      = 10,
+		.vsync_len      = 10,
+		.sync           = 0,
+		.vmode          = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int reg;
+
+	/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
+	SETUP_IOMUX_PADS(lvds_pads);
+	gpio_direction_output(LVDS0_EN, 1);
+	gpio_direction_output(LVDS0_BL_EN, 1);
+
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
+	reg = __raw_readl(&mxc_ccm->CCGR3);
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
+	writel(reg, &mxc_ccm->CCGR3);
+
+	/* set LDB0, LDB1 clk select to 011/011 */
+	reg = readl(&mxc_ccm->cs2cdr);
+	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+		| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+		 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->cs2cdr);
+
+	reg = readl(&mxc_ccm->cscmr2);
+	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
+	writel(reg, &mxc_ccm->cscmr2);
+
+	reg = readl(&mxc_ccm->chsccdr);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+		<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+
+	 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+		| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
+		| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
+		| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+		| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+		| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
+		| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+	writel(reg, &iomux->gpr[2]);
+	reg = readl(&iomux->gpr[3]);
+
+	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
+		| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
+		| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+		<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+
+	writel(reg, &iomux->gpr[3]);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+#if 0 // fix me, cause exception
+	setup_iomux_enet();
+	return cpu_eth_init(bis);
+#endif
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
+	return 0;
+}
+
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+	return 1;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
+	{NULL,	 0},
+};
+#endif
+
+#define I2C_PMIC	1
+int board_init_pmic(void) {
+	struct pmic *p;
+	unsigned int reg;
+
+    power_pfuze100_init(1);
+
+	/* configure PFUZE100 PMIC */
+	power_pfuze100_init(I2C_PMIC);
+	p = pmic_get("PFUZE100");
+	if (p && !pmic_probe(p)) {
+		pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+		printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+		/* Set VGEN2 to 1.5V and enable */
+		pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
+		reg &= ~(LDO_VOL_MASK);
+		reg |= (LDOA_1_50V | (1 << (LDO_EN)));
+		pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
+	}
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+
+#ifdef CONFIG_CMD_BMODE
+	add_board_boot_modes(board_boot_modes);
+#endif
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+	board_late_mmc_init();
+#endif
+
+	set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#if defined(CONFIG_VIDEO_IPUV3)
+	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+		//setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
+	} else {
+		//setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c1_pad_info);
+		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
+	}
+#endif
+	return 0;
+}
+
+int checkboard(void)
+{
+	if (cpu_is_pop())
+		printf("Board: pico-imx6-pop\n");
+	else
+		printf("Board: pico-imx6\n");
+
+	printf("Available baseboard: dwarf, hobbit, nymph\n");
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+int is_recovery_key_pressing(void)
+{
+    return 0;
+
+}
+#endif /*CONFIG_ANDROID_RECOVERY*/
+#endif /*CONFIG_FSL_FASTBOOT*/
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4	0x020e0774 0x000C0000
+DATA 4	0x020e0754 0x00000000
+DATA 4	0x020e04ac 0x00000028
+DATA 4	0x020e04b0 0x00000028
+DATA 4	0x020e0464 0x00000028
+DATA 4	0x020e0490 0x00000028
+DATA 4	0x020e074c 0x00000028
+DATA 4	0x020e0494 0x00000028
+DATA 4	0x020e04a0 0x00000000
+DATA 4	0x020e04b4 0x00000028
+DATA 4	0x020e04b8 0x00000028
+DATA 4	0x020e076c 0x00000028
+DATA 4	0x020e0750 0x00020000
+DATA 4	0x020e04bc 0x00000028
+DATA 4	0x020e04c0 0x00000028
+DATA 4	0x020e04c4 0x00000028
+DATA 4	0x020e04c8 0x00000028
+DATA 4	0x020e0760 0x00020000
+DATA 4	0x020e0764 0x00000028
+DATA 4	0x020e0770 0x00000028
+DATA 4	0x020e0778 0x00000028
+DATA 4	0x020e077c 0x00000028
+DATA 4	0x020e0470 0x00000028
+DATA 4	0x020e0474 0x00000028
+DATA 4	0x020e0478 0x00000028
+DATA 4	0x020e047c 0x00000028
+
+DATA 4	0x021b0800 0xA1390003
+
+DATA 4	0x021b080c 0x003D0044
+DATA 4	0x021b0810 0x0036003A
+
+DATA 4	0x021b083c 0x0240023C
+DATA 4	0x021b0840 0x0224022C
+
+DATA 4	0x021b0848 0x42464848
+
+DATA 4	0x021b0850 0x3A383636
+
+DATA 4	0x021b081c 0x33333333
+DATA 4	0x021b0820 0x33333333
+DATA 4	0x021b0824 0x33333333
+DATA 4	0x021b0828 0x33333333
+
+DATA 4	0x021b08b8 0x00000800
+
+DATA 4	0x021b0004 0x0002002D
+DATA 4	0x021b0008 0x00333040
+DATA 4	0x021b000c 0x676B5333
+DATA 4	0x021b0010 0xB68E8B63
+DATA 4	0x021b0014 0x01FF00DB
+
+DATA 4	0x021b0018 0x00011740
+DATA 4	0x021b001c 0x00008000
+DATA 4	0x021b002c 0x000026D2
+DATA 4	0x021b0030 0x006B1023
+DATA 4	0x021b0040 0x00000027
+DATA 4	0x021b0000 0x84190000
+
+DATA 4	0x021b001c 0x02008032
+DATA 4	0x021b001c 0x00008033
+DATA 4	0x021b001c 0x00048031
+DATA 4	0x021b001c 0x05208030
+DATA 4  0x021b001c 0x04008040
+
+DATA 4	0x021b0020 0x00007800
+DATA 4	0x021b0818 0x00022227
+
+DATA 4	0x021b0004 0x0002556D
+DATA 4	0x021b0404 0x00011006
+DATA 4	0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6dl/pico-imx6dl.cfg,ANDROID_THINGS_SUPPORT"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_PICO_IMX6DL=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_FASTBOOT=y
+CONFIG_CMD_FASTBOOT=y
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_BOOTDELAY=-2
+CONFIG_EFI_PARTITION=y
+CONFIG_VIDEO=y
+CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_MMC=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
+/*
+ * Copyright (C) 2015 Technexion Ltd.
+ * Copyright 2017-2018 NXP
+ *
+ * Configuration settings for the Technexion Pico i.mx6DL board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __PICO_IMX6DL_CONFIG_H
+#define __PICO_IMX6DL_CONFIG_H
+
+#include "mx6_common.h"
+
+#undef CONFIG_LDO_BYPASS_CHECK
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+/* MMC Configs */
+/* #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC3_BASE_ADDR */
+/* #define CONFIG_SYS_FSL_USDHC_NUM	1 */
+
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM        2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       USDHC3_BASE_ADDR
+
+
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV 1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             RMII
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1  /* need board rework */
+#define CONFIG_FEC_XCV_TYPE             RMII
+#endif
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#endif
+
+/* I2C configs */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+#endif
+
+#ifdef CONFIG_DEFAULT_FDT_FILE
+#undef CONFIG_DEFAULT_FDT_FILE
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-pico.dtb"
+#endif
+
+#define PHYS_SDRAM_SIZE                        SZ_512M
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+
+/* Framebuffer */
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"clk_ignore_unused "\
+		"\0" \
+	"loadaddr=0x12000000\0" \
+	"fdt_addr=0x18000000\0" \
+	"initrd_addr=0x12C00000\0" \
+	"initrd_high=0xffffffff\0" \
+	"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"splashpos=m,m\0" \
+	"som=autodetect\0" \
+	"baseboard=dwarf\0" \
+	"default_baseboard=dwarf\0" \
+	"fdtfile=undefined\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x18000000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else run netboot; fi"
+
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+#define CONFIG_ENV_OFFSET		(384 * 1024)
+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
+#define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET		(60 << 20)
+#define CONFIG_ENV_SECT_SIZE		(128 << 10)
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#endif
+
+#define CONFIG_SYS_MMC_ENV_DEV		0  /* USDHC3 */
+#define CONFIG_SYS_MMC_ENV_PART		1	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* USDHC3 */
+
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define PRODUCT_NAME "imx6dl_pico"
+#define VARIANT_NAME "imx6dl_pico"
+
+#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
+#include "pico-imx6dl_android_things.h"
+#endif
+
+#endif
+
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __PICO_IMX6DL_ANDROID_THINGS_H
+#define __PICO_IMX6DL_ANDROID_THINGS_H
+#include "mx_android_common.h"
+/* For NAND we don't support lock/unlock */
+#ifndef CONFIG_NAND_BOOT
+#define CONFIG_FASTBOOT_LOCK
+#define CONFIG_ENABLE_LOCKSTATUS_SUPPORT
+#define FSL_FASTBOOT_FB_DEV "mmc"
+#endif
+
+#define CONFIG_ANDROID_AB_SUPPORT
+#define CONFIG_FSL_CAAM_KB
+#define CONFIG_CMD_FSL_CAAM_KB
+#define CONFIG_SHA1
+#define CONFIG_SHA256
+
+#define CONFIG_AVB_SUPPORT
+#define CONFIG_SYSTEM_RAMDISK_SUPPORT
+#ifdef CONFIG_AVB_SUPPORT
+
+#ifdef CONFIG_SYS_MALLOC_LEN
+#undef CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_MALLOC_LEN		(32 * SZ_1M)
+#endif
+
+#define CONFIG_SUPPORT_EMMC_RPMB
+/* fuse bank size in word */
+#define CONFIG_AVB_FUSE_BANK_SIZEW 8
+#define CONFIG_AVB_FUSE_BANK_START 10
+#define CONFIG_AVB_FUSE_BANK_END 15
+#endif
+
+#endif
+/* __PICO_IMX6DL_ANDROID_THINGS_H */
...	...	@@ -482,6 +482,14 @@
482	482	select SUPPORT_SPL
483	483	imply CMD_SATA
484	484
	485	+config TARGET_PICO_IMX6DL
	486	+ bool "Support pico-imx6dl"
	487	+ select MX6QDL
	488	+ select BOARD_LATE_INIT
	489	+ select DM
	490	+ select DM_THERMAL
	491	+ select BOARD_EARLY_INIT_F
	492	+
485	493	config TARGET_PICO_IMX6UL
486	494	bool "PICO-IMX6UL-EMMC"
487	495	select MX6UL
...	...	@@ -631,6 +639,7 @@
631	639	source "board/sks-kinkel/sksimx6/Kconfig"
632	640	source "board/solidrun/mx6cuboxi/Kconfig"
633	641	source "board/technexion/pico-imx6ul/Kconfig"
	642	+source "board/technexion/pico-imx6dl/Kconfig"
634	643	source "board/tbs/tbs2910/Kconfig"
635	644	source "board/tqc/tqma6/Kconfig"
636	645	source "board/toradex/apalis_imx6/Kconfig"
...	...	@@ -1461,7 +1461,7 @@
1461	1461	}
1462	1462	#endif
1463	1463
1464		-#if defined(CONFIG_MX6Q) \|\| defined(CONFIG_MX6DL) \|\| \
	1464	+#if defined(CONFIG_MX6QDL) \|\| defined(CONFIG_MX6Q) \|\| defined(CONFIG_MX6DL) \|\| \
1465	1465	defined(CONFIG_MX6S)
1466	1466	static void disable_ldb_di_clock_sources(void)
1467	1467	{
	1	+if TARGET_PICO_IMX6DL
	2	+
	3	+config SYS_BOARD
	4	+ default "pico-imx6dl"
	5	+
	6	+config SYS_VENDOR
	7	+ default "technexion"
	8	+
	9	+config SYS_SOC
	10	+ default "mx6"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "pico-imx6dl"
	14	+
	15	+endif
	1	+Technexion PICO-IMX6 board
	2	+M: Richard Hu <richard.hu@technexion.com>
	3	+S: Maintained
	4	+F: board/pico-imx6dl/
	5	+F: include/configs/pico-imx6dl.h
	6	+F: configs/pico-imx6dl_defconfig
	1	+#
	2	+# (C) Copyright 2015 Technexion Ltd.
	3	+# (C) Copyright 2017 NXP
	4	+#
	5	+# SPDX-License-Identifier: GPL-2.0+
	6	+#
	7	+
	8	+obj-y := pico-imx6dl.o
	1	+/*
	2	+ * Copyright (C) 2015 Technexion Ltd.
	3	+ * Copyright 2017 NXP
	4	+ *
	5	+ * Author: Richard Hu <richard.hu@technexion.com>
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#include <asm/arch/clock.h>
	11	+#include <asm/arch/crm_regs.h>
	12	+#include <asm/arch/iomux.h>
	13	+#include <asm/arch/imx-regs.h>
	14	+#include <asm/arch/mx6-pins.h>
	15	+#include <asm/arch/mxc_hdmi.h>
	16	+#include <asm/arch/sys_proto.h>
	17	+#include <asm/gpio.h>
	18	+#include <asm/mach-imx/iomux-v3.h>
	19	+#include <asm/mach-imx/mxc_i2c.h>
	20	+#include <asm/mach-imx/boot_mode.h>
	21	+#include <asm/mach-imx/video.h>
	22	+#include <asm/io.h>
	23	+#include <linux/sizes.h>
	24	+#include <common.h>
	25	+#include <fsl_esdhc.h>
	26	+#include <mmc.h>
	27	+#include <miiphy.h>
	28	+#include <netdev.h>
	29	+#include <phy.h>
	30	+#include <input.h>
	31	+#include <i2c.h>
	32	+#include <power/pmic.h>
	33	+#include <power/pfuze100_pmic.h>
	34	+
	35	+DECLARE_GLOBAL_DATA_PTR;
	36	+
	37	+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	38	+ PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	39	+ PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	40	+
	41	+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	42	+ PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	43	+ PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	44	+
	45	+#define BASEBOARD_USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	46	+ PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_40ohm \| \
	47	+ PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	48	+
	49	+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	50	+ PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	51	+
	52	+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	53	+ PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	54	+ PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	55	+
	56	+#define USDHC1_CD_GPIO IMX_GPIO_NR(3, 9)
	57	+#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 2)
	58	+#define ETH_PHY_RESET IMX_GPIO_NR(1, 26)
	59	+#define WL_REG_ON IMX_GPIO_NR(1, 7)
	60	+#define BT_NRST IMX_GPIO_NR(7, 12)
	61	+#define LVDS0_EN IMX_GPIO_NR(2, 8)
	62	+#define LVDS0_BL_EN IMX_GPIO_NR(2, 9)
	63	+
	64	+int dram_init(void)
	65	+{
	66	+ gd->ram_size = imx_ddr_size();
	67	+
	68	+ return 0;
	69	+}
	70	+
	71	+static iomux_v3_cfg_t const uart1_pads[] = {
	72	+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	73	+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
	74	+};
	75	+
	76	+static iomux_v3_cfg_t const usdhc1_pads[] = {
	77	+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	78	+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	79	+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	80	+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	81	+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	82	+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 \| MUX_PAD_CTRL(BASEBOARD_USDHC_PAD_CTRL)),
	83	+ /* Carrier MicroSD Card Detect */
	84	+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	85	+};
	86	+
	87	+static iomux_v3_cfg_t const usdhc3_pads[] = {
	88	+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	89	+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	90	+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	91	+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	92	+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	93	+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	94	+ /* SOM MicroSD Card Detect */
	95	+ IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	96	+};
	97	+
	98	+static iomux_v3_cfg_t const lvds_pads[] = {
	99	+ /* lvds */
	100	+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	101	+ IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	102	+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	103	+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	104	+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	105	+};
	106	+
	107	+static void setup_iomux_uart(void)
	108	+{
	109	+ SETUP_IOMUX_PADS(uart1_pads);
	110	+}
	111	+
	112	+static bool cpu_is_pop(void)
	113	+{
	114	+ u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
	115	+ u32 ddr_map;
	116	+
	117	+ /* BOOT_CFG3[4] and BOOT_CFG3[5] */
	118	+ ddr_map = (soc_sbmr >> 20) & 0x3;
	119	+
	120	+ if (ddr_map == 0x2)
	121	+ return true;
	122	+ else
	123	+ return false;
	124	+}
	125	+
	126	+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	127	+ { USDHC3_BASE_ADDR, 0, 8 },
	128	+ {USDHC1_BASE_ADDR, 0, 8 },
	129	+};
	130	+
	131	+int mmc_map_to_kernel_blk(int dev_no)
	132	+{
	133	+ return dev_no + 2;
	134	+}
	135	+
	136	+int board_mmc_getcd(struct mmc *mmc)
	137	+{
	138	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	139	+ int ret = 0;
	140	+
	141	+ switch (cfg->esdhc_base) {
	142	+ case USDHC1_BASE_ADDR:
	143	+ ret = !gpio_get_value(USDHC1_CD_GPIO);
	144	+ break;
	145	+ case USDHC3_BASE_ADDR:
	146	+ ret = !gpio_get_value(USDHC3_CD_GPIO);
	147	+ break;
	148	+ }
	149	+
	150	+ return ret;
	151	+}
	152	+
	153	+int board_mmc_init(bd_t *bis)
	154	+{
	155	+ int ret;
	156	+ u32 index = 0;
	157	+
	158	+ /*
	159	+ * Following map is done:
	160	+ * (USDHC) (Physical Port)
	161	+ * usdhc3 SOM MicroSD/MMC
	162	+ * usdhc1 Carrier board MicroSD
	163	+ * Always set boot USDHC as mmc0
	164	+ */
	165	+
	166	+ SETUP_IOMUX_PADS(usdhc3_pads);
	167	+ gpio_direction_input(USDHC3_CD_GPIO);
	168	+
	169	+ SETUP_IOMUX_PADS(usdhc1_pads);
	170	+ gpio_direction_input(USDHC1_CD_GPIO);
	171	+
	172	+ switch (get_boot_device()) {
	173	+ case SD1_BOOT:
	174	+ usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
	175	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	176	+ usdhc_cfg[0].max_bus_width = 4;
	177	+ usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
	178	+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	179	+ usdhc_cfg[1].max_bus_width = 4;
	180	+ break;
	181	+
	182	+ case SD3_BOOT:
	183	+ default:
	184	+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
	185	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	186	+ usdhc_cfg[0].max_bus_width = 4;
	187	+ usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR;
	188	+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	189	+ usdhc_cfg[1].max_bus_width = 4;
	190	+ break;
	191	+ }
	192	+
	193	+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
	194	+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
	195	+ if (ret)
	196	+ return ret;
	197	+ }
	198	+
	199	+ return 0;
	200	+}
	201	+
	202	+int check_mmc_autodetect(void)
	203	+{
	204	+ char *autodetect_str = env_get("mmcautodetect");
	205	+
	206	+ if ((autodetect_str != NULL) &&
	207	+ (strcmp(autodetect_str, "yes") == 0)) {
	208	+ return 1;
	209	+ }
	210	+
	211	+ return 0;
	212	+}
	213	+
	214	+void board_late_mmc_init(void)
	215	+{
	216	+ char cmd[32];
	217	+ char mmcblk[32];
	218	+ u32 dev_no = mmc_get_env_dev();
	219	+
	220	+ if (!check_mmc_autodetect())
	221	+ return;
	222	+
	223	+ env_set_ulong("mmcdev", dev_no);
	224	+
	225	+ /* Set mmcblk env */
	226	+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
	227	+ mmc_map_to_kernel_blk(dev_no));
	228	+ env_set("mmcroot", mmcblk);
	229	+
	230	+ sprintf(cmd, "mmc dev %d", dev_no);
	231	+ run_command(cmd, 0);
	232	+}
	233	+
	234	+static int mx6_rgmii_rework(struct phy_device *phydev)
	235	+{
	236	+ unsigned short val;
	237	+
	238	+ /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
	239	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	240	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	241	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	242	+
	243	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	244	+ val &= 0xffe7;
	245	+ val \|= 0x18;
	246	+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	247	+
	248	+ /* introduce tx clock delay */
	249	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	250	+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	251	+ val \|= 0x0100;
	252	+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	253	+
	254	+ return 0;
	255	+}
	256	+
	257	+int board_phy_config(struct phy_device *phydev)
	258	+{
	259	+ mx6_rgmii_rework(phydev);
	260	+
	261	+ if (phydev->drv->config)
	262	+ phydev->drv->config(phydev);
	263	+
	264	+ return 0;
	265	+}
	266	+
	267	+#if defined(CONFIG_VIDEO_IPUV3)
	268	+struct i2c_pads_info mx6q_i2c2_pad_info = {
	269	+ .scl = {
	270	+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
	271	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	272	+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
	273	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	274	+ .gp = IMX_GPIO_NR(4, 12)
	275	+ },
	276	+ .sda = {
	277	+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
	278	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	279	+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
	280	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	281	+ .gp = IMX_GPIO_NR(4, 13)
	282	+ }
	283	+};
	284	+
	285	+struct i2c_pads_info mx6dl_i2c2_pad_info = {
	286	+ .scl = {
	287	+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
	288	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	289	+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
	290	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	291	+ .gp = IMX_GPIO_NR(4, 12)
	292	+ },
	293	+ .sda = {
	294	+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
	295	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	296	+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
	297	+ \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	298	+ .gp = IMX_GPIO_NR(4, 13)
	299	+ }
	300	+};
	301	+
	302	+struct i2c_pads_info mx6q_i2c3_pad_info = {
	303	+ .scl = {
	304	+ .i2c_mode = MX6Q_PAD_EIM_D17__I2C3_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	305	+ .gpio_mode = MX6Q_PAD_EIM_D17__GPIO3_IO17 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	306	+ .gp = IMX_GPIO_NR(3, 17)
	307	+ },
	308	+ .sda = {
	309	+ .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	310	+ .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	311	+ .gp = IMX_GPIO_NR(3, 18)
	312	+ }
	313	+};
	314	+
	315	+struct i2c_pads_info mx6dl_i2c3_pad_info = {
	316	+ .scl = {
	317	+ .i2c_mode = MX6DL_PAD_EIM_D17__I2C3_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	318	+ .gpio_mode = MX6DL_PAD_EIM_D17__GPIO3_IO17 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	319	+ .gp = IMX_GPIO_NR(3, 17)
	320	+ },
	321	+ .sda = {
	322	+ .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	323	+ .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	324	+ .gp = IMX_GPIO_NR(3, 18)
	325	+ }
	326	+};
	327	+#endif
	328	+
	329	+#if defined(CONFIG_VIDEO_IPUV3)
	330	+static iomux_v3_cfg_t const ej050na_pads[] = {
	331	+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	332	+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
	333	+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
	334	+ IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 \| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
	335	+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
	336	+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
	337	+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
	338	+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
	339	+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
	340	+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
	341	+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
	342	+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
	343	+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
	344	+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
	345	+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
	346	+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
	347	+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
	348	+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
	349	+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
	350	+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
	351	+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
	352	+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
	353	+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
	354	+ IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18),
	355	+ IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19),
	356	+ IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20),
	357	+ IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21),
	358	+ IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22),
	359	+ IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23),
	360	+ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
	361	+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
	362	+};
	363	+
	364	+static void do_enable_hdmi(struct display_info_t const *dev)
	365	+{
	366	+ imx_enable_hdmi_phy();
	367	+}
	368	+
	369	+static int detect_i2c(struct display_info_t const *dev)
	370	+{
	371	+ return (0 == i2c_set_bus_num(dev->bus)) &&
	372	+ (0 == i2c_probe(dev->addr));
	373	+}
	374	+
	375	+static void enable_lvds(struct display_info_t const *dev)
	376	+{
	377	+ struct iomuxc iomux = (struct iomuxc )
	378	+ IOMUXC_BASE_ADDR;
	379	+
	380	+ /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
	381	+ u32 reg = readl(&iomux->gpr[2]);
	382	+ reg \|= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
	383	+ writel(reg, &iomux->gpr[2]);
	384	+
	385	+ /* Enable Backlight - use GPIO for Brightness adjustment */
	386	+ SETUP_IOMUX_PAD(PAD_SD4_DAT1__GPIO2_IO09);
	387	+ gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
	388	+
	389	+ SETUP_IOMUX_PAD(PAD_SD4_DAT0__GPIO2_IO08);
	390	+ gpio_direction_output(IMX_GPIO_NR(2, 8), 1);
	391	+}
	392	+
	393	+static void enable_ej050na(struct display_info_t const *dev)
	394	+{
	395	+ SETUP_IOMUX_PADS(ej050na_pads);
	396	+
	397	+ gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
	398	+ gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
	399	+}
	400	+
	401	+struct display_info_t const displays[] = {{
	402	+ .bus = -1,
	403	+ .addr = 0,
	404	+ .pixfmt = IPU_PIX_FMT_RGB24,
	405	+ .detect = NULL,
	406	+ .enable = enable_lvds,
	407	+ .mode = {
	408	+ .name = "hj070na",
	409	+ .refresh = 60,
	410	+ .xres = 1024,
	411	+ .yres = 600,
	412	+ .pixclock = 15385,
	413	+ .left_margin = 220,
	414	+ .right_margin = 40,
	415	+ .upper_margin = 21,
	416	+ .lower_margin = 7,
	417	+ .hsync_len = 60,
	418	+ .vsync_len = 10,
	419	+ .sync = FB_SYNC_EXT,
	420	+ .vmode = FB_VMODE_NONINTERLACED
	421	+} }, {
	422	+ .bus = -1,
	423	+ .addr = 0,
	424	+ .pixfmt = IPU_PIX_FMT_RGB24,
	425	+ .detect = detect_hdmi,
	426	+ .enable = do_enable_hdmi,
	427	+ .mode = {
	428	+ .name = "HDMI",
	429	+ .refresh = 60,
	430	+ .xres = 1024,
	431	+ .yres = 768,
	432	+ .pixclock = 15385,
	433	+ .left_margin = 220,
	434	+ .right_margin = 40,
	435	+ .upper_margin = 21,
	436	+ .lower_margin = 7,
	437	+ .hsync_len = 60,
	438	+ .vsync_len = 10,
	439	+ .sync = FB_SYNC_EXT,
	440	+ .vmode = FB_VMODE_NONINTERLACED
	441	+} }, {
	442	+ .bus = 1,
	443	+ .addr = 0x38,
	444	+ .pixfmt = IPU_PIX_FMT_RGB24,
	445	+ .detect = detect_i2c,
	446	+ .enable = enable_ej050na,
	447	+ .mode = {
	448	+ .name = "EJ050NA",
	449	+ .refresh = 60,
	450	+ .xres = 800,
	451	+ .yres = 480,
	452	+ .pixclock = 29850,
	453	+ .left_margin = 89,
	454	+ .right_margin = 64,
	455	+ .upper_margin = 23,
	456	+ .lower_margin = 10,
	457	+ .hsync_len = 10,
	458	+ .vsync_len = 10,
	459	+ .sync = 0,
	460	+ .vmode = FB_VMODE_NONINTERLACED
	461	+} } };
	462	+size_t display_count = ARRAY_SIZE(displays);
	463	+
	464	+static void setup_display(void)
	465	+{
	466	+ struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	467	+ struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	468	+ int reg;
	469	+
	470	+ /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
	471	+ SETUP_IOMUX_PADS(lvds_pads);
	472	+ gpio_direction_output(LVDS0_EN, 1);
	473	+ gpio_direction_output(LVDS0_BL_EN, 1);
	474	+
	475	+ enable_ipu_clock();
	476	+ imx_setup_hdmi();
	477	+
	478	+ reg = __raw_readl(&mxc_ccm->CCGR3);
	479	+ reg \|= MXC_CCM_CCGR3_LDB_DI0_MASK \| MXC_CCM_CCGR3_LDB_DI1_MASK;
	480	+ writel(reg, &mxc_ccm->CCGR3);
	481	+
	482	+ /* set LDB0, LDB1 clk select to 011/011 */
	483	+ reg = readl(&mxc_ccm->cs2cdr);
	484	+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
	485	+ \| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
	486	+ reg \|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
	487	+ \| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
	488	+ writel(reg, &mxc_ccm->cs2cdr);
	489	+
	490	+ reg = readl(&mxc_ccm->cscmr2);
	491	+ reg \|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV \| MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
	492	+ writel(reg, &mxc_ccm->cscmr2);
	493	+
	494	+ reg = readl(&mxc_ccm->chsccdr);
	495	+ reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
	496	+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	497	+ reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
	498	+ << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
	499	+ writel(reg, &mxc_ccm->chsccdr);
	500	+
	501	+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
	502	+ \| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
	503	+ \| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
	504	+ \| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
	505	+ \| IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
	506	+ \| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
	507	+ \| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
	508	+ \| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
	509	+ \| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
	510	+ writel(reg, &iomux->gpr[2]);
	511	+ reg = readl(&iomux->gpr[3]);
	512	+
	513	+ reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
	514	+ \| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
	515	+ \| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
	516	+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
	517	+
	518	+ writel(reg, &iomux->gpr[3]);
	519	+}
	520	+#endif /* CONFIG_VIDEO_IPUV3 */
	521	+
	522	+int board_eth_init(bd_t *bis)
	523	+{
	524	+#if 0 // fix me, cause exception
	525	+ setup_iomux_enet();
	526	+ return cpu_eth_init(bis);
	527	+#endif
	528	+
	529	+ return 0;
	530	+}
	531	+
	532	+int board_early_init_f(void)
	533	+{
	534	+ setup_iomux_uart();
	535	+#if defined(CONFIG_VIDEO_IPUV3)
	536	+ setup_display();
	537	+#endif
	538	+ return 0;
	539	+}
	540	+
	541	+/*
	542	+ * Do not overwrite the console
	543	+ * Use always serial for U-Boot console
	544	+ */
	545	+int overwrite_console(void)
	546	+{
	547	+ return 1;
	548	+}
	549	+
	550	+#ifdef CONFIG_CMD_BMODE
	551	+static const struct boot_mode board_boot_modes[] = {
	552	+ /* 4 bit bus width */
	553	+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	554	+ {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
	555	+ {NULL, 0},
	556	+};
	557	+#endif
	558	+
	559	+#define I2C_PMIC 1
	560	+int board_init_pmic(void) {
	561	+ struct pmic *p;
	562	+ unsigned int reg;
	563	+
	564	+ power_pfuze100_init(1);
	565	+
	566	+ /* configure PFUZE100 PMIC */
	567	+ power_pfuze100_init(I2C_PMIC);
	568	+ p = pmic_get("PFUZE100");
	569	+ if (p && !pmic_probe(p)) {
	570	+ pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
	571	+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
	572	+
	573	+ /* Set VGEN2 to 1.5V and enable */
	574	+ pmic_reg_read(p, PFUZE100_VGEN2VOL, &reg);
	575	+ reg &= ~(LDO_VOL_MASK);
	576	+ reg \|= (LDOA_1_50V \| (1 << (LDO_EN)));
	577	+ pmic_reg_write(p, PFUZE100_VGEN2VOL, reg);
	578	+ }
	579	+
	580	+ return 0;
	581	+}
	582	+
	583	+int board_late_init(void)
	584	+{
	585	+
	586	+#ifdef CONFIG_CMD_BMODE
	587	+ add_board_boot_modes(board_boot_modes);
	588	+#endif
	589	+
	590	+#ifdef CONFIG_ENV_IS_IN_MMC
	591	+ board_late_mmc_init();
	592	+#endif
	593	+
	594	+ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
	595	+
	596	+ return 0;
	597	+}
	598	+
	599	+int board_init(void)
	600	+{
	601	+ /* address of boot parameters */
	602	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	603	+
	604	+#if defined(CONFIG_VIDEO_IPUV3)
	605	+ if (is_cpu_type(MXC_CPU_MX6Q) \|\| is_cpu_type(MXC_CPU_MX6D)) {
	606	+ //setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
	607	+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
	608	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
	609	+ } else {
	610	+ //setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c1_pad_info);
	611	+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
	612	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
	613	+ }
	614	+#endif
	615	+ return 0;
	616	+}
	617	+
	618	+int checkboard(void)
	619	+{
	620	+ if (cpu_is_pop())
	621	+ printf("Board: pico-imx6-pop\n");
	622	+ else
	623	+ printf("Board: pico-imx6\n");
	624	+
	625	+ printf("Available baseboard: dwarf, hobbit, nymph\n");
	626	+
	627	+ return 0;
	628	+}
	629	+
	630	+#ifdef CONFIG_FSL_FASTBOOT
	631	+#ifdef CONFIG_ANDROID_RECOVERY
	632	+int is_recovery_key_pressing(void)
	633	+{
	634	+ return 0;
	635	+
	636	+}
	637	+#endif /CONFIG_ANDROID_RECOVERY/
	638	+#endif /CONFIG_FSL_FASTBOOT/
	1	+/*
	2	+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ *
	6	+ * Refer docs/README.imxmage for more details about how-to configure
	7	+ * and create imximage boot image
	8	+ *
	9	+ * The syntax is taken as close as possible with the kwbimage
	10	+ */
	11	+
	12	+#define __ASSEMBLY__
	13	+#include <config.h>
	14	+/* image version */
	15	+
	16	+IMAGE_VERSION 2
	17	+
	18	+/*
	19	+ * Boot Device : one of
	20	+ * spi, sd (the board has no nand neither onenand)
	21	+ */
	22	+
	23	+BOOT_FROM sd
	24	+
	25	+#ifdef CONFIG_SECURE_BOOT
	26	+CSF CONFIG_CSF_SIZE
	27	+#endif
	28	+
	29	+/*
	30	+ * Device Configuration Data (DCD)
	31	+ *
	32	+ * Each entry must have the format:
	33	+ * Addr-type Address Value
	34	+ *
	35	+ * where:
	36	+ * Addr-type register length (1,2 or 4 bytes)
	37	+ * Address absolute address of the register
	38	+ * value value to be stored in the register
	39	+ */
	40	+DATA 4 0x020e0774 0x000C0000
	41	+DATA 4 0x020e0754 0x00000000
	42	+DATA 4 0x020e04ac 0x00000028
	43	+DATA 4 0x020e04b0 0x00000028
	44	+DATA 4 0x020e0464 0x00000028
	45	+DATA 4 0x020e0490 0x00000028
	46	+DATA 4 0x020e074c 0x00000028
	47	+DATA 4 0x020e0494 0x00000028
	48	+DATA 4 0x020e04a0 0x00000000
	49	+DATA 4 0x020e04b4 0x00000028
	50	+DATA 4 0x020e04b8 0x00000028
	51	+DATA 4 0x020e076c 0x00000028
	52	+DATA 4 0x020e0750 0x00020000
	53	+DATA 4 0x020e04bc 0x00000028
	54	+DATA 4 0x020e04c0 0x00000028
	55	+DATA 4 0x020e04c4 0x00000028
	56	+DATA 4 0x020e04c8 0x00000028
	57	+DATA 4 0x020e0760 0x00020000
	58	+DATA 4 0x020e0764 0x00000028
	59	+DATA 4 0x020e0770 0x00000028
	60	+DATA 4 0x020e0778 0x00000028
	61	+DATA 4 0x020e077c 0x00000028
	62	+DATA 4 0x020e0470 0x00000028
	63	+DATA 4 0x020e0474 0x00000028
	64	+DATA 4 0x020e0478 0x00000028
	65	+DATA 4 0x020e047c 0x00000028
	66	+
	67	+DATA 4 0x021b0800 0xA1390003
	68	+
	69	+DATA 4 0x021b080c 0x003D0044
	70	+DATA 4 0x021b0810 0x0036003A
	71	+
	72	+DATA 4 0x021b083c 0x0240023C
	73	+DATA 4 0x021b0840 0x0224022C
	74	+
	75	+DATA 4 0x021b0848 0x42464848
	76	+
	77	+DATA 4 0x021b0850 0x3A383636
	78	+
	79	+DATA 4 0x021b081c 0x33333333
	80	+DATA 4 0x021b0820 0x33333333
	81	+DATA 4 0x021b0824 0x33333333
	82	+DATA 4 0x021b0828 0x33333333
	83	+
	84	+DATA 4 0x021b08b8 0x00000800
	85	+
	86	+DATA 4 0x021b0004 0x0002002D
	87	+DATA 4 0x021b0008 0x00333040
	88	+DATA 4 0x021b000c 0x676B5333
	89	+DATA 4 0x021b0010 0xB68E8B63
	90	+DATA 4 0x021b0014 0x01FF00DB
	91	+
	92	+DATA 4 0x021b0018 0x00011740
	93	+DATA 4 0x021b001c 0x00008000
	94	+DATA 4 0x021b002c 0x000026D2
	95	+DATA 4 0x021b0030 0x006B1023
	96	+DATA 4 0x021b0040 0x00000027
	97	+DATA 4 0x021b0000 0x84190000
	98	+
	99	+DATA 4 0x021b001c 0x02008032
	100	+DATA 4 0x021b001c 0x00008033
	101	+DATA 4 0x021b001c 0x00048031
	102	+DATA 4 0x021b001c 0x05208030
	103	+DATA 4 0x021b001c 0x04008040
	104	+
	105	+DATA 4 0x021b0020 0x00007800
	106	+DATA 4 0x021b0818 0x00022227
	107	+
	108	+DATA 4 0x021b0004 0x0002556D
	109	+DATA 4 0x021b0404 0x00011006
	110	+DATA 4 0x021b001c 0x00000000
	111	+
	112	+/* set the default clock gate to save power */
	113	+DATA 4 0x020c4068 0x00C03F3F
	114	+DATA 4 0x020c406c 0x0030FC03
	115	+DATA 4 0x020c4070 0x0FFFC000
	116	+DATA 4 0x020c4074 0x3FF00000
	117	+DATA 4 0x020c4078 0x00FFF300
	118	+DATA 4 0x020c407c 0x0F0000C3
	119	+DATA 4 0x020c4080 0x000003FF
	120	+
	121	+/* enable AXI cache for VDOA/VPU/IPU */
	122	+DATA 4 0x020e0010 0xF00000CF
	123	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	124	+DATA 4 0x020e0018 0x007F007F
	125	+DATA 4 0x020e001c 0x007F007F
	1	+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx6dl/pico-imx6dl.cfg,ANDROID_THINGS_SUPPORT"
	2	+CONFIG_ARM=y
	3	+CONFIG_ARCH_MX6=y
	4	+CONFIG_TARGET_PICO_IMX6DL=y
	5	+CONFIG_SYS_TEXT_BASE=0x17800000
	6	+CONFIG_SYS_MALLOC_F=y
	7	+CONFIG_SYS_MALLOC_F_LEN=0x400
	8	+CONFIG_FASTBOOT=y
	9	+CONFIG_CMD_FASTBOOT=y
	10	+CONFIG_ANDROID_BOOT_IMAGE=y
	11	+CONFIG_BOOTDELAY=-2
	12	+CONFIG_EFI_PARTITION=y
	13	+CONFIG_VIDEO=y
	14	+CONFIG_ENV_IS_IN_MMC=y
	15	+# CONFIG_CONSOLE_MUX is not set
	16	+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
	17	+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
	18	+CONFIG_HUSH_PARSER=y
	19	+CONFIG_CMD_BOOTZ=y
	20	+# CONFIG_CMD_IMLS is not set
	21	+CONFIG_CMD_MEMTEST=y
	22	+# CONFIG_CMD_FLASH is not set
	23	+CONFIG_CMD_MMC=y
	24	+CONFIG_CMD_USB=y
	25	+CONFIG_CMD_GPIO=y
	26	+CONFIG_CMD_DHCP=y
	27	+CONFIG_CMD_MII=y
	28	+CONFIG_CMD_PING=y
	29	+CONFIG_CMD_CACHE=y
	30	+CONFIG_CMD_EXT2=y
	31	+CONFIG_CMD_EXT4=y
	32	+CONFIG_CMD_EXT4_WRITE=y
	33	+CONFIG_CMD_FAT=y
	34	+CONFIG_CMD_FS_GENERIC=y
	35	+CONFIG_DFU_MMC=y
	36	+CONFIG_USB=y
	37	+CONFIG_USB_STORAGE=y
	38	+CONFIG_OF_LIBFDT=y
	39	+CONFIG_DM=y
	40	+CONFIG_DM_THERMAL=y
	1	+/*
	2	+ * Copyright (C) 2015 Technexion Ltd.
	3	+ * Copyright 2017-2018 NXP
	4	+ *
	5	+ * Configuration settings for the Technexion Pico i.mx6DL board.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+#ifndef __PICO_IMX6DL_CONFIG_H
	10	+#define __PICO_IMX6DL_CONFIG_H
	11	+
	12	+#include "mx6_common.h"
	13	+
	14	+#undef CONFIG_LDO_BYPASS_CHECK
	15	+
	16	+/* Size of malloc() pool */
	17	+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
	18	+
	19	+#define CONFIG_MXC_UART
	20	+#define CONFIG_MXC_UART_BASE UART1_BASE
	21	+
	22	+/* MMC Configs */
	23	+/* #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR */
	24	+/* #define CONFIG_SYS_FSL_USDHC_NUM 1 */
	25	+
	26	+
	27	+/* MMC Configuration */
	28	+#define CONFIG_FSL_ESDHC
	29	+#define CONFIG_FSL_USDHC
	30	+#define CONFIG_SYS_FSL_USDHC_NUM 2
	31	+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
	32	+
	33	+
	34	+
	35	+#ifdef CONFIG_CMD_NET
	36	+#define CONFIG_FEC_MXC
	37	+#define CONFIG_MII
	38	+#define CONFIG_FEC_ENET_DEV 1
	39	+
	40	+#if (CONFIG_FEC_ENET_DEV == 0)
	41	+#define IMX_FEC_BASE ENET_BASE_ADDR
	42	+#define CONFIG_FEC_MXC_PHYADDR 0x2
	43	+#define CONFIG_FEC_XCV_TYPE RMII
	44	+#elif (CONFIG_FEC_ENET_DEV == 1)
	45	+#define IMX_FEC_BASE ENET2_BASE_ADDR
	46	+#define CONFIG_FEC_MXC_PHYADDR 0x1 /* need board rework */
	47	+#define CONFIG_FEC_XCV_TYPE RMII
	48	+#endif
	49	+#define CONFIG_ETHPRIME "FEC"
	50	+
	51	+#define CONFIG_PHYLIB
	52	+#define CONFIG_PHY_MICREL
	53	+#endif
	54	+
	55	+/* I2C configs */
	56	+#define CONFIG_CMD_I2C
	57	+#ifdef CONFIG_CMD_I2C
	58	+#define CONFIG_SYS_I2C
	59	+#define CONFIG_SYS_I2C_MXC
	60	+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
	61	+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
	62	+#define CONFIG_SYS_I2C_SPEED 100000
	63	+#endif
	64	+
	65	+#ifdef CONFIG_DEFAULT_FDT_FILE
	66	+#undef CONFIG_DEFAULT_FDT_FILE
	67	+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-pico.dtb"
	68	+#endif
	69	+
	70	+#define PHYS_SDRAM_SIZE SZ_512M
	71	+
	72	+/* PMIC */
	73	+#define CONFIG_POWER
	74	+#define CONFIG_POWER_I2C
	75	+#define CONFIG_POWER_PFUZE100
	76	+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
	77	+
	78	+
	79	+/* Framebuffer */
	80	+#define CONFIG_VIDEO_IPUV3
	81	+#define CONFIG_VIDEO_BMP_RLE8
	82	+#define CONFIG_SPLASH_SCREEN
	83	+#define CONFIG_SPLASH_SCREEN_ALIGN
	84	+#define CONFIG_BMP_16BPP
	85	+#define CONFIG_VIDEO_LOGO
	86	+#define CONFIG_VIDEO_BMP_LOGO
	87	+#define CONFIG_CMD_HDMIDETECT
	88	+#define CONFIG_IMX_HDMI
	89	+#define CONFIG_IMX_VIDEO_SKIP
	90	+
	91	+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
	92	+
	93	+#define CONFIG_MFG_ENV_SETTINGS \
	94	+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
	95	+ "rdinit=/linuxrc " \
	96	+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
	97	+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
	98	+ "g_mass_storage.iSerialNumber=\"\" "\
	99	+ "clk_ignore_unused "\
	100	+ "\0" \
	101	+ "loadaddr=0x12000000\0" \
	102	+ "fdt_addr=0x18000000\0" \
	103	+ "initrd_addr=0x12C00000\0" \
	104	+ "initrd_high=0xffffffff\0" \
	105	+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
	106	+
	107	+
	108	+#define CONFIG_EXTRA_ENV_SETTINGS \
	109	+ CONFIG_MFG_ENV_SETTINGS \
	110	+ "script=boot.scr\0" \
	111	+ "image=zImage\0" \
	112	+ "console=ttymxc0\0" \
	113	+ "splashpos=m,m\0" \
	114	+ "som=autodetect\0" \
	115	+ "baseboard=dwarf\0" \
	116	+ "default_baseboard=dwarf\0" \
	117	+ "fdtfile=undefined\0" \
	118	+ "fdt_high=0xffffffff\0" \
	119	+ "initrd_high=0xffffffff\0" \
	120	+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
	121	+ "fdt_addr=0x18000000\0" \
	122	+ "boot_fdt=try\0" \
	123	+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	124	+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	125	+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	126	+ "mmcautodetect=yes\0" \
	127	+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
	128	+ "root=${mmcroot}\0" \
	129	+ "loadbootscript=" \
	130	+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	131	+ "bootscript=echo Running bootscript from mmc ...; " \
	132	+ "source\0" \
	133	+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	134	+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	135	+ "mmcboot=echo Booting from mmc ...; " \
	136	+ "run mmcargs; " \
	137	+ "if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	138	+ "if run loadfdt; then " \
	139	+ "bootz ${loadaddr} - ${fdt_addr}; " \
	140	+ "else " \
	141	+ "if test ${boot_fdt} = try; then " \
	142	+ "bootz; " \
	143	+ "else " \
	144	+ "echo WARN: Cannot load the DT; " \
	145	+ "fi; " \
	146	+ "fi; " \
	147	+ "else " \
	148	+ "bootz; " \
	149	+ "fi;\0"
	150	+
	151	+#define CONFIG_BOOTCOMMAND \
	152	+ "mmc dev ${mmcdev};" \
	153	+ "mmc dev ${mmcdev}; if mmc rescan; then " \
	154	+ "if run loadbootscript; then " \
	155	+ "run bootscript; " \
	156	+ "else " \
	157	+ "if run loadimage; then " \
	158	+ "run mmcboot; " \
	159	+ "else run netboot; " \
	160	+ "fi; " \
	161	+ "fi; " \
	162	+ "else run netboot; fi"
	163	+
	164	+#define CONFIG_SYS_MEMTEST_START 0x80000000
	165	+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
	166	+
	167	+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	168	+#define CONFIG_SYS_HZ 1000
	169	+
	170	+/* Physical Memory Map */
	171	+#define CONFIG_NR_DRAM_BANKS 1
	172	+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	173	+
	174	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	175	+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	176	+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	177	+
	178	+#define CONFIG_SYS_INIT_SP_OFFSET \
	179	+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	180	+#define CONFIG_SYS_INIT_SP_ADDR \
	181	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	182	+
	183	+#define CONFIG_ENV_SIZE SZ_8K
	184	+
	185	+#ifdef CONFIG_CMD_NAND
	186	+#define CONFIG_CMD_NAND_TRIMFFS
	187	+
	188	+/* NAND stuff */
	189	+#define CONFIG_NAND_MXS
	190	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	191	+#define CONFIG_SYS_NAND_BASE 0x40000000
	192	+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	193	+#define CONFIG_SYS_NAND_ONFI_DETECTION
	194	+
	195	+/* DMA stuff, needed for GPMI/MXS NAND support */
	196	+#define CONFIG_APBH_DMA
	197	+#define CONFIG_APBH_DMA_BURST
	198	+#define CONFIG_APBH_DMA_BURST8
	199	+#endif
	200	+
	201	+#if defined(CONFIG_ENV_IS_IN_MMC)
	202	+#define CONFIG_ENV_OFFSET (12 * SZ_64K)
	203	+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
	204	+#define CONFIG_ENV_OFFSET (384 * 1024)
	205	+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	206	+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
	207	+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	208	+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
	209	+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	210	+#elif defined(CONFIG_ENV_IS_IN_NAND)
	211	+#undef CONFIG_ENV_SIZE
	212	+#define CONFIG_ENV_OFFSET (60 << 20)
	213	+#define CONFIG_ENV_SECT_SIZE (128 << 10)
	214	+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	215	+#endif
	216	+
	217	+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC3 */
	218	+#define CONFIG_SYS_MMC_ENV_PART 1 /* user area */
	219	+#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
	220	+
	221	+
	222	+/* USB Configs */
	223	+#ifdef CONFIG_CMD_USB
	224	+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	225	+#define CONFIG_USB_HOST_ETHER
	226	+#define CONFIG_USB_ETHER_ASIX
	227	+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI \| PORT_PTS_PTW)
	228	+#define CONFIG_MXC_USB_FLAGS 0
	229	+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	230	+#endif
	231	+
	232	+#define PRODUCT_NAME "imx6dl_pico"
	233	+#define VARIANT_NAME "imx6dl_pico"
	234	+
	235	+#if defined(CONFIG_ANDROID_THINGS_SUPPORT)
	236	+#include "pico-imx6dl_android_things.h"
	237	+#endif
	238	+
	239	+#endif