Eric Lee / smarc-uboot

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Commit 1001502545ff0125c39232cf0e7f26d9213ab55f

Authored by Trevor Woerner
Committed by Tom Rini
1 parent a0aba8a2eb
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

CONFIG_SPL_SYS_[DI]CACHE_OFF: add 

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>

Showing 92 changed files with 206 additions and 114 deletions Side-by-side Diff

... ... @@ -114,11 +114,25 @@
114 114 help
115 115 Do not enable instruction cache in U-Boot.
116 116  
  117 +config SPL_SYS_ICACHE_OFF
  118 + bool "Do not enable icache in SPL"
  119 + depends on SPL
  120 + default SYS_ICACHE_OFF
  121 + help
  122 + Do not enable instruction cache in SPL.
  123 +
117 124 config SYS_DCACHE_OFF
118 125 bool "Do not enable dcache"
119 126 default n
120 127 help
121 128 Do not enable data cache in U-Boot.
  129 +
  130 +config SPL_SYS_DCACHE_OFF
  131 + bool "Do not enable dcache in SPL"
  132 + depends on SPL
  133 + default SYS_DCACHE_OFF
  134 + help
  135 + Do not enable data cache in SPL.
122 136  
123 137 menuconfig ARC_DBG
124 138 bool "ARC debugging"
arch/arc/lib/start.S
Diff comments   View file @ 1001502
... ... @@ -16,7 +16,7 @@
16 16 lr r5, [ARC_BCR_IC_BUILD]
17 17 breq r5, 0, 1f ; I$ doesn't exist
18 18 lr r5, [ARC_AUX_IC_CTRL]
19   -#ifndef CONFIG_SYS_ICACHE_OFF
  19 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
20 20 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
21 21 #else
22 22 bset r5, r5, 0 ; I$ exists, but is not used
... ... @@ -37,7 +37,7 @@
37 37 breq r5, 0, 1f ; D$ doesn't exist
38 38 lr r5, [ARC_AUX_DC_CTRL]
39 39 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
40   -#ifndef CONFIG_SYS_DCACHE_OFF
  40 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
41 41 bclr r5, r5, 0 ; Enable (+Inv)
42 42 #else
43 43 bset r5, r5, 0 ; Disable (+Inv)
... ... @@ -80,11 +80,25 @@
80 80 help
81 81 Do not enable instruction cache in U-Boot.
82 82  
  83 +config SPL_SYS_ICACHE_OFF
  84 + bool "Do not enable icache in SPL"
  85 + depends on SPL
  86 + default SYS_ICACHE_OFF
  87 + help
  88 + Do not enable instruction cache in SPL.
  89 +
83 90 config SYS_DCACHE_OFF
84 91 bool "Do not enable dcache"
85 92 default n
86 93 help
87 94 Do not enable data cache in U-Boot.
  95 +
  96 +config SPL_SYS_DCACHE_OFF
  97 + bool "Do not enable dcache in SPL"
  98 + depends on SPL
  99 + default SYS_DCACHE_OFF
  100 + help
  101 + Do not enable data cache in SPL.
88 102  
89 103 config SYS_ARM_CACHE_CP15
90 104 bool "CP15 based cache enabling support"
arch/arm/cpu/arm11/cpu.c
Diff comments   View file @ 1001502
... ... @@ -51,7 +51,7 @@
51 51 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i));
52 52 }
53 53  
54   -#ifndef CONFIG_SYS_DCACHE_OFF
  54 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
55 55 void invalidate_dcache_all(void)
56 56 {
57 57 asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
... ... @@ -87,7 +87,7 @@
87 87 asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
88 88 }
89 89  
90   -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  90 +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
91 91 void invalidate_dcache_all(void)
92 92 {
93 93 }
94 94  
95 95  
96 96  
... ... @@ -95,15 +95,15 @@
95 95 void flush_dcache_all(void)
96 96 {
97 97 }
98   -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  98 +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
99 99  
100   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  100 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
101 101 void enable_caches(void)
102 102 {
103   -#ifndef CONFIG_SYS_ICACHE_OFF
  103 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
104 104 icache_enable();
105 105 #endif
106   -#ifndef CONFIG_SYS_DCACHE_OFF
  106 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
107 107 dcache_enable();
108 108 #endif
109 109 }
arch/arm/cpu/arm926ejs/cache.c
Diff comments   View file @ 1001502
... ... @@ -6,7 +6,7 @@
6 6 #include <linux/types.h>
7 7 #include <common.h>
8 8  
9   -#ifndef CONFIG_SYS_DCACHE_OFF
  9 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
10 10 void invalidate_dcache_all(void)
11 11 {
12 12 asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
... ... @@ -46,7 +46,7 @@
46 46  
47 47 asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
48 48 }
49   -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  49 +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
50 50 void invalidate_dcache_all(void)
51 51 {
52 52 }
... ... @@ -54,7 +54,7 @@
54 54 void flush_dcache_all(void)
55 55 {
56 56 }
57   -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  57 +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
58 58  
59 59 /*
60 60 * Stub implementations for l2 cache operations
... ... @@ -66,7 +66,7 @@
66 66 __weak void invalidate_l2_cache(void) {}
67 67 #endif
68 68  
69   -#ifndef CONFIG_SYS_ICACHE_OFF
  69 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
70 70 /* Invalidate entire I-cache and branch predictor array */
71 71 void invalidate_icache_all(void)
72 72 {
73 73  
... ... @@ -80,10 +80,10 @@
80 80  
81 81 void enable_caches(void)
82 82 {
83   -#ifndef CONFIG_SYS_ICACHE_OFF
  83 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
84 84 icache_enable();
85 85 #endif
86   -#ifndef CONFIG_SYS_DCACHE_OFF
  86 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
87 87 dcache_enable();
88 88 #endif
89 89 }
arch/arm/cpu/arm926ejs/cpu.c
Diff comments   View file @ 1001502
... ... @@ -44,7 +44,7 @@
44 44 /* flush I/D-cache */
45 45 static void cache_flush (void)
46 46 {
47   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  47 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
48 48 unsigned long i = 0;
49 49  
50 50 asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
arch/arm/cpu/arm926ejs/start.S
Diff comments   View file @ 1001502
... ... @@ -84,7 +84,7 @@
84 84  
85 85 /*
86 86 * disable MMU and D cache
87   - * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
  87 + * enable I cache if SYS_ICACHE_OFF is not defined
88 88 */
89 89 mrc p15, 0, r0, c1, c0, 0
90 90 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
... ... @@ -95,7 +95,7 @@
95 95 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
96 96 #endif
97 97 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
98   -#ifndef CONFIG_SYS_ICACHE_OFF
  98 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
99 99 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
100 100 #endif
101 101 mcr p15, 0, r0, c1, c0, 0
arch/arm/cpu/armv7/cache_v7.c
Diff comments   View file @ 1001502
... ... @@ -12,7 +12,7 @@
12 12 #define ARMV7_DCACHE_INVAL_RANGE 1
13 13 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
14 14  
15   -#ifndef CONFIG_SYS_DCACHE_OFF
  15 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
16 16  
17 17 /* Asm functions from cache_v7_asm.S */
18 18 void v7_flush_dcache_all(void);
... ... @@ -149,7 +149,7 @@
149 149 flush_dcache_range(start, stop);
150 150 v7_inval_tlb();
151 151 }
152   -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  152 +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
153 153 void invalidate_dcache_all(void)
154 154 {
155 155 }
156 156  
... ... @@ -177,9 +177,9 @@
177 177 void arm_init_domains(void)
178 178 {
179 179 }
180   -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  180 +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
181 181  
182   -#ifndef CONFIG_SYS_ICACHE_OFF
  182 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
183 183 /* Invalidate entire I-cache and branch predictor array */
184 184 void invalidate_icache_all(void)
185 185 {
arch/arm/cpu/armv7/iproc-common/hwinit-common.c
Diff comments   View file @ 1001502
... ... @@ -5,7 +5,7 @@
5 5  
6 6 #include <common.h>
7 7  
8   -#ifndef CONFIG_SYS_DCACHE_OFF
  8 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
9 9 void enable_caches(void)
10 10 {
11 11 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/cpu/armv7/kona-common/hwinit-common.c
Diff comments   View file @ 1001502
... ... @@ -6,7 +6,7 @@
6 6 #include <common.h>
7 7 #include <linux/sizes.h>
8 8  
9   -#ifndef CONFIG_SYS_DCACHE_OFF
  9 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
10 10 void enable_caches(void)
11 11 {
12 12 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/cpu/armv7/ls102xa/cpu.c
Diff comments   View file @ 1001502
... ... @@ -26,7 +26,7 @@
26 26  
27 27 DECLARE_GLOBAL_DATA_PTR;
28 28  
29   -#ifndef CONFIG_SYS_DCACHE_OFF
  29 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
30 30  
31 31 /*
32 32 * Bit[1] of the descriptor indicates the descriptor type,
... ... @@ -215,7 +215,7 @@
215 215 invalidate_dcache_all();
216 216 set_cr(get_cr() | CR_C);
217 217 }
218   -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  218 +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
219 219  
220 220  
221 221 uint get_svr(void)
arch/arm/cpu/armv7/start.S
Diff comments   View file @ 1001502
... ... @@ -97,7 +97,7 @@
97 97 /*
98 98 * If I-cache is enabled invalidate it
99 99 */
100   -#ifndef CONFIG_SYS_ICACHE_OFF
  100 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
101 101 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
102 102 mcr p15, 0, r0, c7, c10, 4 @ DSB
103 103 mcr p15, 0, r0, c7, c5, 4 @ ISB
... ... @@ -155,7 +155,7 @@
155 155 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
156 156 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
157 157 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
158   -#ifdef CONFIG_SYS_ICACHE_OFF
  158 +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
159 159 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
160 160 #else
161 161 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
arch/arm/cpu/armv7/vf610/generic.c
Diff comments   View file @ 1001502
... ... @@ -360,7 +360,7 @@
360 360 return 0;
361 361 }
362 362  
363   -#ifndef CONFIG_SYS_DCACHE_OFF
  363 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
364 364 void enable_caches(void)
365 365 {
366 366 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
arch/arm/cpu/armv7m/cache.c
Diff comments   View file @ 1001502
... ... @@ -54,7 +54,7 @@
54 54 FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
55 55 };
56 56  
57   -#ifndef CONFIG_SYS_DCACHE_OFF
  57 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
58 58 struct dcache_config {
59 59 u32 ways;
60 60 u32 sets;
... ... @@ -292,7 +292,7 @@
292 292 }
293 293 #endif
294 294  
295   -#ifndef CONFIG_SYS_ICACHE_OFF
  295 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
296 296  
297 297 void invalidate_icache_all(void)
298 298 {
299 299  
... ... @@ -349,10 +349,10 @@
349 349  
350 350 void enable_caches(void)
351 351 {
352   -#ifndef CONFIG_SYS_ICACHE_OFF
  352 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
353 353 icache_enable();
354 354 #endif
355   -#ifndef CONFIG_SYS_DCACHE_OFF
  355 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
356 356 dcache_enable();
357 357 #endif
358 358 }
arch/arm/cpu/armv8/cache_v8.c
Diff comments   View file @ 1001502
... ... @@ -13,7 +13,7 @@
13 13  
14 14 DECLARE_GLOBAL_DATA_PTR;
15 15  
16   -#ifndef CONFIG_SYS_DCACHE_OFF
  16 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
17 17  
18 18 /*
19 19 * With 4k page granule, a virtual address is split into 4 lookup parts
... ... @@ -657,7 +657,7 @@
657 657 __asm_invalidate_tlb_all();
658 658 }
659 659  
660   -#else /* CONFIG_SYS_DCACHE_OFF */
  660 +#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
661 661  
662 662 /*
663 663 * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
664 664  
... ... @@ -694,9 +694,9 @@
694 694 {
695 695 }
696 696  
697   -#endif /* CONFIG_SYS_DCACHE_OFF */
  697 +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
698 698  
699   -#ifndef CONFIG_SYS_ICACHE_OFF
  699 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
700 700  
701 701 void icache_enable(void)
702 702 {
... ... @@ -720,7 +720,7 @@
720 720 __asm_invalidate_l3_icache();
721 721 }
722 722  
723   -#else /* CONFIG_SYS_ICACHE_OFF */
  723 +#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
724 724  
725 725 void icache_enable(void)
726 726 {
... ... @@ -739,7 +739,7 @@
739 739 {
740 740 }
741 741  
742   -#endif /* CONFIG_SYS_ICACHE_OFF */
  742 +#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
743 743  
744 744 /*
745 745 * Enable dCache & iCache, whether cache is actually enabled
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 1001502
... ... @@ -388,7 +388,7 @@
388 388 strcpy(name, "unknown");
389 389 }
390 390  
391   -#ifndef CONFIG_SYS_DCACHE_OFF
  391 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
392 392 /*
393 393 * To start MMU before DDR is available, we create MMU table in SRAM.
394 394 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
... ... @@ -611,7 +611,7 @@
611 611 icache_enable();
612 612 dcache_enable();
613 613 }
614   -#endif /* CONFIG_SYS_DCACHE_OFF */
  614 +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
615 615  
616 616 #ifdef CONFIG_TFABOOT
617 617 enum boot_src __get_boot_src(u32 porsr1)
arch/arm/cpu/armv8/s32v234/cpu.c
Diff comments   View file @ 1001502
... ... @@ -16,7 +16,7 @@
16 16 return readl(MC_ME_CS);
17 17 }
18 18  
19   -#ifndef CONFIG_SYS_DCACHE_OFF
  19 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
20 20  
21 21 #define S32V234_IRAM_BASE 0x3e800000UL
22 22 #define S32V234_IRAM_SIZE 0x800000UL
arch/arm/cpu/pxa/cache.c
Diff comments   View file @ 1001502
... ... @@ -6,7 +6,7 @@
6 6 #include <linux/types.h>
7 7 #include <common.h>
8 8  
9   -#ifndef CONFIG_SYS_DCACHE_OFF
  9 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
10 10 void invalidate_dcache_all(void)
11 11 {
12 12 /* Flush/Invalidate I cache */
... ... @@ -35,7 +35,7 @@
35 35 {
36 36 return invalidate_dcache_range(start, stop);
37 37 }
38   -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
  38 +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
39 39 void invalidate_dcache_all(void)
40 40 {
41 41 }
... ... @@ -43,7 +43,7 @@
43 43 void flush_dcache_all(void)
44 44 {
45 45 }
46   -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
  46 +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
47 47  
48 48 /*
49 49 * Stub implementations for l2 cache operations
arch/arm/cpu/pxa/pxa2xx.c
Diff comments   View file @ 1001502
... ... @@ -286,10 +286,10 @@
286 286  
287 287 void enable_caches(void)
288 288 {
289   -#ifndef CONFIG_SYS_ICACHE_OFF
  289 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
290 290 icache_enable();
291 291 #endif
292   -#ifndef CONFIG_SYS_DCACHE_OFF
  292 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
293 293 dcache_enable();
294 294 #endif
295 295 }
arch/arm/include/asm/global_data.h
Diff comments   View file @ 1001502
... ... @@ -35,7 +35,7 @@
35 35 unsigned int tbl;
36 36 unsigned long lastinc;
37 37 unsigned long long timer_reset_value;
38   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  38 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
39 39 unsigned long tlb_addr;
40 40 unsigned long tlb_size;
41 41 #if defined(CONFIG_ARM64)
arch/arm/lib/cache-cp15.c
Diff comments   View file @ 1001502
... ... @@ -10,7 +10,7 @@
10 10 #include <linux/compiler.h>
11 11 #include <asm/armv7_mpu.h>
12 12  
13   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  13 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
14 14  
15 15 DECLARE_GLOBAL_DATA_PTR;
16 16  
... ... @@ -246,7 +246,7 @@
246 246 }
247 247 #endif
248 248  
249   -#ifdef CONFIG_SYS_ICACHE_OFF
  249 +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
250 250 void icache_enable (void)
251 251 {
252 252 return;
... ... @@ -278,7 +278,7 @@
278 278 }
279 279 #endif
280 280  
281   -#ifdef CONFIG_SYS_DCACHE_OFF
  281 +#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
282 282 void dcache_enable (void)
283 283 {
284 284 return;
arch/arm/lib/cache.c
Diff comments   View file @ 1001502
... ... @@ -87,7 +87,7 @@
87 87 noncached_end = end;
88 88 noncached_next = start;
89 89  
90   -#ifndef CONFIG_SYS_DCACHE_OFF
  90 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
91 91 mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF);
92 92 #endif
93 93 }
arch/arm/mach-exynos/soc.c
Diff comments   View file @ 1001502
... ... @@ -25,7 +25,7 @@
25 25 #endif
26 26 }
27 27  
28   -#ifndef CONFIG_SYS_DCACHE_OFF
  28 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
29 29 void enable_caches(void)
30 30 {
31 31 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-imx/cache.c
Diff comments   View file @ 1001502
... ... @@ -37,7 +37,7 @@
37 37 }
38 38 }
39 39  
40   -#ifndef CONFIG_SYS_DCACHE_OFF
  40 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
41 41 void enable_caches(void)
42 42 {
43 43 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
arch/arm/mach-imx/imx8/cpu.c
Diff comments   View file @ 1001502
... ... @@ -446,7 +446,7 @@
446 446 dcache_enable();
447 447 }
448 448  
449   -#ifndef CONFIG_SYS_DCACHE_OFF
  449 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
450 450 u64 get_page_table_size(void)
451 451 {
452 452 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
arch/arm/mach-imx/mx5/soc.c
Diff comments   View file @ 1001502
... ... @@ -62,7 +62,7 @@
62 62 }
63 63 #endif
64 64  
65   -#ifndef CONFIG_SYS_DCACHE_OFF
  65 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
66 66 void enable_caches(void)
67 67 {
68 68 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-keystone/init.c
Diff comments   View file @ 1001502
... ... @@ -204,7 +204,7 @@
204 204  
205 205 void enable_caches(void)
206 206 {
207   -#ifndef CONFIG_SYS_DCACHE_OFF
  207 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
208 208 /* Enable D-cache. I-cache is already enabled in start.S */
209 209 dcache_enable();
210 210 #endif
arch/arm/mach-omap2/Makefile
Diff comments   View file @ 1001502
... ... @@ -34,7 +34,7 @@
34 34 endif
35 35 endif
36 36  
37   -ifeq ($(CONFIG_SYS_DCACHE_OFF),)
  37 +ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),)
38 38 obj-y += omap-cache.o
39 39 endif
40 40  
arch/arm/mach-omap2/omap5/sec_entry_cpu1.S
Diff comments   View file @ 1001502
... ... @@ -16,7 +16,7 @@
16 16  
17 17 .arch_extension sec
18 18  
19   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  19 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
20 20 .global flush_dcache_range
21 21 #endif
22 22  
... ... @@ -79,7 +79,7 @@
79 79 push {r4, r5, lr}
80 80 ldr r4, =omap_smc_sec_cpu1_args
81 81 stm r4, {r0,r1,r2,r3} @ Save args to memory
82   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  82 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
83 83 mov r0, r4
84 84 mov r1, #CONFIG_SYS_CACHELINE_SIZE
85 85 add r1, r0, r1 @ dcache is not enabled on CPU1, so
... ... @@ -109,7 +109,7 @@
109 109 */
110 110 .section .data
111 111 omap_smc_sec_cpu1_args:
112   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  112 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
113 113 .balign CONFIG_SYS_CACHELINE_SIZE
114 114 .rept CONFIG_SYS_CACHELINE_SIZE/4
115 115 .word 0
arch/arm/mach-omap2/sec-common.c
Diff comments   View file @ 1001502
... ... @@ -333,7 +333,7 @@
333 333 debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0);
334 334 debug("tee_file_size = %d\n", tee_file_size);
335 335  
336   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  336 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
337 337 flush_dcache_range(
338 338 rounddown((u32)loadptr, ARCH_DMA_MINALIGN),
339 339 roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN));
... ... @@ -356,7 +356,7 @@
356 356 /* Reuse the tee_info buffer for SMC params */
357 357 smc_cpu1_params = (u32 *)&tee_info;
358 358 smc_cpu1_params[0] = 0;
359   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  359 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
360 360 flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params +
361 361 roundup(sizeof(u32), ARCH_DMA_MINALIGN));
362 362 #endif
arch/arm/mach-rmobile/cpu_info.c
Diff comments   View file @ 1001502
... ... @@ -17,7 +17,7 @@
17 17  
18 18 /* R-Car Gen3 D-cache is enabled in memmap-gen3.c */
19 19 #ifndef CONFIG_RCAR_GEN3
20   -#ifndef CONFIG_SYS_DCACHE_OFF
  20 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
21 21 void enable_caches(void)
22 22 {
23 23 dcache_enable();
arch/arm/mach-rockchip/rk3036-board.c
Diff comments   View file @ 1001502
... ... @@ -48,7 +48,7 @@
48 48 }
49 49 #endif
50 50  
51   -#ifndef CONFIG_SYS_DCACHE_OFF
  51 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
52 52 void enable_caches(void)
53 53 {
54 54 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-rockchip/rk3128-board.c
Diff comments   View file @ 1001502
... ... @@ -57,7 +57,7 @@
57 57 return 0;
58 58 }
59 59  
60   -#ifndef CONFIG_SYS_DCACHE_OFF
  60 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
61 61 void enable_caches(void)
62 62 {
63 63 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-rockchip/rk3188-board.c
Diff comments   View file @ 1001502
... ... @@ -75,7 +75,7 @@
75 75 #endif
76 76 }
77 77  
78   -#ifndef CONFIG_SYS_DCACHE_OFF
  78 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
79 79 void enable_caches(void)
80 80 {
81 81 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-rockchip/rk322x-board.c
Diff comments   View file @ 1001502
... ... @@ -58,7 +58,7 @@
58 58 return 0;
59 59 }
60 60  
61   -#ifndef CONFIG_SYS_DCACHE_OFF
  61 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
62 62 void enable_caches(void)
63 63 {
64 64 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-rockchip/rk3288-board.c
Diff comments   View file @ 1001502
... ... @@ -186,7 +186,7 @@
186 186 #endif
187 187 }
188 188  
189   -#ifndef CONFIG_SYS_DCACHE_OFF
  189 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
190 190 void enable_caches(void)
191 191 {
192 192 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-rockchip/rv1108/rv1108.c
Diff comments   View file @ 1001502
... ... @@ -6,7 +6,7 @@
6 6  
7 7 #include <common.h>
8 8  
9   -#ifndef CONFIG_SYS_DCACHE_OFF
  9 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
10 10 void enable_caches(void)
11 11 {
12 12 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-s5pc1xx/cache.c
Diff comments   View file @ 1001502
... ... @@ -9,7 +9,7 @@
9 9  
10 10 #include <common.h>
11 11  
12   -#ifndef CONFIG_SYS_DCACHE_OFF
  12 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
13 13 void enable_caches(void)
14 14 {
15 15 dcache_enable();
arch/arm/mach-socfpga/misc.c
Diff comments   View file @ 1001502
... ... @@ -48,10 +48,10 @@
48 48  
49 49 void enable_caches(void)
50 50 {
51   -#ifndef CONFIG_SYS_ICACHE_OFF
  51 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
52 52 icache_enable();
53 53 #endif
54   -#ifndef CONFIG_SYS_DCACHE_OFF
  54 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
55 55 dcache_enable();
56 56 #endif
57 57 }
arch/arm/mach-sunxi/board.c
Diff comments   View file @ 1001502
... ... @@ -300,7 +300,7 @@
300 300 #endif
301 301 }
302 302  
303   -#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  303 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
304 304 void enable_caches(void)
305 305 {
306 306 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-tegra/board.c
Diff comments   View file @ 1001502
... ... @@ -226,7 +226,7 @@
226 226 };
227 227 #endif
228 228  
229   -#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
  229 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
230 230 void enable_caches(void)
231 231 {
232 232 /* Enable D-cache. I-cache is already enabled in start.S */
arch/arm/mach-zynq/cpu.c
Diff comments   View file @ 1001502
... ... @@ -83,7 +83,7 @@
83 83 ;
84 84 }
85 85  
86   -#ifndef CONFIG_SYS_DCACHE_OFF
  86 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
87 87 void enable_caches(void)
88 88 {
89 89 /* Enable D-cache. I-cache is already enabled in start.S */
... ... @@ -22,11 +22,25 @@
22 22 help
23 23 Do not enable instruction cache in U-Boot.
24 24  
  25 +config SPL_SYS_ICACHE_OFF
  26 + bool "Do not enable icache in SPL"
  27 + depends on SPL
  28 + default SYS_ICACHE_OFF
  29 + help
  30 + Do not enable instruction cache in SPL.
  31 +
25 32 config SYS_DCACHE_OFF
26 33 bool "Do not enable dcache"
27 34 default n
28 35 help
29 36 Do not enable data cache in U-Boot.
  37 +
  38 +config SPL_SYS_DCACHE_OFF
  39 + bool "Do not enable dcache in SPL"
  40 + depends on SPL
  41 + default SYS_DCACHE_OFF
  42 + help
  43 + Do not enable data cache in SPL.
30 44  
31 45 source "board/AndesTech/adp-ag101p/Kconfig"
32 46 source "board/AndesTech/adp-ae3xx/Kconfig"
arch/nds32/cpu/n1213/start.S
Diff comments   View file @ 1001502
... ... @@ -129,7 +129,7 @@
129 129 mfsr $r1, $mr8
130 130 and $r1, $r1, $r0
131 131 mtsr $r1, $mr8
132   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  132 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
133 133 /*
134 134 * MMU_CTL NTC0 Cacheable/Write-Back
135 135 */
... ... @@ -139,7 +139,7 @@
139 139 mtsr $r1, $mr0
140 140 #endif
141 141  
142   -#ifndef CONFIG_SYS_DCACHE_OFF
  142 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
143 143 #ifdef CONFIG_ARCH_MAP_SYSMEM
144 144 /*
145 145 * MMU_CTL NTC1 Non-cacheable
146 146  
... ... @@ -158,14 +158,14 @@
158 158 #endif
159 159 #endif
160 160  
161   -#if !defined(CONFIG_SYS_ICACHE_OFF)
  161 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
162 162 li $r0, 0x1
163 163 mfsr $r1, $mr8
164 164 or $r1, $r1, $r0
165 165 mtsr $r1, $mr8
166 166 #endif
167 167  
168   -#if !defined(CONFIG_SYS_DCACHE_OFF)
  168 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
169 169 li $r0, 0x2
170 170 mfsr $r1, $mr8
171 171 or $r1, $r1, $r0
arch/nds32/lib/cache.c
Diff comments   View file @ 1001502
... ... @@ -6,7 +6,7 @@
6 6 */
7 7  
8 8 #include <common.h>
9   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  9 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
10 10 static inline unsigned long CACHE_SET(unsigned char cache)
11 11 {
12 12 if (cache == ICACHE)
... ... @@ -38,7 +38,7 @@
38 38 }
39 39 #endif
40 40  
41   -#ifndef CONFIG_SYS_ICACHE_OFF
  41 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
42 42 void invalidate_icache_all(void)
43 43 {
44 44 unsigned long end, line_size;
... ... @@ -133,7 +133,7 @@
133 133  
134 134 #endif
135 135  
136   -#ifndef CONFIG_SYS_DCACHE_OFF
  136 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
137 137 void dcache_wbinval_all(void)
138 138 {
139 139 unsigned long end, line_size;
... ... @@ -25,11 +25,25 @@
25 25 help
26 26 Do not enable instruction cache in U-Boot.
27 27  
  28 +config SPL_SYS_ICACHE_OFF
  29 + bool "Do not enable icache in SPL"
  30 + depends on SPL
  31 + default SYS_ICACHE_OFF
  32 + help
  33 + Do not enable instruction cache in SPL.
  34 +
28 35 config SYS_DCACHE_OFF
29 36 bool "Do not enable dcache"
30 37 default n
31 38 help
32 39 Do not enable data cache in U-Boot.
  40 +
  41 +config SPL_SYS_DCACHE_OFF
  42 + bool "Do not enable dcache in SPL"
  43 + depends on SPL
  44 + default SYS_DCACHE_OFF
  45 + help
  46 + Do not enable data cache in SPL.
33 47  
34 48 # board-specific options below
35 49 source "board/AndesTech/ax25-ae350/Kconfig"
arch/riscv/cpu/ax25/cache.c
Diff comments   View file @ 1001502
... ... @@ -30,7 +30,7 @@
30 30  
31 31 void icache_enable(void)
32 32 {
33   -#ifndef CONFIG_SYS_ICACHE_OFF
  33 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
34 34 #ifdef CONFIG_RISCV_NDS_CACHE
35 35 asm volatile (
36 36 "csrr t1, mcache_ctl\n\t"
... ... @@ -43,7 +43,7 @@
43 43  
44 44 void icache_disable(void)
45 45 {
46   -#ifndef CONFIG_SYS_ICACHE_OFF
  46 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
47 47 #ifdef CONFIG_RISCV_NDS_CACHE
48 48 asm volatile (
49 49 "fence.i\n\t"
... ... @@ -57,7 +57,7 @@
57 57  
58 58 void dcache_enable(void)
59 59 {
60   -#ifndef CONFIG_SYS_DCACHE_OFF
  60 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
61 61 #ifdef CONFIG_RISCV_NDS_CACHE
62 62 asm volatile (
63 63 "csrr t1, mcache_ctl\n\t"
... ... @@ -70,7 +70,7 @@
70 70  
71 71 void dcache_disable(void)
72 72 {
73   -#ifndef CONFIG_SYS_DCACHE_OFF
  73 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
74 74 #ifdef CONFIG_RISCV_NDS_CACHE
75 75 asm volatile (
76 76 "fence\n\t"
... ... @@ -22,11 +22,25 @@
22 22 help
23 23 Do not enable instruction cache in U-Boot.
24 24  
  25 +config SPL_SYS_ICACHE_OFF
  26 + bool "Do not enable icache in SPL"
  27 + depends on SPL
  28 + default SYS_ICACHE_OFF
  29 + help
  30 + Do not enable instruction cache in SPL.
  31 +
25 32 config SYS_DCACHE_OFF
26 33 bool "Do not enable dcache"
27 34 default n
28 35 help
29 36 Do not enable data cache in U-Boot.
  37 +
  38 +config SPL_SYS_DCACHE_OFF
  39 + bool "Do not enable dcache in SPL"
  40 + depends on SPL
  41 + default SYS_DCACHE_OFF
  42 + help
  43 + Do not enable data cache in SPL.
30 44  
31 45 source "board/cadence/xtfpga/Kconfig"
32 46  
arch/xtensa/cpu/start.S
Diff comments   View file @ 1001502
... ... @@ -164,18 +164,19 @@
164 164 * enable data/instruction cache for relocated image.
165 165 */
166 166 #if XCHAL_HAVE_SPANNING_WAY && \
167   - !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF))
  167 + !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \
  168 + CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
168 169 srli a7, a4, 29
169 170 slli a7, a7, 29
170 171 addi a7, a7, XCHAL_SPANNING_WAY
171   -#ifndef CONFIG_SYS_DCACHE_OFF
  172 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
172 173 rdtlb1 a8, a7
173 174 srli a8, a8, 4
174 175 slli a8, a8, 4
175 176 addi a8, a8, CA_WRITEBACK
176 177 wdtlb a8, a7
177 178 #endif
178   -#ifndef CONFIG_SYS_ICACHE_OFF
  179 +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
179 180 ritlb1 a8, a7
180 181 srli a8, a8, 4
181 182 slli a8, a8, 4
board/st/stih410-b2260/board.c
Diff comments   View file @ 1001502
... ... @@ -26,7 +26,7 @@
26 26 return 0;
27 27 }
28 28  
29   -#ifndef CONFIG_SYS_DCACHE_OFF
  29 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
30 30 void enable_caches(void)
31 31 {
32 32 /* Enable D-cache. I-cache is already enabled in start.S */
... ... @@ -321,7 +321,7 @@
321 321 print_eths();
322 322 #endif
323 323 print_baudrate();
324   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  324 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
325 325 print_num("TLB addr", gd->arch.tlb_addr);
326 326 #endif
327 327 print_num("relocaddr", gd->relocaddr);
... ... @@ -381,7 +381,7 @@
381 381 #ifdef CONFIG_ARM
382 382 __weak int reserve_mmu(void)
383 383 {
384   -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  384 +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
385 385 /* reserve TLB table */
386 386 gd->arch.tlb_size = PGTABLE_SIZE;
387 387 gd->relocaddr -= gd->arch.tlb_size;
... ... @@ -61,7 +61,7 @@
61 61 * architectures do not actually implement it. Is there a way to find
62 62 * out whether it exists? For now, ARM is safe.
63 63 */
64   -#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
  64 +#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
65 65 int line_length;
66 66  
67 67 if (lcd_flush_dcache)
configs/axm_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_SYS_THUMB_BUILD=y
3 4 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
4 5 # CONFIG_SPL_USE_ARCH_MEMSET is not set
configs/bitmain_antminer_s9_defconfig
Diff comments   View file @ 1001502
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_SYS_BOARD="antminer_s9"
4 4 CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9"
5 5 CONFIG_ARCH_ZYNQ=y
  6 +CONFIG_SPL_SYS_DCACHE_OFF=y
6 7 CONFIG_SYS_TEXT_BASE=0x4000000
7 8 CONFIG_ENV_OFFSET=0x300000
8 9 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/imx8mq_evk_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
2 2 CONFIG_ARCH_IMX8M=y
  3 +CONFIG_SPL_SYS_ICACHE_OFF=y
  4 +CONFIG_SPL_SYS_DCACHE_OFF=y
3 5 CONFIG_SYS_TEXT_BASE=0x40200000
4 6 CONFIG_SYS_MALLOC_F_LEN=0x2000
5 7 CONFIG_TARGET_IMX8MQ_EVK=y
configs/imx8qm_mek_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
2 2 CONFIG_ARCH_IMX8=y
  3 +CONFIG_SPL_SYS_ICACHE_OFF=y
  4 +CONFIG_SPL_SYS_DCACHE_OFF=y
3 5 CONFIG_SYS_TEXT_BASE=0x80020000
4 6 CONFIG_SPL_GPIO_SUPPORT=y
5 7 CONFIG_SPL_LIBCOMMON_SUPPORT=y
configs/imx8qxp_mek_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
2 2 CONFIG_ARCH_IMX8=y
  3 +CONFIG_SPL_SYS_ICACHE_OFF=y
  4 +CONFIG_SPL_SYS_DCACHE_OFF=y
3 5 CONFIG_SYS_TEXT_BASE=0x80020000
4 6 CONFIG_SPL_GPIO_SUPPORT=y
5 7 CONFIG_SPL_LIBCOMMON_SUPPORT=y
configs/smartweb_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,8 @@
2 2 CONFIG_SPL_SYS_THUMB_BUILD=y
3 3 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
4 4 # CONFIG_SPL_USE_ARCH_MEMSET is not set
  5 +CONFIG_SPL_SYS_ICACHE_OFF=y
  6 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 7 CONFIG_ARCH_AT91=y
6 8 CONFIG_SYS_TEXT_BASE=0x23000000
7 9 CONFIG_TARGET_SMARTWEB=y
configs/syzygy_hub_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,7 @@
2 2 CONFIG_SYS_VENDOR="opalkelly"
3 3 CONFIG_SYS_CONFIG_NAME="syzygy_hub"
4 4 CONFIG_ARCH_ZYNQ=y
  5 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 6 CONFIG_SYS_TEXT_BASE=0x4000000
6 7 CONFIG_SPL_STACK_R_ADDR=0x200000
7 8 CONFIG_SPL=y
configs/taurus_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,8 @@
2 2 CONFIG_SYS_THUMB_BUILD=y
3 3 # CONFIG_SPL_USE_ARCH_MEMCPY is not set
4 4 # CONFIG_SPL_USE_ARCH_MEMSET is not set
  5 +CONFIG_SPL_SYS_ICACHE_OFF=y
  6 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 7 CONFIG_ARCH_AT91=y
6 8 CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds"
7 9 CONFIG_SYS_TEXT_BASE=0x21000000
configs/topic_miami_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,7 @@
2 2 CONFIG_SYS_VENDOR="topic"
3 3 CONFIG_SYS_CONFIG_NAME="topic_miami"
4 4 CONFIG_ARCH_ZYNQ=y
  5 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 6 CONFIG_SYS_TEXT_BASE=0x4000000
6 7 CONFIG_SPL_STACK_R_ADDR=0x200000
7 8 CONFIG_SPL=y
configs/topic_miamilite_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,7 @@
2 2 CONFIG_SYS_VENDOR="topic"
3 3 CONFIG_SYS_CONFIG_NAME="topic_miami"
4 4 CONFIG_ARCH_ZYNQ=y
  5 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 6 CONFIG_SYS_TEXT_BASE=0x4000000
6 7 CONFIG_SPL_STACK_R_ADDR=0x200000
7 8 CONFIG_SPL=y
configs/topic_miamiplus_defconfig
Diff comments   View file @ 1001502
... ... @@ -2,6 +2,7 @@
2 2 CONFIG_SYS_VENDOR="topic"
3 3 CONFIG_SYS_CONFIG_NAME="topic_miami"
4 4 CONFIG_ARCH_ZYNQ=y
  5 +CONFIG_SPL_SYS_DCACHE_OFF=y
5 6 CONFIG_SYS_TEXT_BASE=0x4000000
6 7 CONFIG_SPL_STACK_R_ADDR=0x200000
7 8 CONFIG_SPL=y
configs/zynq_cc108_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_cse_nand_defconfig
Diff comments   View file @ 1001502
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_SYS_ICACHE_OFF=y
4 4 CONFIG_SYS_DCACHE_OFF=y
5 5 CONFIG_ARCH_ZYNQ=y
  6 +CONFIG_SPL_SYS_DCACHE_OFF=y
6 7 CONFIG_SYS_TEXT_BASE=0x100000
7 8 CONFIG_ENV_SIZE=0x190
8 9 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_cse_nor_defconfig
Diff comments   View file @ 1001502
... ... @@ -3,6 +3,7 @@
3 3 CONFIG_SYS_ICACHE_OFF=y
4 4 CONFIG_SYS_DCACHE_OFF=y
5 5 CONFIG_ARCH_ZYNQ=y
  6 +CONFIG_SPL_SYS_DCACHE_OFF=y
6 7 CONFIG_SYS_TEXT_BASE=0xFFFC0000
7 8 CONFIG_ENV_SIZE=0x190
8 9 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_dlc20_rev1_0_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_microzed_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_minized_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_picozed_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_z_turn_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc702_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc706_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc770_xm010_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc770_xm011_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc770_xm011_x16_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc770_xm012_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zc770_xm013_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zed_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zybo_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
configs/zynq_zybo_z7_defconfig
Diff comments   View file @ 1001502
1 1 CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_DCACHE_OFF=y
2 3 CONFIG_ARCH_ZYNQ=y
3 4 CONFIG_SYS_TEXT_BASE=0x4000000
4 5 CONFIG_SPL_STACK_R_ADDR=0x200000
drivers/dma/apbh_dma.c
Diff comments   View file @ 1001502
... ... @@ -81,7 +81,7 @@
81 81 return tmp;
82 82 }
83 83  
84   -#ifndef CONFIG_SYS_DCACHE_OFF
  84 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
85 85 void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
86 86 {
87 87 uint32_t addr;
drivers/mtd/nand/raw/mxs_nand.c
Diff comments   View file @ 1001502
... ... @@ -50,7 +50,7 @@
50 50 /*
51 51 * Cache management functions
52 52 */
53   -#ifndef CONFIG_SYS_DCACHE_OFF
  53 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
54 54 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
55 55 {
56 56 uint32_t addr = (uint32_t)info->data_buf;
drivers/net/dwc_eth_qos.c
Diff comments   View file @ 1001502
... ... @@ -241,7 +241,7 @@
241 241 */
242 242 #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
243 243 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
244   - !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  244 + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
245 245 #warning Cache line size is larger than descriptor size
246 246 #endif
247 247 #endif
drivers/net/rtl8169.c
Diff comments   View file @ 1001502
... ... @@ -302,7 +302,7 @@
302 302 */
303 303 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
304 304 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
305   - !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  305 + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
306 306 #warning cache-line size is larger than descriptor size
307 307 #endif
308 308 #endif
drivers/net/sh_eth.c
Diff comments   View file @ 1001502
... ... @@ -34,7 +34,8 @@
34 34 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
35 35 #endif
36 36  
37   -#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
  37 +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  38 + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
38 39 #define flush_cache_wback(addr, len) \
39 40 flush_dcache_range((u32)addr, \
40 41 (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
drivers/video/video-uclass.c
Diff comments   View file @ 1001502
... ... @@ -149,7 +149,7 @@
149 149 * architectures do not actually implement it. Is there a way to find
150 150 * out whether it exists? For now, ARM is safe.
151 151 */
152   -#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF)
  152 +#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
153 153 struct video_priv *priv = dev_get_uclass_priv(vid);
154 154  
155 155 if (priv->flush_dcache) {
include/configs/mx7ulp_evk.h
Diff comments   View file @ 1001502
... ... @@ -167,7 +167,7 @@
167 167 #define CONFIG_SYS_INIT_SP_ADDR \
168 168 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
169 169  
170   -#ifndef CONFIG_SYS_DCACHE_OFF
  170 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
171 171 #define CONFIG_CMD_CACHE
172 172 #endif
173 173  
include/configs/smartweb.h
Diff comments   View file @ 1001502
... ... @@ -216,11 +216,6 @@
216 216 #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
217 217 #define CONFIG_SYS_AT91_PLLB 0x10483f0e
218 218  
219   -#if defined(CONFIG_SPL_BUILD)
220   -#define CONFIG_SYS_ICACHE_OFF
221   -#define CONFIG_SYS_DCACHE_OFF
222   -#endif
223   -
224 219 #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
225 220 #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
226 221  
include/configs/taurus.h
Diff comments   View file @ 1001502
... ... @@ -21,10 +21,6 @@
21 21 #include <asm/hardware.h>
22 22 #include <linux/sizes.h>
23 23  
24   -#if defined(CONFIG_SPL_BUILD)
25   -#define CONFIG_SYS_ICACHE_OFF
26   -#define CONFIG_SYS_DCACHE_OFF
27   -#endif
28 24 /*
29 25 * Warning: changing CONFIG_SYS_TEXT_BASE requires
30 26 * adapting the initial boot program.
include/configs/zynq-common.h
Diff comments   View file @ 1001502
... ... @@ -284,11 +284,6 @@
284 284 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
285 285 #endif
286 286  
287   -/* Disable dcache for SPL just for sure */
288   -#ifdef CONFIG_SPL_BUILD
289   -#define CONFIG_SYS_DCACHE_OFF
290   -#endif
291   -
292 287 /* Address in RAM where the parameters must be copied by SPL. */
293 288 #define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000
294 289