Eric Lee / smarc-uboot

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Commit 10918c03a9761db3ef8b57ca46a20d39e0be41e6

Authored by Tom Rini
2 parents e35c6c7978 a67ef280f4
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge git://git.denx.de/u-boot-arc

Showing 24 changed files Side-by-side Diff

... ... @@ -139,7 +139,7 @@
139 139 new boards should not use this option.
140 140  
141 141 config SYS_TEXT_BASE
142   - depends on SPARC
  142 + depends on SPARC || ARC
143 143 hex "Text Base"
144 144 help
145 145 TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
... ... @@ -4,6 +4,7 @@
4 4  
5 5 config ARC
6 6 bool "ARC architecture"
  7 + select HAVE_PRIVATE_LIBGCC
7 8  
8 9 config ARM
9 10 bool "ARM architecture"
... ... @@ -4,10 +4,78 @@
4 4 config SYS_ARCH
5 5 default "arc"
6 6  
  7 +config USE_PRIVATE_LIBGCC
  8 + default y
  9 +
7 10 config SYS_CPU
8 11 default "arcv1"
9 12  
10 13 choice
  14 + prompt "CPU selection"
  15 + default CPU_ARC770D
  16 +
  17 +config CPU_ARC750D
  18 + bool "ARC 750D"
  19 + select ARC_MMU_V2
  20 + help
  21 + Choose this option to build an U-Boot for ARC750D CPU.
  22 +
  23 +config CPU_ARC770D
  24 + bool "ARC 770D"
  25 + select ARC_MMU_V3
  26 + help
  27 + Choose this option to build an U-Boot for ARC770D CPU.
  28 +
  29 +endchoice
  30 +
  31 +choice
  32 + prompt "MMU Version"
  33 + default ARC_MMU_V3 if CPU_ARC770D
  34 + default ARC_MMU_V2 if CPU_ARC750D
  35 +
  36 +config ARC_MMU_V2
  37 + bool "MMU v2"
  38 + depends on CPU_ARC750D
  39 + help
  40 + Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
  41 + when 2 D-TLB and 1 I-TLB entries index into same 2way set.
  42 +
  43 +config ARC_MMU_V3
  44 + bool "MMU v3"
  45 + depends on CPU_ARC770D
  46 + help
  47 + Introduced with ARC700 4.10: New Features
  48 + Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
  49 + Shared Address Spaces (SASID)
  50 +
  51 +endchoice
  52 +
  53 +config CPU_BIG_ENDIAN
  54 + bool "Enable Big Endian Mode"
  55 + default n
  56 + help
  57 + Build kernel for Big Endian Mode of ARC CPU
  58 +
  59 +config SYS_ICACHE_OFF
  60 + bool "Do not use Instruction Cache"
  61 + default n
  62 +
  63 +config SYS_DCACHE_OFF
  64 + bool "Do not use Data Cache"
  65 + default n
  66 +
  67 +config ARC_CACHE_LINE_SHIFT
  68 + int "Cache Line Length (as power of 2)"
  69 + range 5 7
  70 + default "6"
  71 + depends on !SYS_DCACHE_OFF || !SYS_DCACHE_OFF
  72 + help
  73 + Starting with ARC700 4.9, Cache line length is configurable,
  74 + This option specifies "N", with Line-len = 2 power N
  75 + So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
  76 + Linux only supports same line lengths for I and D caches.
  77 +
  78 +choice
11 79 prompt "Target select"
12 80  
13 81 config TARGET_TB100
... ... @@ -15,9 +83,6 @@
15 83  
16 84 config TARGET_ARCANGEL4
17 85 bool "Support arcangel4"
18   -
19   -config TARGET_ARCANGEL4_BE
20   - bool "Support arcangel4-be"
21 86  
22 87 config TARGET_AXS101
23 88 bool "Support axs101"
... ... @@ -4,17 +4,22 @@
4 4 # SPDX-License-Identifier: GPL-2.0+
5 5 #
6 6  
7   -ifndef CONFIG_SYS_BIG_ENDIAN
  7 +ifndef CONFIG_CPU_BIG_ENDIAN
8 8 CONFIG_SYS_LITTLE_ENDIAN = 1
  9 +else
  10 +CONFIG_SYS_BIG_ENDIAN = 1
9 11 endif
10 12  
11 13 ifdef CONFIG_SYS_LITTLE_ENDIAN
12 14 ARC_CROSS_COMPILE := arc-buildroot-linux-uclibc-
  15 +PLATFORM_LDFLAGS += -EL
  16 +PLATFORM_CPPFLAGS += -mlittle-endian
13 17 endif
14 18  
15 19 ifdef CONFIG_SYS_BIG_ENDIAN
16 20 ARC_CROSS_COMPILE := arceb-buildroot-linux-uclibc-
17 21 PLATFORM_LDFLAGS += -EB
  22 +PLATFORM_CPPFLAGS += -mbig-endian
18 23 endif
19 24  
20 25 ifeq ($(CROSS_COMPILE),)
... ... @@ -23,6 +28,14 @@
23 28  
24 29 ifdef CONFIG_ARC_MMU_VER
25 30 CONFIG_MMU = 1
  31 +endif
  32 +
  33 +ifdef CONFIG_CPU_ARC750D
  34 +PLATFORM_CPPFLAGS += -marc700
  35 +endif
  36 +
  37 +ifdef CONFIG_CPU_ARC770D
  38 +PLATFORM_CPPFLAGS += -marc700 -mlock -mswape
26 39 endif
27 40  
28 41 PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
arch/arc/cpu/arcv1/config.mk
View file @ 10918c0
1   -#
2   -# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3   -#
4   -# SPDX-License-Identifier: GPL-2.0+
5   -#
6   -
7   -PLATFORM_CPPFLAGS += -mA7
arch/arc/include/asm/arcregs.h
Diff comments   View file @ 10918c0
... ... @@ -7,6 +7,8 @@
7 7 #ifndef _ASM_ARC_ARCREGS_H
8 8 #define _ASM_ARC_ARCREGS_H
9 9  
  10 +#include <asm/cache.h>
  11 +
10 12 /*
11 13 * ARC architecture has additional address space - auxiliary registers.
12 14 * These registers are mostly used for configuration purposes.
... ... @@ -21,7 +23,7 @@
21 23 #define ARC_AUX_IC_IVIC 0x10
22 24 #define ARC_AUX_IC_CTRL 0x11
23 25 #define ARC_AUX_IC_IVIL 0x19
24   -#if (CONFIG_ARC_MMU_VER > 2)
  26 +#if (CONFIG_ARC_MMU_VER == 3)
25 27 #define ARC_AUX_IC_PTAG 0x1E
26 28 #endif
27 29 #define ARC_BCR_IC_BUILD 0x77
... ... @@ -40,7 +42,7 @@
40 42 #define ARC_AUX_DC_IVDL 0x4A
41 43 #define ARC_AUX_DC_FLSH 0x4B
42 44 #define ARC_AUX_DC_FLDL 0x4C
43   -#if (CONFIG_ARC_MMU_VER > 2)
  45 +#if (CONFIG_ARC_MMU_VER == 3)
44 46 #define ARC_AUX_DC_PTAG 0x5C
45 47 #endif
46 48 #define ARC_BCR_DC_BUILD 0x72
arch/arc/include/asm/cache.h
Diff comments   View file @ 10918c0
... ... @@ -9,15 +9,18 @@
9 9  
10 10 #include <config.h>
11 11  
12   -/*
13   - * The current upper bound for ARC L1 data cache line sizes is 128 bytes.
14   - * We use that value for aligning DMA buffers unless the board config has
15   - * specified an alternate cache line size.
16   - */
17   -#ifdef CONFIG_SYS_CACHELINE_SIZE
18   -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  12 +#ifdef CONFIG_ARC_CACHE_LINE_SHIFT
  13 +#define CONFIG_SYS_CACHELINE_SIZE (1 << CONFIG_ARC_CACHE_LINE_SHIFT)
  14 +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
19 15 #else
20   -#define ARCH_DMA_MINALIGN 128
  16 +/* Satisfy users of ARCH_DMA_MINALIGN */
  17 +#define ARCH_DMA_MINALIGN 128
  18 +#endif
  19 +
  20 +#if defined(CONFIG_ARC_MMU_V2)
  21 +#define CONFIG_ARC_MMU_VER 2
  22 +#elif defined(CONFIG_ARC_MMU_V3)
  23 +#define CONFIG_ARC_MMU_VER 3
21 24 #endif
22 25  
23 26 #endif /* __ASM_ARC_CACHE_H */
arch/arc/include/asm/config.h
Diff comments   View file @ 10918c0
... ... @@ -7,8 +7,10 @@
7 7 #ifndef __ASM_ARC_CONFIG_H_
8 8 #define __ASM_ARC_CONFIG_H_
9 9  
  10 +#define CONFIG_SYS_GENERIC_BOARD
10 11 #define CONFIG_SYS_GENERIC_GLOBAL_DATA
11 12 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
  13 +#define CONFIG_ARCH_EARLY_INIT_R
12 14  
13 15 #define CONFIG_LMB
14 16  
arch/arc/lib/Makefile
Diff comments   View file @ 10918c0
... ... @@ -20,4 +20,6 @@
20 20 obj-y += timer.o
21 21  
22 22 obj-$(CONFIG_CMD_BOOTM) += bootm.o
  23 +
  24 +lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _millicodethunk.o libgcc2.o
arch/arc/lib/_millicodethunk.S
Diff comments   View file @ 10918c0
  1 +/*
  2 + * Copyright (C) 1995, 1997, 2007-2013 Free Software Foundation, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 + /* ANSI concatenation macros. */
  8 +
  9 + #define CONCAT1(a, b) CONCAT2(a, b)
  10 + #define CONCAT2(a, b) a ## b
  11 +
  12 + /* Use the right prefix for global labels. */
  13 +
  14 + #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
  15 +
  16 +#ifndef WORKING_ASSEMBLER
  17 +#define abs_l abs
  18 +#define asl_l asl
  19 +#define mov_l mov
  20 +#endif
  21 +
  22 +#define FUNC(X) .type SYM(X),@function
  23 +#define HIDDEN_FUNC(X) FUNC(X)` .hidden X
  24 +#define ENDFUNC0(X) .Lfe_##X: .size X,.Lfe_##X-X
  25 +#define ENDFUNC(X) ENDFUNC0(X)
  26 +
  27 + .section .text
  28 + .align 4
  29 + .global SYM(__st_r13_to_r15)
  30 + .global SYM(__st_r13_to_r16)
  31 + .global SYM(__st_r13_to_r17)
  32 + .global SYM(__st_r13_to_r18)
  33 + .global SYM(__st_r13_to_r19)
  34 + .global SYM(__st_r13_to_r20)
  35 + .global SYM(__st_r13_to_r21)
  36 + .global SYM(__st_r13_to_r22)
  37 + .global SYM(__st_r13_to_r23)
  38 + .global SYM(__st_r13_to_r24)
  39 + .global SYM(__st_r13_to_r25)
  40 + HIDDEN_FUNC(__st_r13_to_r15)
  41 + HIDDEN_FUNC(__st_r13_to_r16)
  42 + HIDDEN_FUNC(__st_r13_to_r17)
  43 + HIDDEN_FUNC(__st_r13_to_r18)
  44 + HIDDEN_FUNC(__st_r13_to_r19)
  45 + HIDDEN_FUNC(__st_r13_to_r20)
  46 + HIDDEN_FUNC(__st_r13_to_r21)
  47 + HIDDEN_FUNC(__st_r13_to_r22)
  48 + HIDDEN_FUNC(__st_r13_to_r23)
  49 + HIDDEN_FUNC(__st_r13_to_r24)
  50 + HIDDEN_FUNC(__st_r13_to_r25)
  51 + .align 4
  52 +SYM(__st_r13_to_r25):
  53 + st r25, [sp,48]
  54 +SYM(__st_r13_to_r24):
  55 + st r24, [sp,44]
  56 +SYM(__st_r13_to_r23):
  57 + st r23, [sp,40]
  58 +SYM(__st_r13_to_r22):
  59 + st r22, [sp,36]
  60 +SYM(__st_r13_to_r21):
  61 + st r21, [sp,32]
  62 +SYM(__st_r13_to_r20):
  63 + st r20, [sp,28]
  64 +SYM(__st_r13_to_r19):
  65 + st r19, [sp,24]
  66 +SYM(__st_r13_to_r18):
  67 + st r18, [sp,20]
  68 +SYM(__st_r13_to_r17):
  69 + st r17, [sp,16]
  70 +SYM(__st_r13_to_r16):
  71 + st r16, [sp,12]
  72 +SYM(__st_r13_to_r15):
  73 +#ifdef __ARC700__
  74 + st r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
  75 +#else
  76 + st_s r15, [sp,8]
  77 +#endif
  78 + st_s r14, [sp,4]
  79 + j_s.d [%blink]
  80 + st_s r13, [sp,0]
  81 + ENDFUNC(__st_r13_to_r15)
  82 + ENDFUNC(__st_r13_to_r16)
  83 + ENDFUNC(__st_r13_to_r17)
  84 + ENDFUNC(__st_r13_to_r18)
  85 + ENDFUNC(__st_r13_to_r19)
  86 + ENDFUNC(__st_r13_to_r20)
  87 + ENDFUNC(__st_r13_to_r21)
  88 + ENDFUNC(__st_r13_to_r22)
  89 + ENDFUNC(__st_r13_to_r23)
  90 + ENDFUNC(__st_r13_to_r24)
  91 + ENDFUNC(__st_r13_to_r25)
  92 +
  93 + .section .text
  94 + .align 4
  95 +; ==================================
  96 +; the loads
  97 +
  98 + .global SYM(__ld_r13_to_r15)
  99 + .global SYM(__ld_r13_to_r16)
  100 + .global SYM(__ld_r13_to_r17)
  101 + .global SYM(__ld_r13_to_r18)
  102 + .global SYM(__ld_r13_to_r19)
  103 + .global SYM(__ld_r13_to_r20)
  104 + .global SYM(__ld_r13_to_r21)
  105 + .global SYM(__ld_r13_to_r22)
  106 + .global SYM(__ld_r13_to_r23)
  107 + .global SYM(__ld_r13_to_r24)
  108 + .global SYM(__ld_r13_to_r25)
  109 + HIDDEN_FUNC(__ld_r13_to_r15)
  110 + HIDDEN_FUNC(__ld_r13_to_r16)
  111 + HIDDEN_FUNC(__ld_r13_to_r17)
  112 + HIDDEN_FUNC(__ld_r13_to_r18)
  113 + HIDDEN_FUNC(__ld_r13_to_r19)
  114 + HIDDEN_FUNC(__ld_r13_to_r20)
  115 + HIDDEN_FUNC(__ld_r13_to_r21)
  116 + HIDDEN_FUNC(__ld_r13_to_r22)
  117 + HIDDEN_FUNC(__ld_r13_to_r23)
  118 + HIDDEN_FUNC(__ld_r13_to_r24)
  119 + HIDDEN_FUNC(__ld_r13_to_r25)
  120 +SYM(__ld_r13_to_r25):
  121 + ld r25, [sp,48]
  122 +SYM(__ld_r13_to_r24):
  123 + ld r24, [sp,44]
  124 +SYM(__ld_r13_to_r23):
  125 + ld r23, [sp,40]
  126 +SYM(__ld_r13_to_r22):
  127 + ld r22, [sp,36]
  128 +SYM(__ld_r13_to_r21):
  129 + ld r21, [sp,32]
  130 +SYM(__ld_r13_to_r20):
  131 + ld r20, [sp,28]
  132 +SYM(__ld_r13_to_r19):
  133 + ld r19, [sp,24]
  134 +SYM(__ld_r13_to_r18):
  135 + ld r18, [sp,20]
  136 +SYM(__ld_r13_to_r17):
  137 + ld r17, [sp,16]
  138 +SYM(__ld_r13_to_r16):
  139 + ld r16, [sp,12]
  140 +SYM(__ld_r13_to_r15):
  141 +#ifdef __ARC700__
  142 + ld r15, [sp,8] ; minimum function size to avoid stall: 6 bytes.
  143 +#else
  144 + ld_s r15, [sp,8]
  145 +#endif
  146 + ld_s r14, [sp,4]
  147 + j_s.d [%blink]
  148 + ld_s r13, [sp,0]
  149 + ENDFUNC(__ld_r13_to_r15)
  150 + ENDFUNC(__ld_r13_to_r16)
  151 + ENDFUNC(__ld_r13_to_r17)
  152 + ENDFUNC(__ld_r13_to_r18)
  153 + ENDFUNC(__ld_r13_to_r19)
  154 + ENDFUNC(__ld_r13_to_r20)
  155 + ENDFUNC(__ld_r13_to_r21)
  156 + ENDFUNC(__ld_r13_to_r22)
  157 + ENDFUNC(__ld_r13_to_r23)
  158 + ENDFUNC(__ld_r13_to_r24)
  159 + ENDFUNC(__ld_r13_to_r25)
  160 +
  161 + .global SYM(__ld_r13_to_r14_ret)
  162 + .global SYM(__ld_r13_to_r15_ret)
  163 + .global SYM(__ld_r13_to_r16_ret)
  164 + .global SYM(__ld_r13_to_r17_ret)
  165 + .global SYM(__ld_r13_to_r18_ret)
  166 + .global SYM(__ld_r13_to_r19_ret)
  167 + .global SYM(__ld_r13_to_r20_ret)
  168 + .global SYM(__ld_r13_to_r21_ret)
  169 + .global SYM(__ld_r13_to_r22_ret)
  170 + .global SYM(__ld_r13_to_r23_ret)
  171 + .global SYM(__ld_r13_to_r24_ret)
  172 + .global SYM(__ld_r13_to_r25_ret)
  173 + HIDDEN_FUNC(__ld_r13_to_r14_ret)
  174 + HIDDEN_FUNC(__ld_r13_to_r15_ret)
  175 + HIDDEN_FUNC(__ld_r13_to_r16_ret)
  176 + HIDDEN_FUNC(__ld_r13_to_r17_ret)
  177 + HIDDEN_FUNC(__ld_r13_to_r18_ret)
  178 + HIDDEN_FUNC(__ld_r13_to_r19_ret)
  179 + HIDDEN_FUNC(__ld_r13_to_r20_ret)
  180 + HIDDEN_FUNC(__ld_r13_to_r21_ret)
  181 + HIDDEN_FUNC(__ld_r13_to_r22_ret)
  182 + HIDDEN_FUNC(__ld_r13_to_r23_ret)
  183 + HIDDEN_FUNC(__ld_r13_to_r24_ret)
  184 + HIDDEN_FUNC(__ld_r13_to_r25_ret)
  185 + .section .text
  186 + .align 4
  187 +SYM(__ld_r13_to_r25_ret):
  188 + ld r25, [sp,48]
  189 +SYM(__ld_r13_to_r24_ret):
  190 + ld r24, [sp,44]
  191 +SYM(__ld_r13_to_r23_ret):
  192 + ld r23, [sp,40]
  193 +SYM(__ld_r13_to_r22_ret):
  194 + ld r22, [sp,36]
  195 +SYM(__ld_r13_to_r21_ret):
  196 + ld r21, [sp,32]
  197 +SYM(__ld_r13_to_r20_ret):
  198 + ld r20, [sp,28]
  199 +SYM(__ld_r13_to_r19_ret):
  200 + ld r19, [sp,24]
  201 +SYM(__ld_r13_to_r18_ret):
  202 + ld r18, [sp,20]
  203 +SYM(__ld_r13_to_r17_ret):
  204 + ld r17, [sp,16]
  205 +SYM(__ld_r13_to_r16_ret):
  206 + ld r16, [sp,12]
  207 +SYM(__ld_r13_to_r15_ret):
  208 + ld r15, [sp,8]
  209 +SYM(__ld_r13_to_r14_ret):
  210 + ld blink,[sp,r12]
  211 + ld_s r14, [sp,4]
  212 + ld.ab r13, [sp,r12]
  213 + j_s.d [%blink]
  214 + add_s sp,sp,4
  215 + ENDFUNC(__ld_r13_to_r14_ret)
  216 + ENDFUNC(__ld_r13_to_r15_ret)
  217 + ENDFUNC(__ld_r13_to_r16_ret)
  218 + ENDFUNC(__ld_r13_to_r17_ret)
  219 + ENDFUNC(__ld_r13_to_r18_ret)
  220 + ENDFUNC(__ld_r13_to_r19_ret)
  221 + ENDFUNC(__ld_r13_to_r20_ret)
  222 + ENDFUNC(__ld_r13_to_r21_ret)
  223 + ENDFUNC(__ld_r13_to_r22_ret)
  224 + ENDFUNC(__ld_r13_to_r23_ret)
  225 + ENDFUNC(__ld_r13_to_r24_ret)
  226 + ENDFUNC(__ld_r13_to_r25_ret)
arch/arc/lib/cache.c
Diff comments   View file @ 10918c0
... ... @@ -6,6 +6,7 @@
6 6  
7 7 #include <config.h>
8 8 #include <asm/arcregs.h>
  9 +#include <asm/cache.h>
9 10  
10 11 /* Bit values in IC_CTRL */
11 12 #define IC_CTRL_CACHE_DISABLE (1 << 0)
... ... @@ -101,7 +102,7 @@
101 102 #ifndef CONFIG_SYS_DCACHE_OFF
102 103 static void dcache_flush_line(unsigned addr)
103 104 {
104   -#if (CONFIG_ARC_MMU_VER > 2)
  105 +#if (CONFIG_ARC_MMU_VER == 3)
105 106 write_aux_reg(ARC_AUX_DC_PTAG, addr);
106 107 #endif
107 108 write_aux_reg(ARC_AUX_DC_FLDL, addr);
... ... @@ -115,7 +116,7 @@
115 116 * Invalidate I$ for addresses range just flushed from D$.
116 117 * If we try to execute data flushed above it will be valid/correct
117 118 */
118   -#if (CONFIG_ARC_MMU_VER > 2)
  119 +#if (CONFIG_ARC_MMU_VER == 3)
119 120 write_aux_reg(ARC_AUX_IC_PTAG, addr);
120 121 #endif
121 122 write_aux_reg(ARC_AUX_IC_IVIL, addr);
... ... @@ -145,7 +146,7 @@
145 146 end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
146 147  
147 148 for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
148   -#if (CONFIG_ARC_MMU_VER > 2)
  149 +#if (CONFIG_ARC_MMU_VER == 3)
149 150 write_aux_reg(ARC_AUX_DC_PTAG, addr);
150 151 #endif
151 152 write_aux_reg(ARC_AUX_DC_IVDL, addr);
arch/arc/lib/libgcc2.c
Diff comments   View file @ 10918c0
  1 +/*
  2 + * Copyright (C) 1989-2013 Free Software Foundation, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include "libgcc2.h"
  8 +
  9 +DWtype
  10 +__ashldi3(DWtype u, shift_count_type b)
  11 +{
  12 + if (b == 0)
  13 + return u;
  14 +
  15 + const DWunion uu = {.ll = u};
  16 + const shift_count_type bm = W_TYPE_SIZE - b;
  17 + DWunion w;
  18 +
  19 + if (bm <= 0) {
  20 + w.s.low = 0;
  21 + w.s.high = (UWtype)uu.s.low << -bm;
  22 + } else {
  23 + const UWtype carries = (UWtype) uu.s.low >> bm;
  24 +
  25 + w.s.low = (UWtype)uu.s.low << b;
  26 + w.s.high = ((UWtype)uu.s.high << b) | carries;
  27 + }
  28 +
  29 + return w.ll;
  30 +}
  31 +
  32 +DWtype
  33 +__ashrdi3(DWtype u, shift_count_type b)
  34 +{
  35 + if (b == 0)
  36 + return u;
  37 +
  38 + const DWunion uu = {.ll = u};
  39 + const shift_count_type bm = W_TYPE_SIZE - b;
  40 + DWunion w;
  41 +
  42 + if (bm <= 0) {
  43 + /* w.s.high = 1..1 or 0..0 */
  44 + w.s.high = uu.s.high >> (W_TYPE_SIZE - 1);
  45 + w.s.low = uu.s.high >> -bm;
  46 + } else {
  47 + const UWtype carries = (UWtype) uu.s.high << bm;
  48 +
  49 + w.s.high = uu.s.high >> b;
  50 + w.s.low = ((UWtype)uu.s.low >> b) | carries;
  51 + }
  52 +
  53 + return w.ll;
  54 +}
  55 +
  56 +DWtype
  57 +__lshrdi3(DWtype u, shift_count_type b)
  58 +{
  59 + if (b == 0)
  60 + return u;
  61 +
  62 + const DWunion uu = {.ll = u};
  63 + const shift_count_type bm = W_TYPE_SIZE - b;
  64 + DWunion w;
  65 +
  66 + if (bm <= 0) {
  67 + w.s.high = 0;
  68 + w.s.low = (UWtype)uu.s.high >> -bm;
  69 + } else {
  70 + const UWtype carries = (UWtype)uu.s.high << bm;
  71 +
  72 + w.s.high = (UWtype)uu.s.high >> b;
  73 + w.s.low = ((UWtype)uu.s.low >> b) | carries;
  74 + }
  75 +
  76 + return w.ll;
  77 +}
  78 +
  79 +unsigned long
  80 +udivmodsi4(unsigned long num, unsigned long den, int modwanted)
  81 +{
  82 + unsigned long bit = 1;
  83 + unsigned long res = 0;
  84 +
  85 + while (den < num && bit && !(den & (1L<<31))) {
  86 + den <<= 1;
  87 + bit <<= 1;
  88 + }
  89 +
  90 + while (bit) {
  91 + if (num >= den) {
  92 + num -= den;
  93 + res |= bit;
  94 + }
  95 + bit >>= 1;
  96 + den >>= 1;
  97 + }
  98 +
  99 + if (modwanted)
  100 + return num;
  101 +
  102 + return res;
  103 +}
  104 +
  105 +long
  106 +__divsi3(long a, long b)
  107 +{
  108 + int neg = 0;
  109 + long res;
  110 +
  111 + if (a < 0) {
  112 + a = -a;
  113 + neg = !neg;
  114 + }
  115 +
  116 + if (b < 0) {
  117 + b = -b;
  118 + neg = !neg;
  119 + }
  120 +
  121 + res = udivmodsi4(a, b, 0);
  122 +
  123 + if (neg)
  124 + res = -res;
  125 +
  126 + return res;
  127 +}
  128 +
  129 +long
  130 +__modsi3(long a, long b)
  131 +{
  132 + int neg = 0;
  133 + long res;
  134 +
  135 + if (a < 0) {
  136 + a = -a;
  137 + neg = 1;
  138 + }
  139 +
  140 + if (b < 0)
  141 + b = -b;
  142 +
  143 + res = udivmodsi4(a, b, 1);
  144 +
  145 + if (neg)
  146 + res = -res;
  147 +
  148 + return res;
  149 +}
  150 +
  151 +long
  152 +__udivsi3(long a, long b)
  153 +{
  154 + return udivmodsi4(a, b, 0);
  155 +}
  156 +
  157 +long
  158 +__umodsi3(long a, long b)
  159 +{
  160 + return udivmodsi4(a, b, 1);
  161 +}
arch/arc/lib/libgcc2.h
Diff comments   View file @ 10918c0
  1 +/*
  2 + * Copyright (C) 1989-2013 Free Software Foundation, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __ASM_LIBGCC_H
  8 +#define __ASM_LIBGCC_H
  9 +
  10 +#define UNITS_PER_WORD 4 /* for ARC */
  11 +#define BITS_PER_UNIT 8 /* for ARC */
  12 +
  13 +#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
  14 +
  15 +#define MIN_UNITS_PER_WORD UNITS_PER_WORD
  16 +
  17 +/* Work out the largest "word" size that we can deal with on this target. */
  18 +#if MIN_UNITS_PER_WORD > 4
  19 +# define LIBGCC2_MAX_UNITS_PER_WORD 8
  20 +#elif (MIN_UNITS_PER_WORD > 2 \
  21 + || (MIN_UNITS_PER_WORD > 1 && __SIZEOF_LONG_LONG__ > 4))
  22 +# define LIBGCC2_MAX_UNITS_PER_WORD 4
  23 +#else
  24 +# define LIBGCC2_MAX_UNITS_PER_WORD MIN_UNITS_PER_WORD
  25 +#endif
  26 +
  27 +/* Work out what word size we are using for this compilation.
  28 + The value can be set on the command line. */
  29 +#ifndef LIBGCC2_UNITS_PER_WORD
  30 +#define LIBGCC2_UNITS_PER_WORD LIBGCC2_MAX_UNITS_PER_WORD
  31 +#endif
  32 +
  33 +typedef int QItype __attribute__ ((mode (QI)));
  34 +typedef unsigned int UQItype __attribute__ ((mode (QI)));
  35 +typedef int HItype __attribute__ ((mode (HI)));
  36 +typedef unsigned int UHItype __attribute__ ((mode (HI)));
  37 +#if MIN_UNITS_PER_WORD > 1
  38 +/* These typedefs are usually forbidden on dsp's with UNITS_PER_WORD 1. */
  39 +typedef int SItype __attribute__ ((mode (SI)));
  40 +typedef unsigned int USItype __attribute__ ((mode (SI)));
  41 +#if __SIZEOF_LONG_LONG__ > 4
  42 +/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 2. */
  43 +typedef int DItype __attribute__ ((mode (DI)));
  44 +typedef unsigned int UDItype __attribute__ ((mode (DI)));
  45 +#if MIN_UNITS_PER_WORD > 4
  46 +/* These typedefs are usually forbidden on archs with UNITS_PER_WORD 4. */
  47 +typedef int TItype __attribute__ ((mode (TI)));
  48 +typedef unsigned int UTItype __attribute__ ((mode (TI)));
  49 +#endif
  50 +#endif
  51 +#endif
  52 +
  53 +#if LIBGCC2_UNITS_PER_WORD == 8
  54 +#define W_TYPE_SIZE (8 * BITS_PER_UNIT)
  55 +#define Wtype DItype
  56 +#define UWtype UDItype
  57 +#define HWtype DItype
  58 +#define UHWtype UDItype
  59 +#define DWtype TItype
  60 +#define UDWtype UTItype
  61 +#ifdef LIBGCC2_GNU_PREFIX
  62 +#define __NW(a,b) __gnu_ ## a ## di ## b
  63 +#define __NDW(a,b) __gnu_ ## a ## ti ## b
  64 +#else
  65 +#define __NW(a,b) __ ## a ## di ## b
  66 +#define __NDW(a,b) __ ## a ## ti ## b
  67 +#endif
  68 +#elif LIBGCC2_UNITS_PER_WORD == 4
  69 +#define W_TYPE_SIZE (4 * BITS_PER_UNIT)
  70 +#define Wtype SItype
  71 +#define UWtype USItype
  72 +#define HWtype SItype
  73 +#define UHWtype USItype
  74 +#define DWtype DItype
  75 +#define UDWtype UDItype
  76 +#ifdef LIBGCC2_GNU_PREFIX
  77 +#define __NW(a,b) __gnu_ ## a ## si ## b
  78 +#define __NDW(a,b) __gnu_ ## a ## di ## b
  79 +#else
  80 +#define __NW(a,b) __ ## a ## si ## b
  81 +#define __NDW(a,b) __ ## a ## di ## b
  82 +#endif
  83 +#elif LIBGCC2_UNITS_PER_WORD == 2
  84 +#define W_TYPE_SIZE (2 * BITS_PER_UNIT)
  85 +#define Wtype HItype
  86 +#define UWtype UHItype
  87 +#define HWtype HItype
  88 +#define UHWtype UHItype
  89 +#define DWtype SItype
  90 +#define UDWtype USItype
  91 +#ifdef LIBGCC2_GNU_PREFIX
  92 +#define __NW(a,b) __gnu_ ## a ## hi ## b
  93 +#define __NDW(a,b) __gnu_ ## a ## si ## b
  94 +#else
  95 +#define __NW(a,b) __ ## a ## hi ## b
  96 +#define __NDW(a,b) __ ## a ## si ## b
  97 +#endif
  98 +#else
  99 +#define W_TYPE_SIZE BITS_PER_UNIT
  100 +#define Wtype QItype
  101 +#define UWtype UQItype
  102 +#define HWtype QItype
  103 +#define UHWtype UQItype
  104 +#define DWtype HItype
  105 +#define UDWtype UHItype
  106 +#ifdef LIBGCC2_GNU_PREFIX
  107 +#define __NW(a,b) __gnu_ ## a ## qi ## b
  108 +#define __NDW(a,b) __gnu_ ## a ## hi ## b
  109 +#else
  110 +#define __NW(a,b) __ ## a ## qi ## b
  111 +#define __NDW(a,b) __ ## a ## hi ## b
  112 +#endif
  113 +#endif
  114 +
  115 +typedef int shift_count_type __attribute__((mode (__libgcc_shift_count__)));
  116 +
  117 +#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
  118 + struct DWstruct {Wtype high, low;};
  119 +#else
  120 + struct DWstruct {Wtype low, high;};
  121 +#endif
  122 +
  123 +/* We need this union to unpack/pack DImode values, since we don't have
  124 + any arithmetic yet. Incoming DImode parameters are stored into the
  125 + `ll' field, and the unpacked result is read from the struct `s'. */
  126 +
  127 +typedef union {
  128 + struct DWstruct s;
  129 + DWtype ll;
  130 +} DWunion;
  131 +
  132 +#endif /* __ASM_LIBGCC_H */
arch/arc/lib/memcmp.S
Diff comments   View file @ 10918c0
... ... @@ -29,6 +29,7 @@
29 29 ld.a %r4, [%r0, 8]
30 30 ld.a %r5, [%r1, 8]
31 31 brne WORD2, %r12, .Lodd
  32 + nop
32 33 .Loop_end:
33 34 asl_s SHIFT, SHIFT, 3
34 35 bhs_s .Last_cmp
... ... @@ -105,6 +106,7 @@
105 106 ldb.a %r4, [%r0, 2]
106 107 ldb.a %r5, [%r1, 2]
107 108 brne %r3, %r12, .Lbyte_odd
  109 + nop
108 110 .Lbyte_end:
109 111 bcc .Lbyte_even
110 112 brne %r4, %r5, .Lbyte_even
board/synopsys/Kconfig
Diff comments   View file @ 10918c0
... ... @@ -7,14 +7,4 @@
7 7 default "arcangel4"
8 8  
9 9 endif
10   -
11   -if TARGET_ARCANGEL4_BE
12   -
13   -config SYS_VENDOR
14   - default "synopsys"
15   -
16   -config SYS_CONFIG_NAME
17   - default "arcangel4-be"
18   -
19   -endif
board/synopsys/MAINTAINERS
Diff comments   View file @ 10918c0
... ... @@ -3,6 +3,5 @@
3 3 S: Maintained
4 4 F: include/configs/arcangel4.h
5 5 F: configs/arcangel4_defconfig
6   -F: include/configs/arcangel4-be.h
7 6 F: configs/arcangel4-be_defconfig
configs/arcangel4-be_defconfig
Diff comments   View file @ 10918c0
1 1 CONFIG_ARC=y
2   -CONFIG_TARGET_ARCANGEL4_BE=y
  2 +CONFIG_TARGET_ARCANGEL4=y
3 3 CONFIG_SYS_CLK_FREQ=70000000
  4 +CONFIG_CPU_BIG_ENDIAN=y
  5 +CONFIG_SYS_TEXT_BASE=0x81000000
configs/arcangel4_defconfig
Diff comments   View file @ 10918c0
1 1 CONFIG_ARC=y
2 2 CONFIG_TARGET_ARCANGEL4=y
3 3 CONFIG_SYS_CLK_FREQ=70000000
  4 +CONFIG_SYS_TEXT_BASE=0x81000000
configs/axs101_defconfig
Diff comments   View file @ 10918c0
1 1 CONFIG_ARC=y
2 2 CONFIG_TARGET_AXS101=y
3 3 CONFIG_SYS_CLK_FREQ=750000000
  4 +CONFIG_ARC_CACHE_LINE_SHIFT=5
  5 +CONFIG_SYS_DCACHE_OFF=y
  6 +CONFIG_SYS_TEXT_BASE=0x81000000
configs/tb100_defconfig
Diff comments   View file @ 10918c0
1 1 CONFIG_ARC=y
2 2 CONFIG_TARGET_TB100=y
3 3 CONFIG_SYS_CLK_FREQ=500000000
  4 +CONFIG_ARC_CACHE_LINE_SHIFT=5
  5 +CONFIG_SYS_TEXT_BASE=0x84000000
include/configs/arcangel4-be.h
View file @ 10918c0
1   -/*
2   - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#ifndef _CONFIG_ARCANGEL4_H_
8   -#define _CONFIG_ARCANGEL4_H_
9   -
10   -/*
11   - * CPU configuration
12   - */
13   -#define CONFIG_SYS_BIG_ENDIAN
14   -#define CONFIG_ARC700
15   -#define CONFIG_ARC_MMU_VER 3
16   -#define CONFIG_SYS_CACHELINE_SIZE 64
17   -#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
18   -
19   -/*
20   - * Board configuration
21   - */
22   -#define CONFIG_SYS_GENERIC_BOARD
23   -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
24   -
25   -#define CONFIG_ARCH_EARLY_INIT_R
26   -
27   -/*
28   - * Memory configuration
29   - */
30   -#define CONFIG_SYS_TEXT_BASE 0x81000000
31   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
32   -
33   -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
34   -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
35   -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
36   -
37   -#define CONFIG_SYS_INIT_SP_ADDR \
38   - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
39   -
40   -#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
41   -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
42   -#define CONFIG_SYS_LOAD_ADDR 0x82000000
43   -
44   -#define CONFIG_SYS_NO_FLASH
45   -
46   -/*
47   - * UART configuration
48   - *
49   - */
50   -#define CONFIG_ARC_SERIAL
51   -#define CONFIG_ARC_UART_BASE 0xC0FC1000
52   -#define CONFIG_BAUDRATE 115200
53   -
54   -/*
55   - * Command line configuration
56   - */
57   -#include <config_cmd_default.h>
58   -
59   -#define CONFIG_CMD_ELF
60   -
61   -#define CONFIG_OF_LIBFDT
62   -
63   -#define CONFIG_AUTO_COMPLETE
64   -#define CONFIG_SYS_MAXARGS 16
65   -
66   -/*
67   - * Environment settings
68   - */
69   -#define CONFIG_ENV_IS_NOWHERE
70   -#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
71   -#define CONFIG_ENV_OFFSET 0
72   -
73   -/*
74   - * Environment configuration
75   - */
76   -#define CONFIG_BOOTDELAY 3
77   -#define CONFIG_BOOTFILE "uImage"
78   -#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
79   -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
80   -
81   -/*
82   - * Console configuration
83   - */
84   -#define CONFIG_SYS_LONGHELP
85   -#define CONFIG_SYS_PROMPT "arcangel4# "
86   -#define CONFIG_SYS_CBSIZE 256
87   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
88   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
89   - sizeof(CONFIG_SYS_PROMPT) + 16)
90   -
91   -#endif /* _CONFIG_ARCANGEL4_H_ */
include/configs/arcangel4.h
Diff comments   View file @ 10918c0
... ... @@ -10,23 +10,11 @@
10 10 /*
11 11 * CPU configuration
12 12 */
13   -#define CONFIG_ARC700
14   -#define CONFIG_ARC_MMU_VER 3
15   -#define CONFIG_SYS_CACHELINE_SIZE 64
16 13 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
17 14  
18 15 /*
19   - * Board configuration
20   - */
21   -#define CONFIG_SYS_GENERIC_BOARD
22   -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
23   -
24   -#define CONFIG_ARCH_EARLY_INIT_R
25   -
26   -/*
27 16 * Memory configuration
28 17 */
29   -#define CONFIG_SYS_TEXT_BASE 0x81000000
30 18 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
31 19  
32 20 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
include/configs/axs101.h
Diff comments   View file @ 10918c0
... ... @@ -10,22 +10,8 @@
10 10 /*
11 11 * CPU configuration
12 12 */
13   -#define CONFIG_ARC700
14   -#define CONFIG_ARC_MMU_VER 3
15   -#define CONFIG_SYS_CACHELINE_SIZE 32
16 13 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
17 14  
18   -/* NAND controller DMA doesn't work correctly with D$ enabled */
19   -#define CONFIG_SYS_DCACHE_OFF
20   -
21   -/*
22   - * Board configuration
23   - */
24   -#define CONFIG_SYS_GENERIC_BOARD
25   -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
26   -
27   -#define CONFIG_ARCH_EARLY_INIT_R
28   -
29 15 #define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
30 16 #define ARC_APB_PERIPHERAL_BASE 0xF0000000
31 17 #define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
... ... @@ -34,7 +20,6 @@
34 20 /*
35 21 * Memory configuration
36 22 */
37   -#define CONFIG_SYS_TEXT_BASE 0x81000000
38 23 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
39 24  
40 25 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
include/configs/tb100.h
Diff comments   View file @ 10918c0
... ... @@ -12,21 +12,11 @@
12 12 /*
13 13 * CPU configuration
14 14 */
15   -#define CONFIG_ARC700
16   -#define CONFIG_ARC_MMU_VER 3
17   -#define CONFIG_SYS_CACHELINE_SIZE 32
18 15 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
19 16  
20 17 /*
21   - * Board configuration
22   - */
23   -#define CONFIG_SYS_GENERIC_BOARD
24   -#define CONFIG_ARCH_EARLY_INIT_R
25   -
26   -/*
27 18 * Memory configuration
28 19 */
29   -#define CONFIG_SYS_TEXT_BASE 0x84000000
30 20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
31 21  
32 22 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000