Eric Lee / smarc-uboot

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Commit 11ea97fb3c67f71ba7d9cb05bf10a9035f1d3cc4

Authored by Ye Li
1 parent f3e87ac7e4
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-24192-2 DTS: imx8qm/qxp/dxl: Update PCIE clocks 

Update PCIE clocks to align with latest v5.4 kernel, otherwise we
may miss some LPCG clocks in u-boot and have potential problem if
they have been disabled in kernel during partition reboot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 76ebe2016c2ab7199cb6a6b83f8bc97fe0140549)

Showing 3 changed files with 22 additions and 12 deletions Inline Diff

arch/arm/dts/fsl-imx8dx.dtsi
Diff comments   View file @ 11ea97f
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi" 7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h> 8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_hsio.h> 9 #include <dt-bindings/soc/imx8_hsio.h>
10 #include <dt-bindings/soc/imx8_pd.h> 10 #include <dt-bindings/soc/imx8_pd.h>
11 #include <dt-bindings/clock/imx8qxp-clock.h> 11 #include <dt-bindings/clock/imx8qxp-clock.h>
12 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 model = "NXP i.MX8DX"; 18 model = "NXP i.MX8DX";
19 compatible = "fsl,imx8dx", "fsl,imx8qxp"; 19 compatible = "fsl,imx8dx", "fsl,imx8qxp";
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 aliases { 24 aliases {
25 csi0 = &mipi_csi_0; 25 csi0 = &mipi_csi_0;
26 video0 = &dpu1; 26 video0 = &dpu1;
27 ethernet0 = &fec1; 27 ethernet0 = &fec1;
28 ethernet1 = &fec2; 28 ethernet1 = &fec2;
29 dsiphy0 = &mipi_dsi_phy1; 29 dsiphy0 = &mipi_dsi_phy1;
30 dsiphy1 = &mipi_dsi_phy2; 30 dsiphy1 = &mipi_dsi_phy2;
31 mipidsi0 = &mipi_dsi1; 31 mipidsi0 = &mipi_dsi1;
32 mipidsi1 = &mipi_dsi2; 32 mipidsi1 = &mipi_dsi2;
33 display0 = &ldb1; 33 display0 = &ldb1;
34 display1 = &ldb2; 34 display1 = &ldb2;
35 isi0 = &isi_0; 35 isi0 = &isi_0;
36 isi1 = &isi_1; 36 isi1 = &isi_1;
37 isi2 = &isi_2; 37 isi2 = &isi_2;
38 isi3 = &isi_3; 38 isi3 = &isi_3;
39 isi4 = &isi_4; 39 isi4 = &isi_4;
40 isi5 = &isi_5; 40 isi5 = &isi_5;
41 isi6 = &isi_6; 41 isi6 = &isi_6;
42 isi7 = &isi_7; 42 isi7 = &isi_7;
43 serial0 = &lpuart0; 43 serial0 = &lpuart0;
44 serial1 = &lpuart1; 44 serial1 = &lpuart1;
45 serial2 = &lpuart2; 45 serial2 = &lpuart2;
46 serial3 = &lpuart3; 46 serial3 = &lpuart3;
47 gpio0 = &gpio0; 47 gpio0 = &gpio0;
48 gpio1 = &gpio1; 48 gpio1 = &gpio1;
49 gpio2 = &gpio2; 49 gpio2 = &gpio2;
50 gpio3 = &gpio3; 50 gpio3 = &gpio3;
51 gpio4 = &gpio4; 51 gpio4 = &gpio4;
52 gpio5 = &gpio5; 52 gpio5 = &gpio5;
53 gpio6 = &gpio6; 53 gpio6 = &gpio6;
54 gpio7 = &gpio7; 54 gpio7 = &gpio7;
55 mmc0 = &usdhc1; 55 mmc0 = &usdhc1;
56 mmc1 = &usdhc2; 56 mmc1 = &usdhc2;
57 mmc2 = &usdhc3; 57 mmc2 = &usdhc3;
58 can0 = &flexcan1; 58 can0 = &flexcan1;
59 can1 = &flexcan2; 59 can1 = &flexcan2;
60 can2 = &flexcan3; 60 can2 = &flexcan3;
61 i2c0 = &i2c0; 61 i2c0 = &i2c0;
62 i2c1 = &i2c1; 62 i2c1 = &i2c1;
63 i2c2 = &i2c2; 63 i2c2 = &i2c2;
64 i2c3 = &i2c3; 64 i2c3 = &i2c3;
65 i2c13 = &i2c0_mipi_lvds0; 65 i2c13 = &i2c0_mipi_lvds0;
66 i2c15 = &i2c0_mipi_lvds1; 66 i2c15 = &i2c0_mipi_lvds1;
67 spi0 = &flexspi0; 67 spi0 = &flexspi0;
68 usb0 = &usbotg1; 68 usb0 = &usbotg1;
69 usbphy0 = &usbphy1; 69 usbphy0 = &usbphy1;
70 usb1 = &usbotg3; 70 usb1 = &usbotg3;
71 pci0 = &pcieb; 71 pci0 = &pcieb;
72 }; 72 };
73 73
74 cpus { 74 cpus {
75 idle-states { 75 idle-states {
76 entry-method = "psci"; 76 entry-method = "psci";
77 77
78 CPU_SLEEP: cpu-sleep { 78 CPU_SLEEP: cpu-sleep {
79 compatible = "arm,idle-state"; 79 compatible = "arm,idle-state";
80 arm,psci-suspend-param = <0x10000>; 80 arm,psci-suspend-param = <0x10000>;
81 local-timer-stop; 81 local-timer-stop;
82 entry-latency-us = <500>; 82 entry-latency-us = <500>;
83 exit-latency-us = <500>; 83 exit-latency-us = <500>;
84 min-residency-us = <5000>; 84 min-residency-us = <5000>;
85 }; 85 };
86 86
87 CLUSTER_SLEEP: cluster-sleep { 87 CLUSTER_SLEEP: cluster-sleep {
88 compatible = "arm,idle-state"; 88 compatible = "arm,idle-state";
89 arm,psci-suspend-param = <0x10033>; 89 arm,psci-suspend-param = <0x10033>;
90 local-timer-stop; 90 local-timer-stop;
91 entry-latency-us = <500>; 91 entry-latency-us = <500>;
92 exit-latency-us = <2300>; 92 exit-latency-us = <2300>;
93 min-residency-us = <14000>; 93 min-residency-us = <14000>;
94 }; 94 };
95 }; 95 };
96 }; 96 };
97 97
98 memory@80000000 { 98 memory@80000000 {
99 device_type = "memory"; 99 device_type = "memory";
100 reg = <0x00000000 0x80000000 0 0x40000000>; 100 reg = <0x00000000 0x80000000 0 0x40000000>;
101 /* DRAM space - 1, size : 1 GB DRAM */ 101 /* DRAM space - 1, size : 1 GB DRAM */
102 }; 102 };
103 103
104 reserved-memory { 104 reserved-memory {
105 #address-cells = <2>; 105 #address-cells = <2>;
106 #size-cells = <2>; 106 #size-cells = <2>;
107 ranges; 107 ranges;
108 108
109 /* 109 /*
110 * reserved-memory layout 110 * reserved-memory layout
111 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 111 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
112 * Shouldn't be used at A core and Linux side. 112 * Shouldn't be used at A core and Linux side.
113 * 113 *
114 */ 114 */
115 decoder_boot: decoder_boot@0x84000000 { 115 decoder_boot: decoder_boot@0x84000000 {
116 no-map; 116 no-map;
117 reg = <0 0x84000000 0 0x2000000>; 117 reg = <0 0x84000000 0 0x2000000>;
118 }; 118 };
119 encoder_boot: encoder_boot@0x86000000 { 119 encoder_boot: encoder_boot@0x86000000 {
120 no-map; 120 no-map;
121 reg = <0 0x86000000 0 0x200000>; 121 reg = <0 0x86000000 0 0x200000>;
122 }; 122 };
123 rpmsg_reserved: rpmsg@0x90000000 { 123 rpmsg_reserved: rpmsg@0x90000000 {
124 no-map; 124 no-map;
125 reg = <0 0x90000000 0 0x400000>; 125 reg = <0 0x90000000 0 0x400000>;
126 }; 126 };
127 rpmsg_dma_reserved:rpmsg_dma@0x90400000 { 127 rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
128 compatible = "shared-dma-pool"; 128 compatible = "shared-dma-pool";
129 no-map; 129 no-map;
130 reg = <0 0x90400000 0 0x1C00000>; 130 reg = <0 0x90400000 0 0x1C00000>;
131 }; 131 };
132 decoder_rpc: decoder_rpc@0x92000000 { 132 decoder_rpc: decoder_rpc@0x92000000 {
133 no-map; 133 no-map;
134 reg = <0 0x92000000 0 0x200000>; 134 reg = <0 0x92000000 0 0x200000>;
135 }; 135 };
136 encoder_rpc: encoder_rpc@0x92200000 { 136 encoder_rpc: encoder_rpc@0x92200000 {
137 no-map; 137 no-map;
138 reg = <0 0x92200000 0 0x200000>; 138 reg = <0 0x92200000 0 0x200000>;
139 }; 139 };
140 dsp_reserved: dsp@0x92400000 { 140 dsp_reserved: dsp@0x92400000 {
141 no-map; 141 no-map;
142 reg = <0 0x92400000 0 0x2000000>; 142 reg = <0 0x92400000 0 0x2000000>;
143 }; 143 };
144 encoder_reserved: encoder_reserved@0x94400000 { 144 encoder_reserved: encoder_reserved@0x94400000 {
145 no-map; 145 no-map;
146 reg = <0 0x94400000 0 0x800000>; 146 reg = <0 0x94400000 0 0x800000>;
147 }; 147 };
148 /* global autoconfigured region for contiguous allocations */ 148 /* global autoconfigured region for contiguous allocations */
149 linux,cma { 149 linux,cma {
150 compatible = "shared-dma-pool"; 150 compatible = "shared-dma-pool";
151 reusable; 151 reusable;
152 size = <0 0x3c000000>; 152 size = <0 0x3c000000>;
153 alloc-ranges = <0 0x96000000 0 0x3c000000>; 153 alloc-ranges = <0 0x96000000 0 0x3c000000>;
154 linux,cma-default; 154 linux,cma-default;
155 }; 155 };
156 }; 156 };
157 157
158 gic: interrupt-controller@51a00000 { 158 gic: interrupt-controller@51a00000 {
159 compatible = "arm,gic-v3"; 159 compatible = "arm,gic-v3";
160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 160 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
161 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 161 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
162 #interrupt-cells = <3>; 162 #interrupt-cells = <3>;
163 interrupt-controller; 163 interrupt-controller;
164 interrupts = <GIC_PPI 9 164 interrupts = <GIC_PPI 9
165 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 165 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
166 interrupt-parent = <&gic>; 166 interrupt-parent = <&gic>;
167 }; 167 };
168 168
169 mu8: mu@5d230000 { 169 mu8: mu@5d230000 {
170 compatible = "fsl,imx-m4-mu"; 170 compatible = "fsl,imx-m4-mu";
171 reg = <0x0 0x5d230000 0x0 0x10000>; 171 reg = <0x0 0x5d230000 0x0 0x10000>;
172 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 172 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
173 power-domains = <&pd_lsio_mu8a>; 173 power-domains = <&pd_lsio_mu8a>;
174 status = "okay"; 174 status = "okay";
175 }; 175 };
176 176
177 mu: mu@5d1c0000 { 177 mu: mu@5d1c0000 {
178 compatible = "fsl,imx8-mu"; 178 compatible = "fsl,imx8-mu";
179 reg = <0x0 0x5d1c0000 0x0 0x10000>; 179 reg = <0x0 0x5d1c0000 0x0 0x10000>;
180 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 180 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
181 interrupt-parent = <&gic>; 181 interrupt-parent = <&gic>;
182 status = "okay"; 182 status = "okay";
183 183
184 clk: clk { 184 clk: clk {
185 compatible = "fsl,imx8qxp-clk"; 185 compatible = "fsl,imx8qxp-clk";
186 #clock-cells = <1>; 186 #clock-cells = <1>;
187 }; 187 };
188 188
189 iomuxc: iomuxc { 189 iomuxc: iomuxc {
190 compatible = "fsl,imx8qxp-iomuxc"; 190 compatible = "fsl,imx8qxp-iomuxc";
191 }; 191 };
192 }; 192 };
193 193
194 mu13: mu13@5d280000 { 194 mu13: mu13@5d280000 {
195 compatible = "fsl,imx8-mu-dsp"; 195 compatible = "fsl,imx8-mu-dsp";
196 reg = <0x0 0x5d280000 0x0 0x10000>; 196 reg = <0x0 0x5d280000 0x0 0x10000>;
197 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 197 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
198 fsl,dsp_ap_mu_id = <13>; 198 fsl,dsp_ap_mu_id = <13>;
199 status = "okay"; 199 status = "okay";
200 }; 200 };
201 201
202 mu_m4: mu_m4@37440000 { 202 mu_m4: mu_m4@37440000 {
203 compatible = "fsl,imx8-mu0-vpu-m4"; 203 compatible = "fsl,imx8-mu0-vpu-m4";
204 reg = <0x0 0x37440000 0x0 0x10000>; 204 reg = <0x0 0x37440000 0x0 0x10000>;
205 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 205 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
206 fsl,vpu_ap_mu_id = <15>; 206 fsl,vpu_ap_mu_id = <15>;
207 status = "okay"; 207 status = "okay";
208 }; 208 };
209 209
210 mu_m0: mu_m0@2d000000 { 210 mu_m0: mu_m0@2d000000 {
211 compatible = "fsl,imx8-mu0-vpu-m0"; 211 compatible = "fsl,imx8-mu0-vpu-m0";
212 reg = <0x0 0x2d000000 0x0 0x20000>; 212 reg = <0x0 0x2d000000 0x0 0x20000>;
213 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 213 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
214 fsl,vpu_ap_mu_id = <16>; 214 fsl,vpu_ap_mu_id = <16>;
215 status = "okay"; 215 status = "okay";
216 }; 216 };
217 217
218 mu1_m0: mu1_m0@2d020000 { 218 mu1_m0: mu1_m0@2d020000 {
219 compatible = "fsl,imx8-mu1-vpu-m0"; 219 compatible = "fsl,imx8-mu1-vpu-m0";
220 reg = <0x0 0x2d020000 0x0 0x20000>; 220 reg = <0x0 0x2d020000 0x0 0x20000>;
221 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 221 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
222 fsl,vpu_ap_mu_id = <17>; 222 fsl,vpu_ap_mu_id = <17>;
223 status = "okay"; 223 status = "okay";
224 }; 224 };
225 225
226 rtc: rtc { 226 rtc: rtc {
227 compatible = "fsl,imx-sc-rtc"; 227 compatible = "fsl,imx-sc-rtc";
228 }; 228 };
229 229
230 timer { 230 timer {
231 compatible = "arm,armv8-timer"; 231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
236 clock-frequency = <8000000>; 236 clock-frequency = <8000000>;
237 interrupt-parent = <&gic>; 237 interrupt-parent = <&gic>;
238 }; 238 };
239 239
240 imx8qx-pm { 240 imx8qx-pm {
241 compatible = "simple-bus"; 241 compatible = "simple-bus";
242 #address-cells = <1>; 242 #address-cells = <1>;
243 #size-cells = <0>; 243 #size-cells = <0>;
244 244
245 pd_lsio: PD_LSIO { 245 pd_lsio: PD_LSIO {
246 compatible = "nxp,imx8-pd"; 246 compatible = "nxp,imx8-pd";
247 reg = <SC_R_NONE>; 247 reg = <SC_R_NONE>;
248 #power-domain-cells = <0>; 248 #power-domain-cells = <0>;
249 #address-cells = <1>; 249 #address-cells = <1>;
250 #size-cells = <0>; 250 #size-cells = <0>;
251 251
252 pd_lsio_pwm0: PD_LSIO_PWM_0 { 252 pd_lsio_pwm0: PD_LSIO_PWM_0 {
253 reg = <SC_R_PWM_0>; 253 reg = <SC_R_PWM_0>;
254 #power-domain-cells = <0>; 254 #power-domain-cells = <0>;
255 power-domains = <&pd_lsio>; 255 power-domains = <&pd_lsio>;
256 }; 256 };
257 pd_lsio_pwm1: PD_LSIO_PWM_1 { 257 pd_lsio_pwm1: PD_LSIO_PWM_1 {
258 reg = <SC_R_PWM_1>; 258 reg = <SC_R_PWM_1>;
259 #power-domain-cells = <0>; 259 #power-domain-cells = <0>;
260 power-domains = <&pd_lsio>; 260 power-domains = <&pd_lsio>;
261 }; 261 };
262 pd_lsio_pwm2: PD_LSIO_PWM_2 { 262 pd_lsio_pwm2: PD_LSIO_PWM_2 {
263 reg = <SC_R_PWM_2>; 263 reg = <SC_R_PWM_2>;
264 #power-domain-cells = <0>; 264 #power-domain-cells = <0>;
265 power-domains = <&pd_lsio>; 265 power-domains = <&pd_lsio>;
266 }; 266 };
267 pd_lsio_pwm3: PD_LSIO_PWM_3 { 267 pd_lsio_pwm3: PD_LSIO_PWM_3 {
268 reg = <SC_R_PWM_3>; 268 reg = <SC_R_PWM_3>;
269 #power-domain-cells = <0>; 269 #power-domain-cells = <0>;
270 power-domains = <&pd_lsio>; 270 power-domains = <&pd_lsio>;
271 }; 271 };
272 pd_lsio_pwm4: PD_LSIO_PWM_4 { 272 pd_lsio_pwm4: PD_LSIO_PWM_4 {
273 reg = <SC_R_PWM_4>; 273 reg = <SC_R_PWM_4>;
274 #power-domain-cells = <0>; 274 #power-domain-cells = <0>;
275 power-domains = <&pd_lsio>; 275 power-domains = <&pd_lsio>;
276 }; 276 };
277 pd_lsio_pwm5: PD_LSIO_PWM_5 { 277 pd_lsio_pwm5: PD_LSIO_PWM_5 {
278 reg = <SC_R_PWM_5>; 278 reg = <SC_R_PWM_5>;
279 #power-domain-cells = <0>; 279 #power-domain-cells = <0>;
280 power-domains = <&pd_lsio>; 280 power-domains = <&pd_lsio>;
281 }; 281 };
282 pd_lsio_pwm6: PD_LSIO_PWM_6 { 282 pd_lsio_pwm6: PD_LSIO_PWM_6 {
283 reg = <SC_R_PWM_6>; 283 reg = <SC_R_PWM_6>;
284 #power-domain-cells = <0>; 284 #power-domain-cells = <0>;
285 power-domains = <&pd_lsio>; 285 power-domains = <&pd_lsio>;
286 }; 286 };
287 pd_lsio_pwm7: PD_LSIO_PWM_7 { 287 pd_lsio_pwm7: PD_LSIO_PWM_7 {
288 reg = <SC_R_PWM_7>; 288 reg = <SC_R_PWM_7>;
289 #power-domain-cells = <0>; 289 #power-domain-cells = <0>;
290 power-domains = <&pd_lsio>; 290 power-domains = <&pd_lsio>;
291 }; 291 };
292 pd_lsio_kpp: PD_LSIO_KPP { 292 pd_lsio_kpp: PD_LSIO_KPP {
293 reg = <SC_R_KPP>; 293 reg = <SC_R_KPP>;
294 #power-domain-cells = <0>; 294 #power-domain-cells = <0>;
295 power-domains = <&pd_lsio>; 295 power-domains = <&pd_lsio>;
296 }; 296 };
297 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 297 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
298 reg = <SC_R_GPIO_0>; 298 reg = <SC_R_GPIO_0>;
299 #power-domain-cells = <0>; 299 #power-domain-cells = <0>;
300 power-domains = <&pd_lsio>; 300 power-domains = <&pd_lsio>;
301 }; 301 };
302 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 302 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
303 reg = <SC_R_GPIO_1>; 303 reg = <SC_R_GPIO_1>;
304 #power-domain-cells = <0>; 304 #power-domain-cells = <0>;
305 power-domains = <&pd_lsio>; 305 power-domains = <&pd_lsio>;
306 }; 306 };
307 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 307 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
308 reg = <SC_R_GPIO_2>; 308 reg = <SC_R_GPIO_2>;
309 #power-domain-cells = <0>; 309 #power-domain-cells = <0>;
310 power-domains = <&pd_lsio>; 310 power-domains = <&pd_lsio>;
311 }; 311 };
312 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 312 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
313 reg = <SC_R_GPIO_3>; 313 reg = <SC_R_GPIO_3>;
314 #power-domain-cells = <0>; 314 #power-domain-cells = <0>;
315 power-domains = <&pd_lsio>; 315 power-domains = <&pd_lsio>;
316 }; 316 };
317 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 317 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
318 reg = <SC_R_GPIO_4>; 318 reg = <SC_R_GPIO_4>;
319 #power-domain-cells = <0>; 319 #power-domain-cells = <0>;
320 power-domains = <&pd_lsio>; 320 power-domains = <&pd_lsio>;
321 }; 321 };
322 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 322 pd_lsio_gpio5: PD_LSIO_GPIO_5{
323 reg = <SC_R_GPIO_5>; 323 reg = <SC_R_GPIO_5>;
324 #power-domain-cells = <0>; 324 #power-domain-cells = <0>;
325 power-domains = <&pd_lsio>; 325 power-domains = <&pd_lsio>;
326 }; 326 };
327 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 327 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
328 reg = <SC_R_GPIO_6>; 328 reg = <SC_R_GPIO_6>;
329 #power-domain-cells = <0>; 329 #power-domain-cells = <0>;
330 power-domains = <&pd_lsio>; 330 power-domains = <&pd_lsio>;
331 }; 331 };
332 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 332 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
333 reg = <SC_R_GPIO_7>; 333 reg = <SC_R_GPIO_7>;
334 #power-domain-cells = <0>; 334 #power-domain-cells = <0>;
335 power-domains = <&pd_lsio>; 335 power-domains = <&pd_lsio>;
336 }; 336 };
337 pd_lsio_gpt0: PD_LSIO_GPT_0 { 337 pd_lsio_gpt0: PD_LSIO_GPT_0 {
338 reg = <SC_R_GPT_0>; 338 reg = <SC_R_GPT_0>;
339 #power-domain-cells = <0>; 339 #power-domain-cells = <0>;
340 power-domains = <&pd_lsio>; 340 power-domains = <&pd_lsio>;
341 }; 341 };
342 pd_lsio_gpt1: PD_LSIO_GPT_1 { 342 pd_lsio_gpt1: PD_LSIO_GPT_1 {
343 reg = <SC_R_GPT_1>; 343 reg = <SC_R_GPT_1>;
344 #power-domain-cells = <0>; 344 #power-domain-cells = <0>;
345 power-domains = <&pd_lsio>; 345 power-domains = <&pd_lsio>;
346 }; 346 };
347 pd_lsio_gpt2: PD_LSIO_GPT_2 { 347 pd_lsio_gpt2: PD_LSIO_GPT_2 {
348 reg = <SC_R_GPT_2>; 348 reg = <SC_R_GPT_2>;
349 #power-domain-cells = <0>; 349 #power-domain-cells = <0>;
350 power-domains = <&pd_lsio>; 350 power-domains = <&pd_lsio>;
351 }; 351 };
352 pd_lsio_gpt3: PD_LSIO_GPT_3 { 352 pd_lsio_gpt3: PD_LSIO_GPT_3 {
353 reg = <SC_R_GPT_3>; 353 reg = <SC_R_GPT_3>;
354 #power-domain-cells = <0>; 354 #power-domain-cells = <0>;
355 power-domains = <&pd_lsio>; 355 power-domains = <&pd_lsio>;
356 }; 356 };
357 pd_lsio_gpt4: PD_LSIO_GPT_4 { 357 pd_lsio_gpt4: PD_LSIO_GPT_4 {
358 reg = <SC_R_GPT_4>; 358 reg = <SC_R_GPT_4>;
359 #power-domain-cells = <0>; 359 #power-domain-cells = <0>;
360 power-domains = <&pd_lsio>; 360 power-domains = <&pd_lsio>;
361 }; 361 };
362 pd_lsio_flexspi0: PD_LSIO_FSPI_0 { 362 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
363 reg = <SC_R_FSPI_0>; 363 reg = <SC_R_FSPI_0>;
364 #power-domain-cells = <0>; 364 #power-domain-cells = <0>;
365 power-domains = <&pd_lsio>; 365 power-domains = <&pd_lsio>;
366 }; 366 };
367 pd_lsio_flexspi1: PD_LSIO_FSPI_1{ 367 pd_lsio_flexspi1: PD_LSIO_FSPI_1{
368 reg = <SC_R_FSPI_1>; 368 reg = <SC_R_FSPI_1>;
369 #power-domain-cells = <0>; 369 #power-domain-cells = <0>;
370 power-domains = <&pd_lsio>; 370 power-domains = <&pd_lsio>;
371 }; 371 };
372 pd_lsio_mu5a: PD_LSIO_MU5A { 372 pd_lsio_mu5a: PD_LSIO_MU5A {
373 reg = <SC_R_MU_5A>; 373 reg = <SC_R_MU_5A>;
374 #power-domain-cells = <0>; 374 #power-domain-cells = <0>;
375 power-domains = <&pd_lsio>; 375 power-domains = <&pd_lsio>;
376 }; 376 };
377 pd_lsio_mu8a: PD_LSIO_MU8A { 377 pd_lsio_mu8a: PD_LSIO_MU8A {
378 reg = <SC_R_MU_8A>; 378 reg = <SC_R_MU_8A>;
379 #power-domain-cells = <0>; 379 #power-domain-cells = <0>;
380 power-domains = <&pd_lsio>; 380 power-domains = <&pd_lsio>;
381 }; 381 };
382 }; 382 };
383 383
384 pd_conn: PD_CONN { 384 pd_conn: PD_CONN {
385 compatible = "nxp,imx8-pd"; 385 compatible = "nxp,imx8-pd";
386 reg = <SC_R_NONE>; 386 reg = <SC_R_NONE>;
387 #power-domain-cells = <0>; 387 #power-domain-cells = <0>;
388 #address-cells = <1>; 388 #address-cells = <1>;
389 #size-cells = <0>; 389 #size-cells = <0>;
390 390
391 pd_conn_usbotg0: PD_CONN_USB_0 { 391 pd_conn_usbotg0: PD_CONN_USB_0 {
392 reg = <SC_R_USB_0>; 392 reg = <SC_R_USB_0>;
393 #power-domain-cells = <0>; 393 #power-domain-cells = <0>;
394 power-domains = <&pd_conn>; 394 power-domains = <&pd_conn>;
395 #address-cells = <1>; 395 #address-cells = <1>;
396 #size-cells = <0>; 396 #size-cells = <0>;
397 wakeup-irq = <267>; 397 wakeup-irq = <267>;
398 398
399 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { 399 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
400 reg = <SC_R_USB_0_PHY>; 400 reg = <SC_R_USB_0_PHY>;
401 #power-domain-cells = <0>; 401 #power-domain-cells = <0>;
402 power-domains = <&pd_conn_usbotg0>; 402 power-domains = <&pd_conn_usbotg0>;
403 wakeup-irq = <267>; 403 wakeup-irq = <267>;
404 }; 404 };
405 405
406 }; 406 };
407 pd_conn_usbotg1: PD_CONN_USB_1 { 407 pd_conn_usbotg1: PD_CONN_USB_1 {
408 reg = <SC_R_USB_1>; 408 reg = <SC_R_USB_1>;
409 #power-domain-cells = <0>; 409 #power-domain-cells = <0>;
410 power-domains = <&pd_conn>; 410 power-domains = <&pd_conn>;
411 }; 411 };
412 pd_conn_usb2: PD_CONN_USB_2 { 412 pd_conn_usb2: PD_CONN_USB_2 {
413 reg = <SC_R_USB_2>; 413 reg = <SC_R_USB_2>;
414 #power-domain-cells = <0>; 414 #power-domain-cells = <0>;
415 #address-cells = <1>; 415 #address-cells = <1>;
416 #size-cells = <0>; 416 #size-cells = <0>;
417 power-domains = <&pd_conn>; 417 power-domains = <&pd_conn>;
418 wakeup-irq = <271>; 418 wakeup-irq = <271>;
419 419
420 pd_conn_usb2_phy: PD_CONN_USB_2_PHY { 420 pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
421 reg = <SC_R_USB_2_PHY>; 421 reg = <SC_R_USB_2_PHY>;
422 #power-domain-cells = <0>; 422 #power-domain-cells = <0>;
423 power-domains = <&pd_conn_usb2>; 423 power-domains = <&pd_conn_usb2>;
424 wakeup-irq = <271>; 424 wakeup-irq = <271>;
425 }; 425 };
426 426
427 }; 427 };
428 pd_conn_sdch0: PD_CONN_SDHC_0 { 428 pd_conn_sdch0: PD_CONN_SDHC_0 {
429 reg = <SC_R_SDHC_0>; 429 reg = <SC_R_SDHC_0>;
430 #power-domain-cells = <0>; 430 #power-domain-cells = <0>;
431 power-domains = <&pd_conn>; 431 power-domains = <&pd_conn>;
432 }; 432 };
433 pd_conn_sdch1: PD_CONN_SDHC_1 { 433 pd_conn_sdch1: PD_CONN_SDHC_1 {
434 reg = <SC_R_SDHC_1>; 434 reg = <SC_R_SDHC_1>;
435 #power-domain-cells = <0>; 435 #power-domain-cells = <0>;
436 power-domains = <&pd_conn>; 436 power-domains = <&pd_conn>;
437 }; 437 };
438 pd_conn_sdch2: PD_CONN_SDHC_2 { 438 pd_conn_sdch2: PD_CONN_SDHC_2 {
439 reg = <SC_R_SDHC_2>; 439 reg = <SC_R_SDHC_2>;
440 #power-domain-cells = <0>; 440 #power-domain-cells = <0>;
441 power-domains = <&pd_conn>; 441 power-domains = <&pd_conn>;
442 }; 442 };
443 pd_conn_enet0: PD_CONN_ENET_0 { 443 pd_conn_enet0: PD_CONN_ENET_0 {
444 reg = <SC_R_ENET_0>; 444 reg = <SC_R_ENET_0>;
445 #power-domain-cells = <0>; 445 #power-domain-cells = <0>;
446 power-domains = <&pd_conn>; 446 power-domains = <&pd_conn>;
447 wakeup-irq = <258>; 447 wakeup-irq = <258>;
448 }; 448 };
449 pd_conn_enet1: PD_CONN_ENET_1 { 449 pd_conn_enet1: PD_CONN_ENET_1 {
450 reg = <SC_R_ENET_1>; 450 reg = <SC_R_ENET_1>;
451 #power-domain-cells = <0>; 451 #power-domain-cells = <0>;
452 power-domains = <&pd_conn>; 452 power-domains = <&pd_conn>;
453 fsl,wakeup_irq = <262>; 453 fsl,wakeup_irq = <262>;
454 }; 454 };
455 pd_conn_nand: PD_CONN_NAND { 455 pd_conn_nand: PD_CONN_NAND {
456 reg = <SC_R_NAND>; 456 reg = <SC_R_NAND>;
457 #power-domain-cells = <0>; 457 #power-domain-cells = <0>;
458 power-domains = <&pd_conn>; 458 power-domains = <&pd_conn>;
459 }; 459 };
460 pd_conn_mlb0: PD_CONN_MLB_0 { 460 pd_conn_mlb0: PD_CONN_MLB_0 {
461 reg = <SC_R_MLB_0>; 461 reg = <SC_R_MLB_0>;
462 #power-domain-cells = <0>; 462 #power-domain-cells = <0>;
463 power-domains = <&pd_conn>; 463 power-domains = <&pd_conn>;
464 }; 464 };
465 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { 465 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
466 reg = <SC_R_DMA_4_CH0>; 466 reg = <SC_R_DMA_4_CH0>;
467 #power-domain-cells = <0>; 467 #power-domain-cells = <0>;
468 power-domains =<&pd_conn>; 468 power-domains =<&pd_conn>;
469 }; 469 };
470 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { 470 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
471 reg = <SC_R_DMA_4_CH1>; 471 reg = <SC_R_DMA_4_CH1>;
472 #power-domain-cells = <0>; 472 #power-domain-cells = <0>;
473 power-domains =<&pd_conn>; 473 power-domains =<&pd_conn>;
474 }; 474 };
475 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { 475 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
476 reg = <SC_R_DMA_4_CH2>; 476 reg = <SC_R_DMA_4_CH2>;
477 #power-domain-cells = <0>; 477 #power-domain-cells = <0>;
478 power-domains =<&pd_conn>; 478 power-domains =<&pd_conn>;
479 }; 479 };
480 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { 480 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
481 reg = <SC_R_DMA_4_CH3>; 481 reg = <SC_R_DMA_4_CH3>;
482 #power-domain-cells = <0>; 482 #power-domain-cells = <0>;
483 power-domains =<&pd_conn>; 483 power-domains =<&pd_conn>;
484 }; 484 };
485 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { 485 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
486 reg = <SC_R_DMA_4_CH4>; 486 reg = <SC_R_DMA_4_CH4>;
487 #power-domain-cells = <0>; 487 #power-domain-cells = <0>;
488 power-domains =<&pd_conn>; 488 power-domains =<&pd_conn>;
489 }; 489 };
490 }; 490 };
491 491
492 pd_audio: PD_AUDIO { 492 pd_audio: PD_AUDIO {
493 compatible = "nxp,imx8-pd"; 493 compatible = "nxp,imx8-pd";
494 reg = <SC_R_NONE>; 494 reg = <SC_R_NONE>;
495 #power-domain-cells = <0>; 495 #power-domain-cells = <0>;
496 #address-cells = <1>; 496 #address-cells = <1>;
497 #size-cells = <0>; 497 #size-cells = <0>;
498 498
499 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { 499 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
500 reg = <SC_R_AUDIO_PLL_0>; 500 reg = <SC_R_AUDIO_PLL_0>;
501 power-domains =<&pd_audio>; 501 power-domains =<&pd_audio>;
502 #power-domain-cells = <0>; 502 #power-domain-cells = <0>;
503 #address-cells = <1>; 503 #address-cells = <1>;
504 #size-cells = <0>; 504 #size-cells = <0>;
505 505
506 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { 506 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
507 reg = <SC_R_AUDIO_PLL_1>; 507 reg = <SC_R_AUDIO_PLL_1>;
508 power-domains =<&pd_audio_pll0>; 508 power-domains =<&pd_audio_pll0>;
509 #power-domain-cells = <0>; 509 #power-domain-cells = <0>;
510 #address-cells = <1>; 510 #address-cells = <1>;
511 #size-cells = <0>; 511 #size-cells = <0>;
512 512
513 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { 513 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
514 reg = <SC_R_AUDIO_CLK_0>; 514 reg = <SC_R_AUDIO_CLK_0>;
515 power-domains =<&pd_audio_pll1>; 515 power-domains =<&pd_audio_pll1>;
516 #power-domain-cells = <0>; 516 #power-domain-cells = <0>;
517 #address-cells = <1>; 517 #address-cells = <1>;
518 #size-cells = <0>; 518 #size-cells = <0>;
519 519
520 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { 520 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
521 reg = <SC_R_AUDIO_CLK_1>; 521 reg = <SC_R_AUDIO_CLK_1>;
522 #power-domain-cells = <0>; 522 #power-domain-cells = <0>;
523 power-domains =<&pd_audio_clk0>; 523 power-domains =<&pd_audio_clk0>;
524 #address-cells = <1>; 524 #address-cells = <1>;
525 #size-cells = <0>; 525 #size-cells = <0>;
526 526
527 pd_dma0_chan0: PD_ASRC_0_RXA { 527 pd_dma0_chan0: PD_ASRC_0_RXA {
528 reg = <SC_R_DMA_0_CH0>; 528 reg = <SC_R_DMA_0_CH0>;
529 power-domains =<&pd_audio_clk1>; 529 power-domains =<&pd_audio_clk1>;
530 #power-domain-cells = <0>; 530 #power-domain-cells = <0>;
531 #address-cells = <1>; 531 #address-cells = <1>;
532 #size-cells = <0>; 532 #size-cells = <0>;
533 533
534 pd_dma0_chan1: PD_ASRC_0_RXB { 534 pd_dma0_chan1: PD_ASRC_0_RXB {
535 reg = <SC_R_DMA_0_CH1>; 535 reg = <SC_R_DMA_0_CH1>;
536 power-domains =<&pd_dma0_chan0>; 536 power-domains =<&pd_dma0_chan0>;
537 #power-domain-cells = <0>; 537 #power-domain-cells = <0>;
538 #address-cells = <1>; 538 #address-cells = <1>;
539 #size-cells = <0>; 539 #size-cells = <0>;
540 540
541 pd_dma0_chan2: PD_ASRC_0_RXC { 541 pd_dma0_chan2: PD_ASRC_0_RXC {
542 reg = <SC_R_DMA_0_CH2>; 542 reg = <SC_R_DMA_0_CH2>;
543 power-domains =<&pd_dma0_chan1>; 543 power-domains =<&pd_dma0_chan1>;
544 #power-domain-cells = <0>; 544 #power-domain-cells = <0>;
545 #address-cells = <1>; 545 #address-cells = <1>;
546 #size-cells = <0>; 546 #size-cells = <0>;
547 547
548 pd_dma0_chan3: PD_ASRC_0_TXA { 548 pd_dma0_chan3: PD_ASRC_0_TXA {
549 reg = <SC_R_DMA_0_CH3>; 549 reg = <SC_R_DMA_0_CH3>;
550 power-domains =<&pd_dma0_chan2>; 550 power-domains =<&pd_dma0_chan2>;
551 #power-domain-cells = <0>; 551 #power-domain-cells = <0>;
552 #address-cells = <1>; 552 #address-cells = <1>;
553 #size-cells = <0>; 553 #size-cells = <0>;
554 554
555 pd_dma0_chan4: PD_ASRC_0_TXB { 555 pd_dma0_chan4: PD_ASRC_0_TXB {
556 reg = <SC_R_DMA_0_CH4>; 556 reg = <SC_R_DMA_0_CH4>;
557 power-domains =<&pd_dma0_chan3>; 557 power-domains =<&pd_dma0_chan3>;
558 #power-domain-cells = <0>; 558 #power-domain-cells = <0>;
559 #address-cells = <1>; 559 #address-cells = <1>;
560 #size-cells = <0>; 560 #size-cells = <0>;
561 561
562 pd_dma0_chan5: PD_ASRC_0_TXC { 562 pd_dma0_chan5: PD_ASRC_0_TXC {
563 reg = <SC_R_DMA_0_CH5>; 563 reg = <SC_R_DMA_0_CH5>;
564 power-domains =<&pd_dma0_chan4>; 564 power-domains =<&pd_dma0_chan4>;
565 #power-domain-cells = <0>; 565 #power-domain-cells = <0>;
566 #address-cells = <1>; 566 #address-cells = <1>;
567 #size-cells = <0>; 567 #size-cells = <0>;
568 568
569 pd_asrc0:PD_AUD_ASRC_0 { 569 pd_asrc0:PD_AUD_ASRC_0 {
570 reg = <SC_R_ASRC_0>; 570 reg = <SC_R_ASRC_0>;
571 #power-domain-cells = <0>; 571 #power-domain-cells = <0>;
572 power-domains =<&pd_dma0_chan5>; 572 power-domains =<&pd_dma0_chan5>;
573 }; 573 };
574 }; 574 };
575 }; 575 };
576 }; 576 };
577 }; 577 };
578 }; 578 };
579 }; 579 };
580 580
581 pd_dma1_chan0: PD_ASRC_1_RXA { 581 pd_dma1_chan0: PD_ASRC_1_RXA {
582 reg = <SC_R_DMA_1_CH0>; 582 reg = <SC_R_DMA_1_CH0>;
583 power-domains =<&pd_audio_clk1>; 583 power-domains =<&pd_audio_clk1>;
584 #power-domain-cells = <0>; 584 #power-domain-cells = <0>;
585 #address-cells = <1>; 585 #address-cells = <1>;
586 #size-cells = <0>; 586 #size-cells = <0>;
587 587
588 pd_dma1_chan1: PD_ASRC_1_RXB { 588 pd_dma1_chan1: PD_ASRC_1_RXB {
589 reg = <SC_R_DMA_1_CH1>; 589 reg = <SC_R_DMA_1_CH1>;
590 power-domains =<&pd_dma1_chan0>; 590 power-domains =<&pd_dma1_chan0>;
591 #power-domain-cells = <0>; 591 #power-domain-cells = <0>;
592 #address-cells = <1>; 592 #address-cells = <1>;
593 #size-cells = <0>; 593 #size-cells = <0>;
594 594
595 pd_dma1_chan2: PD_ASRC_1_RXC { 595 pd_dma1_chan2: PD_ASRC_1_RXC {
596 reg = <SC_R_DMA_1_CH2>; 596 reg = <SC_R_DMA_1_CH2>;
597 power-domains =<&pd_dma1_chan1>; 597 power-domains =<&pd_dma1_chan1>;
598 #power-domain-cells = <0>; 598 #power-domain-cells = <0>;
599 #address-cells = <1>; 599 #address-cells = <1>;
600 #size-cells = <0>; 600 #size-cells = <0>;
601 601
602 pd_dma1_chan3: PD_ASRC_1_TXA { 602 pd_dma1_chan3: PD_ASRC_1_TXA {
603 reg = <SC_R_DMA_1_CH3>; 603 reg = <SC_R_DMA_1_CH3>;
604 power-domains =<&pd_dma1_chan2>; 604 power-domains =<&pd_dma1_chan2>;
605 #power-domain-cells = <0>; 605 #power-domain-cells = <0>;
606 #address-cells = <1>; 606 #address-cells = <1>;
607 #size-cells = <0>; 607 #size-cells = <0>;
608 608
609 pd_dma1_chan4: PD_ASRC_1_TXB { 609 pd_dma1_chan4: PD_ASRC_1_TXB {
610 reg = <SC_R_DMA_1_CH4>; 610 reg = <SC_R_DMA_1_CH4>;
611 power-domains =<&pd_dma1_chan3>; 611 power-domains =<&pd_dma1_chan3>;
612 #power-domain-cells = <0>; 612 #power-domain-cells = <0>;
613 #address-cells = <1>; 613 #address-cells = <1>;
614 #size-cells = <0>; 614 #size-cells = <0>;
615 615
616 pd_dma1_chan5: PD_ASRC_1_TXC { 616 pd_dma1_chan5: PD_ASRC_1_TXC {
617 reg = <SC_R_DMA_1_CH5>; 617 reg = <SC_R_DMA_1_CH5>;
618 power-domains =<&pd_dma1_chan4>; 618 power-domains =<&pd_dma1_chan4>;
619 #power-domain-cells = <0>; 619 #power-domain-cells = <0>;
620 #address-cells = <1>; 620 #address-cells = <1>;
621 #size-cells = <0>; 621 #size-cells = <0>;
622 622
623 pd_asrc1: PD_AUD_ASRC_1 { 623 pd_asrc1: PD_AUD_ASRC_1 {
624 reg = <SC_R_ASRC_1>; 624 reg = <SC_R_ASRC_1>;
625 #power-domain-cells = <0>; 625 #power-domain-cells = <0>;
626 power-domains =<&pd_dma1_chan5>; 626 power-domains =<&pd_dma1_chan5>;
627 627
628 }; 628 };
629 }; 629 };
630 }; 630 };
631 }; 631 };
632 }; 632 };
633 }; 633 };
634 }; 634 };
635 pd_dma0_chan6: PD_ESAI_0_RX { 635 pd_dma0_chan6: PD_ESAI_0_RX {
636 reg = <SC_R_DMA_0_CH6>; 636 reg = <SC_R_DMA_0_CH6>;
637 power-domains =<&pd_audio_clk1>; 637 power-domains =<&pd_audio_clk1>;
638 #power-domain-cells = <0>; 638 #power-domain-cells = <0>;
639 #address-cells = <1>; 639 #address-cells = <1>;
640 #size-cells = <0>; 640 #size-cells = <0>;
641 641
642 pd_dma0_chan7: PD_ESAI_0_TX { 642 pd_dma0_chan7: PD_ESAI_0_TX {
643 reg = <SC_R_DMA_0_CH7>; 643 reg = <SC_R_DMA_0_CH7>;
644 power-domains =<&pd_dma0_chan6>; 644 power-domains =<&pd_dma0_chan6>;
645 #power-domain-cells = <0>; 645 #power-domain-cells = <0>;
646 #address-cells = <1>; 646 #address-cells = <1>;
647 #size-cells = <0>; 647 #size-cells = <0>;
648 648
649 pd_esai0: PD_AUD_ESAI_0 { 649 pd_esai0: PD_AUD_ESAI_0 {
650 reg = <SC_R_ESAI_0>; 650 reg = <SC_R_ESAI_0>;
651 #power-domain-cells = <0>; 651 #power-domain-cells = <0>;
652 power-domains =<&pd_dma0_chan7>; 652 power-domains =<&pd_dma0_chan7>;
653 }; 653 };
654 }; 654 };
655 }; 655 };
656 pd_dma0_chan8: PD_SPDIF_0_RX { 656 pd_dma0_chan8: PD_SPDIF_0_RX {
657 reg = <SC_R_DMA_0_CH8>; 657 reg = <SC_R_DMA_0_CH8>;
658 power-domains =<&pd_audio_clk1>; 658 power-domains =<&pd_audio_clk1>;
659 #power-domain-cells = <0>; 659 #power-domain-cells = <0>;
660 #address-cells = <1>; 660 #address-cells = <1>;
661 #size-cells = <0>; 661 #size-cells = <0>;
662 662
663 pd_dma0_chan9: PD_SPDIF_0_TX { 663 pd_dma0_chan9: PD_SPDIF_0_TX {
664 reg = <SC_R_DMA_0_CH9>; 664 reg = <SC_R_DMA_0_CH9>;
665 power-domains =<&pd_dma0_chan8>; 665 power-domains =<&pd_dma0_chan8>;
666 #power-domain-cells = <0>; 666 #power-domain-cells = <0>;
667 #address-cells = <1>; 667 #address-cells = <1>;
668 #size-cells = <0>; 668 #size-cells = <0>;
669 669
670 pd_spdif0: PD_AUD_SPDIF_0 { 670 pd_spdif0: PD_AUD_SPDIF_0 {
671 reg = <SC_R_SPDIF_0>; 671 reg = <SC_R_SPDIF_0>;
672 #power-domain-cells = <0>; 672 #power-domain-cells = <0>;
673 power-domains =<&pd_dma0_chan9>; 673 power-domains =<&pd_dma0_chan9>;
674 674
675 }; 675 };
676 }; 676 };
677 }; 677 };
678 pd_dma0_chan12: PD_SAI_0_RX { 678 pd_dma0_chan12: PD_SAI_0_RX {
679 reg = <SC_R_DMA_0_CH12>; 679 reg = <SC_R_DMA_0_CH12>;
680 power-domains =<&pd_audio_clk1>; 680 power-domains =<&pd_audio_clk1>;
681 #power-domain-cells = <0>; 681 #power-domain-cells = <0>;
682 #address-cells = <1>; 682 #address-cells = <1>;
683 #size-cells = <0>; 683 #size-cells = <0>;
684 684
685 pd_dma0_chan13: PD_SAI_0_TX { 685 pd_dma0_chan13: PD_SAI_0_TX {
686 reg = <SC_R_DMA_0_CH13>; 686 reg = <SC_R_DMA_0_CH13>;
687 power-domains =<&pd_dma0_chan12>; 687 power-domains =<&pd_dma0_chan12>;
688 #power-domain-cells = <0>; 688 #power-domain-cells = <0>;
689 #address-cells = <1>; 689 #address-cells = <1>;
690 #size-cells = <0>; 690 #size-cells = <0>;
691 691
692 pd_sai0:PD_AUD_SAI_0 { 692 pd_sai0:PD_AUD_SAI_0 {
693 reg = <SC_R_SAI_0>; 693 reg = <SC_R_SAI_0>;
694 #power-domain-cells = <0>; 694 #power-domain-cells = <0>;
695 power-domains =<&pd_dma0_chan13>; 695 power-domains =<&pd_dma0_chan13>;
696 }; 696 };
697 }; 697 };
698 698
699 }; 699 };
700 pd_dma0_chan14: PD_SAI_1_RX { 700 pd_dma0_chan14: PD_SAI_1_RX {
701 reg = <SC_R_DMA_0_CH14>; 701 reg = <SC_R_DMA_0_CH14>;
702 power-domains =<&pd_audio_clk1>; 702 power-domains =<&pd_audio_clk1>;
703 #power-domain-cells = <0>; 703 #power-domain-cells = <0>;
704 #address-cells = <1>; 704 #address-cells = <1>;
705 #size-cells = <0>; 705 #size-cells = <0>;
706 706
707 pd_dma0_chan15: PD_SAI_1_TX { 707 pd_dma0_chan15: PD_SAI_1_TX {
708 reg = <SC_R_DMA_0_CH15>; 708 reg = <SC_R_DMA_0_CH15>;
709 power-domains =<&pd_dma0_chan14>; 709 power-domains =<&pd_dma0_chan14>;
710 #power-domain-cells = <0>; 710 #power-domain-cells = <0>;
711 #address-cells = <1>; 711 #address-cells = <1>;
712 #size-cells = <0>; 712 #size-cells = <0>;
713 713
714 pd_sai1: PD_AUD_SAI_1 { 714 pd_sai1: PD_AUD_SAI_1 {
715 reg = <SC_R_SAI_1>; 715 reg = <SC_R_SAI_1>;
716 #power-domain-cells = <0>; 716 #power-domain-cells = <0>;
717 power-domains =<&pd_dma0_chan15>; 717 power-domains =<&pd_dma0_chan15>;
718 }; 718 };
719 }; 719 };
720 }; 720 };
721 pd_dma0_chan16: PD_SAI_2_RX { 721 pd_dma0_chan16: PD_SAI_2_RX {
722 reg = <SC_R_DMA_0_CH16>; 722 reg = <SC_R_DMA_0_CH16>;
723 power-domains =<&pd_audio_clk1>; 723 power-domains =<&pd_audio_clk1>;
724 #power-domain-cells = <0>; 724 #power-domain-cells = <0>;
725 #address-cells = <1>; 725 #address-cells = <1>;
726 #size-cells = <0>; 726 #size-cells = <0>;
727 pd_sai2: PD_AUD_SAI_2 { 727 pd_sai2: PD_AUD_SAI_2 {
728 reg = <SC_R_SAI_2>; 728 reg = <SC_R_SAI_2>;
729 #power-domain-cells = <0>; 729 #power-domain-cells = <0>;
730 power-domains =<&pd_dma0_chan16>; 730 power-domains =<&pd_dma0_chan16>;
731 }; 731 };
732 }; 732 };
733 pd_dma0_chan17: PD_SAI_3_RX { 733 pd_dma0_chan17: PD_SAI_3_RX {
734 reg = <SC_R_DMA_0_CH17>; 734 reg = <SC_R_DMA_0_CH17>;
735 power-domains =<&pd_audio_clk1>; 735 power-domains =<&pd_audio_clk1>;
736 #power-domain-cells = <0>; 736 #power-domain-cells = <0>;
737 #address-cells = <1>; 737 #address-cells = <1>;
738 #size-cells = <0>; 738 #size-cells = <0>;
739 739
740 pd_sai3: PD_AUD_SAI_3 { 740 pd_sai3: PD_AUD_SAI_3 {
741 reg = <SC_R_SAI_3>; 741 reg = <SC_R_SAI_3>;
742 #power-domain-cells = <0>; 742 #power-domain-cells = <0>;
743 power-domains =<&pd_dma0_chan17>; 743 power-domains =<&pd_dma0_chan17>;
744 }; 744 };
745 }; 745 };
746 pd_dma1_chan8: PD_SAI_4_RX { 746 pd_dma1_chan8: PD_SAI_4_RX {
747 reg = <SC_R_DMA_1_CH8>; 747 reg = <SC_R_DMA_1_CH8>;
748 power-domains =<&pd_audio_clk1>; 748 power-domains =<&pd_audio_clk1>;
749 #power-domain-cells = <0>; 749 #power-domain-cells = <0>;
750 #address-cells = <1>; 750 #address-cells = <1>;
751 #size-cells = <0>; 751 #size-cells = <0>;
752 752
753 pd_dma1_chan9: PD_SAI_4_TX { 753 pd_dma1_chan9: PD_SAI_4_TX {
754 reg = <SC_R_DMA_1_CH9>; 754 reg = <SC_R_DMA_1_CH9>;
755 power-domains =<&pd_dma1_chan8>; 755 power-domains =<&pd_dma1_chan8>;
756 #power-domain-cells = <0>; 756 #power-domain-cells = <0>;
757 #address-cells = <1>; 757 #address-cells = <1>;
758 #size-cells = <0>; 758 #size-cells = <0>;
759 759
760 pd_sai4: PD_AUD_SAI_4 { 760 pd_sai4: PD_AUD_SAI_4 {
761 reg = <SC_R_SAI_4>; 761 reg = <SC_R_SAI_4>;
762 #power-domain-cells = <0>; 762 #power-domain-cells = <0>;
763 power-domains =<&pd_dma1_chan9>; 763 power-domains =<&pd_dma1_chan9>;
764 764
765 }; 765 };
766 }; 766 };
767 }; 767 };
768 pd_dma1_chan10: PD_SAI_5_TX { 768 pd_dma1_chan10: PD_SAI_5_TX {
769 reg = <SC_R_DMA_1_CH10>; 769 reg = <SC_R_DMA_1_CH10>;
770 power-domains =<&pd_audio_clk1>; 770 power-domains =<&pd_audio_clk1>;
771 #power-domain-cells = <0>; 771 #power-domain-cells = <0>;
772 #address-cells = <1>; 772 #address-cells = <1>;
773 #size-cells = <0>; 773 #size-cells = <0>;
774 pd_sai5: PD_AUD_SAI_5 { 774 pd_sai5: PD_AUD_SAI_5 {
775 reg = <SC_R_SAI_5>; 775 reg = <SC_R_SAI_5>;
776 #power-domain-cells = <0>; 776 #power-domain-cells = <0>;
777 power-domains =<&pd_dma1_chan10>; 777 power-domains =<&pd_dma1_chan10>;
778 }; 778 };
779 }; 779 };
780 pd_gpt5: PD_AUD_GPT_5 { 780 pd_gpt5: PD_AUD_GPT_5 {
781 reg = <SC_R_GPT_5>; 781 reg = <SC_R_GPT_5>;
782 #power-domain-cells = <0>; 782 #power-domain-cells = <0>;
783 power-domains =<&pd_audio_clk1>; 783 power-domains =<&pd_audio_clk1>;
784 }; 784 };
785 pd_gpt6: PD_AUD_GPT_6 { 785 pd_gpt6: PD_AUD_GPT_6 {
786 reg = <SC_R_GPT_6>; 786 reg = <SC_R_GPT_6>;
787 #power-domain-cells = <0>; 787 #power-domain-cells = <0>;
788 power-domains =<&pd_audio_clk1>; 788 power-domains =<&pd_audio_clk1>;
789 }; 789 };
790 pd_gpt7: PD_AUD_GPT_7 { 790 pd_gpt7: PD_AUD_GPT_7 {
791 reg = <SC_R_GPT_7>; 791 reg = <SC_R_GPT_7>;
792 #power-domain-cells = <0>; 792 #power-domain-cells = <0>;
793 power-domains =<&pd_audio_clk1>; 793 power-domains =<&pd_audio_clk1>;
794 }; 794 };
795 pd_gpt8: PD_AUD_GPT_8 { 795 pd_gpt8: PD_AUD_GPT_8 {
796 reg = <SC_R_GPT_8>; 796 reg = <SC_R_GPT_8>;
797 #power-domain-cells = <0>; 797 #power-domain-cells = <0>;
798 power-domains =<&pd_audio_clk1>; 798 power-domains =<&pd_audio_clk1>;
799 }; 799 };
800 pd_gpt9: PD_AUD_GPT_9 { 800 pd_gpt9: PD_AUD_GPT_9 {
801 reg = <SC_R_GPT_9>; 801 reg = <SC_R_GPT_9>;
802 #power-domain-cells = <0>; 802 #power-domain-cells = <0>;
803 power-domains =<&pd_audio_clk1>; 803 power-domains =<&pd_audio_clk1>;
804 }; 804 };
805 pd_gpt10: PD_AUD_GPT_10 { 805 pd_gpt10: PD_AUD_GPT_10 {
806 reg = <SC_R_GPT_10>; 806 reg = <SC_R_GPT_10>;
807 #power-domain-cells = <0>; 807 #power-domain-cells = <0>;
808 power-domains =<&pd_audio_clk1>; 808 power-domains =<&pd_audio_clk1>;
809 }; 809 };
810 pd_amix: PD_AUD_AMIX { 810 pd_amix: PD_AUD_AMIX {
811 reg = <SC_R_AMIX>; 811 reg = <SC_R_AMIX>;
812 #power-domain-cells = <0>; 812 #power-domain-cells = <0>;
813 power-domains =<&pd_audio_clk1>; 813 power-domains =<&pd_audio_clk1>;
814 }; 814 };
815 pd_mqs0: PD_AUD_MQS_0 { 815 pd_mqs0: PD_AUD_MQS_0 {
816 reg = <SC_R_MQS_0>; 816 reg = <SC_R_MQS_0>;
817 #power-domain-cells = <0>; 817 #power-domain-cells = <0>;
818 power-domains =<&pd_audio_clk1>; 818 power-domains =<&pd_audio_clk1>;
819 }; 819 };
820 pd_mclk_out0: PD_AUD_MCLK_OUT_0 { 820 pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
821 reg = <SC_R_MCLK_OUT_0>; 821 reg = <SC_R_MCLK_OUT_0>;
822 #power-domain-cells = <0>; 822 #power-domain-cells = <0>;
823 power-domains =<&pd_audio_clk1>; 823 power-domains =<&pd_audio_clk1>;
824 }; 824 };
825 pd_mclk_out1: PD_AUD_MCLK_OUT_1 { 825 pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
826 reg = <SC_R_MCLK_OUT_1>; 826 reg = <SC_R_MCLK_OUT_1>;
827 #power-domain-cells = <0>; 827 #power-domain-cells = <0>;
828 power-domains =<&pd_audio_clk1>; 828 power-domains =<&pd_audio_clk1>;
829 }; 829 };
830 }; 830 };
831 }; 831 };
832 }; 832 };
833 }; 833 };
834 834
835 pd_dsp_mu_A: PD_DSP_MU_A { 835 pd_dsp_mu_A: PD_DSP_MU_A {
836 reg = <SC_R_MU_13A>; 836 reg = <SC_R_MU_13A>;
837 #power-domain-cells = <0>; 837 #power-domain-cells = <0>;
838 power-domains =<&pd_audio>; 838 power-domains =<&pd_audio>;
839 #address-cells = <1>; 839 #address-cells = <1>;
840 #size-cells = <0>; 840 #size-cells = <0>;
841 841
842 pd_dsp_mu_B: PD_DSP_MU_B { 842 pd_dsp_mu_B: PD_DSP_MU_B {
843 reg = <SC_R_MU_13B>; 843 reg = <SC_R_MU_13B>;
844 #power-domain-cells = <0>; 844 #power-domain-cells = <0>;
845 power-domains =<&pd_dsp_mu_A>; 845 power-domains =<&pd_dsp_mu_A>;
846 #address-cells = <1>; 846 #address-cells = <1>;
847 #size-cells = <0>; 847 #size-cells = <0>;
848 848
849 pd_dsp_ram: PD_AUD_OCRAM { 849 pd_dsp_ram: PD_AUD_OCRAM {
850 reg = <SC_R_DSP_RAM>; 850 reg = <SC_R_DSP_RAM>;
851 #power-domain-cells = <0>; 851 #power-domain-cells = <0>;
852 power-domains =<&pd_dsp_mu_B>; 852 power-domains =<&pd_dsp_mu_B>;
853 #address-cells = <1>; 853 #address-cells = <1>;
854 #size-cells = <0>; 854 #size-cells = <0>;
855 pd_dsp: PD_AUD_DSP { 855 pd_dsp: PD_AUD_DSP {
856 reg = <SC_R_DSP>; 856 reg = <SC_R_DSP>;
857 #power-domain-cells = <0>; 857 #power-domain-cells = <0>;
858 power-domains =<&pd_dsp_ram>; 858 power-domains =<&pd_dsp_ram>;
859 }; 859 };
860 }; 860 };
861 }; 861 };
862 }; 862 };
863 }; 863 };
864 864
865 pd_dma: PD_DMA { 865 pd_dma: PD_DMA {
866 compatible = "nxp,imx8-pd"; 866 compatible = "nxp,imx8-pd";
867 reg = <SC_R_NONE>; 867 reg = <SC_R_NONE>;
868 #power-domain-cells = <0>; 868 #power-domain-cells = <0>;
869 #address-cells = <1>; 869 #address-cells = <1>;
870 #size-cells = <0>; 870 #size-cells = <0>;
871 871
872 pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { 872 pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
873 reg = <SC_R_ELCDIF_PLL>; 873 reg = <SC_R_ELCDIF_PLL>;
874 #power-domain-cells = <0>; 874 #power-domain-cells = <0>;
875 power-domains = <&pd_dma>; 875 power-domains = <&pd_dma>;
876 #address-cells = <1>; 876 #address-cells = <1>;
877 #size-cells = <0>; 877 #size-cells = <0>;
878 878
879 pd_dma_lcd0: PD_DMA_LCD_0 { 879 pd_dma_lcd0: PD_DMA_LCD_0 {
880 reg = <SC_R_LCD_0>; 880 reg = <SC_R_LCD_0>;
881 #power-domain-cells = <0>; 881 #power-domain-cells = <0>;
882 power-domains = <&pd_dma_elcdif_pll>; 882 power-domains = <&pd_dma_elcdif_pll>;
883 }; 883 };
884 }; 884 };
885 pd_dma_flexcan0: PD_DMA_CAN_0 { 885 pd_dma_flexcan0: PD_DMA_CAN_0 {
886 reg = <SC_R_CAN_0>; 886 reg = <SC_R_CAN_0>;
887 #power-domain-cells = <0>; 887 #power-domain-cells = <0>;
888 power-domains = <&pd_dma>; 888 power-domains = <&pd_dma>;
889 wakeup-irq = <235>; 889 wakeup-irq = <235>;
890 #address-cells = <1>; 890 #address-cells = <1>;
891 #size-cells = <0>; 891 #size-cells = <0>;
892 892
893 pd_dma_flexcan1: PD_DMA_CAN_1 { 893 pd_dma_flexcan1: PD_DMA_CAN_1 {
894 reg = <SC_R_CAN_1>; 894 reg = <SC_R_CAN_1>;
895 #power-domain-cells = <0>; 895 #power-domain-cells = <0>;
896 power-domains = <&pd_dma_flexcan0>; 896 power-domains = <&pd_dma_flexcan0>;
897 wakeup-irq = <236>; 897 wakeup-irq = <236>;
898 }; 898 };
899 899
900 pd_dma_flexcan2: PD_DMA_CAN_2 { 900 pd_dma_flexcan2: PD_DMA_CAN_2 {
901 reg = <SC_R_CAN_2>; 901 reg = <SC_R_CAN_2>;
902 #power-domain-cells = <0>; 902 #power-domain-cells = <0>;
903 power-domains = <&pd_dma_flexcan0>; 903 power-domains = <&pd_dma_flexcan0>;
904 wakeup-irq = <237>; 904 wakeup-irq = <237>;
905 }; 905 };
906 }; 906 };
907 907
908 pd_dma_ftm0: PD_DMA_FTM_0 { 908 pd_dma_ftm0: PD_DMA_FTM_0 {
909 reg = <SC_R_FTM_0>; 909 reg = <SC_R_FTM_0>;
910 #power-domain-cells = <0>; 910 #power-domain-cells = <0>;
911 power-domains = <&pd_dma>; 911 power-domains = <&pd_dma>;
912 }; 912 };
913 pd_dma_ftm1: PD_DMA_FTM_1 { 913 pd_dma_ftm1: PD_DMA_FTM_1 {
914 reg = <SC_R_FTM_1>; 914 reg = <SC_R_FTM_1>;
915 #power-domain-cells = <0>; 915 #power-domain-cells = <0>;
916 power-domains = <&pd_dma>; 916 power-domains = <&pd_dma>;
917 }; 917 };
918 pd_dma_adc0: PD_DMA_ADC_0 { 918 pd_dma_adc0: PD_DMA_ADC_0 {
919 reg = <SC_R_ADC_0>; 919 reg = <SC_R_ADC_0>;
920 #power-domain-cells = <0>; 920 #power-domain-cells = <0>;
921 power-domains = <&pd_dma>; 921 power-domains = <&pd_dma>;
922 }; 922 };
923 pd_dma_lpi2c0: PD_DMA_I2C_0 { 923 pd_dma_lpi2c0: PD_DMA_I2C_0 {
924 reg = <SC_R_I2C_0>; 924 reg = <SC_R_I2C_0>;
925 #power-domain-cells = <0>; 925 #power-domain-cells = <0>;
926 power-domains = <&pd_dma>; 926 power-domains = <&pd_dma>;
927 }; 927 };
928 pd_dma_lpi2c1: PD_DMA_I2C_1 { 928 pd_dma_lpi2c1: PD_DMA_I2C_1 {
929 reg = <SC_R_I2C_1>; 929 reg = <SC_R_I2C_1>;
930 #power-domain-cells = <0>; 930 #power-domain-cells = <0>;
931 power-domains = <&pd_dma>; 931 power-domains = <&pd_dma>;
932 }; 932 };
933 pd_dma_lpi2c2:PD_DMA_I2C_2 { 933 pd_dma_lpi2c2:PD_DMA_I2C_2 {
934 reg = <SC_R_I2C_2>; 934 reg = <SC_R_I2C_2>;
935 #power-domain-cells = <0>; 935 #power-domain-cells = <0>;
936 power-domains = <&pd_dma>; 936 power-domains = <&pd_dma>;
937 }; 937 };
938 pd_dma_lpi2c3: PD_DMA_I2C_3 { 938 pd_dma_lpi2c3: PD_DMA_I2C_3 {
939 reg = <SC_R_I2C_3>; 939 reg = <SC_R_I2C_3>;
940 #power-domain-cells = <0>; 940 #power-domain-cells = <0>;
941 power-domains = <&pd_dma>; 941 power-domains = <&pd_dma>;
942 }; 942 };
943 pd_dma_lpuart0: PD_DMA_UART0 { 943 pd_dma_lpuart0: PD_DMA_UART0 {
944 reg = <SC_R_UART_0>; 944 reg = <SC_R_UART_0>;
945 #power-domain-cells = <0>; 945 #power-domain-cells = <0>;
946 power-domains = <&pd_dma>; 946 power-domains = <&pd_dma>;
947 wakeup-irq = <345>; 947 wakeup-irq = <345>;
948 }; 948 };
949 pd_dma_lpuart1: PD_DMA_UART1 { 949 pd_dma_lpuart1: PD_DMA_UART1 {
950 reg = <SC_R_UART_1>; 950 reg = <SC_R_UART_1>;
951 #power-domain-cells = <0>; 951 #power-domain-cells = <0>;
952 power-domains = <&pd_dma>; 952 power-domains = <&pd_dma>;
953 #address-cells = <1>; 953 #address-cells = <1>;
954 #size-cells = <0>; 954 #size-cells = <0>;
955 wakeup-irq = <346>; 955 wakeup-irq = <346>;
956 956
957 pd_dma2_chan10: PD_UART1_RX { 957 pd_dma2_chan10: PD_UART1_RX {
958 reg = <SC_R_DMA_2_CH10>; 958 reg = <SC_R_DMA_2_CH10>;
959 power-domains =<&pd_dma_lpuart1>; 959 power-domains =<&pd_dma_lpuart1>;
960 #power-domain-cells = <0>; 960 #power-domain-cells = <0>;
961 #address-cells = <1>; 961 #address-cells = <1>;
962 #size-cells = <0>; 962 #size-cells = <0>;
963 963
964 pd_dma2_chan11: PD_UART1_TX { 964 pd_dma2_chan11: PD_UART1_TX {
965 reg = <SC_R_DMA_2_CH11>; 965 reg = <SC_R_DMA_2_CH11>;
966 power-domains =<&pd_dma2_chan10>; 966 power-domains =<&pd_dma2_chan10>;
967 #power-domain-cells = <0>; 967 #power-domain-cells = <0>;
968 #address-cells = <1>; 968 #address-cells = <1>;
969 #size-cells = <0>; 969 #size-cells = <0>;
970 }; 970 };
971 }; 971 };
972 }; 972 };
973 pd_dma_lpuart2: PD_DMA_UART2 { 973 pd_dma_lpuart2: PD_DMA_UART2 {
974 reg = <SC_R_UART_2>; 974 reg = <SC_R_UART_2>;
975 #power-domain-cells = <0>; 975 #power-domain-cells = <0>;
976 power-domains = <&pd_dma>; 976 power-domains = <&pd_dma>;
977 #address-cells = <1>; 977 #address-cells = <1>;
978 #size-cells = <0>; 978 #size-cells = <0>;
979 wakeup-irq = <347>; 979 wakeup-irq = <347>;
980 980
981 pd_dma2_chan12: PD_UART2_RX { 981 pd_dma2_chan12: PD_UART2_RX {
982 reg = <SC_R_DMA_2_CH12>; 982 reg = <SC_R_DMA_2_CH12>;
983 power-domains =<&pd_dma_lpuart2>; 983 power-domains =<&pd_dma_lpuart2>;
984 #power-domain-cells = <0>; 984 #power-domain-cells = <0>;
985 #address-cells = <1>; 985 #address-cells = <1>;
986 #size-cells = <0>; 986 #size-cells = <0>;
987 987
988 pd_dma2_chan13: PD_UART2_TX { 988 pd_dma2_chan13: PD_UART2_TX {
989 reg = <SC_R_DMA_2_CH13>; 989 reg = <SC_R_DMA_2_CH13>;
990 power-domains =<&pd_dma2_chan12>; 990 power-domains =<&pd_dma2_chan12>;
991 #power-domain-cells = <0>; 991 #power-domain-cells = <0>;
992 #address-cells = <1>; 992 #address-cells = <1>;
993 #size-cells = <0>; 993 #size-cells = <0>;
994 }; 994 };
995 }; 995 };
996 }; 996 };
997 pd_dma_lpuart3: PD_DMA_UART3 { 997 pd_dma_lpuart3: PD_DMA_UART3 {
998 reg = <SC_R_UART_3>; 998 reg = <SC_R_UART_3>;
999 #power-domain-cells = <0>; 999 #power-domain-cells = <0>;
1000 power-domains = <&pd_dma>; 1000 power-domains = <&pd_dma>;
1001 #address-cells = <1>; 1001 #address-cells = <1>;
1002 #size-cells = <0>; 1002 #size-cells = <0>;
1003 wakeup-irq = <348>; 1003 wakeup-irq = <348>;
1004 1004
1005 pd_dma3_chan14: PD_UART3_RX { 1005 pd_dma3_chan14: PD_UART3_RX {
1006 reg = <SC_R_DMA_2_CH14>; 1006 reg = <SC_R_DMA_2_CH14>;
1007 power-domains =<&pd_dma_lpuart3>; 1007 power-domains =<&pd_dma_lpuart3>;
1008 #power-domain-cells = <0>; 1008 #power-domain-cells = <0>;
1009 #address-cells = <1>; 1009 #address-cells = <1>;
1010 #size-cells = <0>; 1010 #size-cells = <0>;
1011 1011
1012 pd_dma3_chan15: PD_UART3_TX { 1012 pd_dma3_chan15: PD_UART3_TX {
1013 reg = <SC_R_DMA_2_CH15>; 1013 reg = <SC_R_DMA_2_CH15>;
1014 power-domains =<&pd_dma3_chan14>; 1014 power-domains =<&pd_dma3_chan14>;
1015 #power-domain-cells = <0>; 1015 #power-domain-cells = <0>;
1016 #address-cells = <1>; 1016 #address-cells = <1>;
1017 #size-cells = <0>; 1017 #size-cells = <0>;
1018 }; 1018 };
1019 }; 1019 };
1020 }; 1020 };
1021 pd_dma_lpspi0: PD_DMA_SPI_0 { 1021 pd_dma_lpspi0: PD_DMA_SPI_0 {
1022 reg = <SC_R_SPI_0>; 1022 reg = <SC_R_SPI_0>;
1023 #power-domain-cells = <0>; 1023 #power-domain-cells = <0>;
1024 power-domains = <&pd_dma>; 1024 power-domains = <&pd_dma>;
1025 }; 1025 };
1026 pd_dma_lpspi1: PD_DMA_SPI_1 { 1026 pd_dma_lpspi1: PD_DMA_SPI_1 {
1027 reg = <SC_R_SPI_1>; 1027 reg = <SC_R_SPI_1>;
1028 #power-domain-cells = <0>; 1028 #power-domain-cells = <0>;
1029 power-domains = <&pd_dma>; 1029 power-domains = <&pd_dma>;
1030 }; 1030 };
1031 pd_dma_lpspi2: PD_DMA_SPI_2 { 1031 pd_dma_lpspi2: PD_DMA_SPI_2 {
1032 reg = <SC_R_SPI_2>; 1032 reg = <SC_R_SPI_2>;
1033 #power-domain-cells = <0>; 1033 #power-domain-cells = <0>;
1034 power-domains = <&pd_dma>; 1034 power-domains = <&pd_dma>;
1035 }; 1035 };
1036 pd_dma_lpspi3: PD_DMA_SPI_3 { 1036 pd_dma_lpspi3: PD_DMA_SPI_3 {
1037 reg = <SC_R_SPI_3>; 1037 reg = <SC_R_SPI_3>;
1038 #power-domain-cells = <0>; 1038 #power-domain-cells = <0>;
1039 power-domains = <&pd_dma>; 1039 power-domains = <&pd_dma>;
1040 }; 1040 };
1041 pd_dma_pwm0: PD_DMA_PWM_0 { 1041 pd_dma_pwm0: PD_DMA_PWM_0 {
1042 reg = <SC_R_LCD_0_PWM_0>; 1042 reg = <SC_R_LCD_0_PWM_0>;
1043 #power-domain-cells = <0>; 1043 #power-domain-cells = <0>;
1044 power-domains = <&pd_dma>; 1044 power-domains = <&pd_dma>;
1045 }; 1045 };
1046 }; 1046 };
1047 1047
1048 pd_gpu: gpu-power-domain { 1048 pd_gpu: gpu-power-domain {
1049 compatible = "nxp,imx8-pd"; 1049 compatible = "nxp,imx8-pd";
1050 reg = <SC_R_NONE>; 1050 reg = <SC_R_NONE>;
1051 #power-domain-cells = <0>; 1051 #power-domain-cells = <0>;
1052 #address-cells = <1>; 1052 #address-cells = <1>;
1053 #size-cells = <0>; 1053 #size-cells = <0>;
1054 1054
1055 pd_gpu0: gpu0 { 1055 pd_gpu0: gpu0 {
1056 name = "gpu0"; 1056 name = "gpu0";
1057 reg = <SC_R_GPU_0_PID0>; 1057 reg = <SC_R_GPU_0_PID0>;
1058 #power-domain-cells = <0>; 1058 #power-domain-cells = <0>;
1059 power-domains =<&pd_gpu>; 1059 power-domains =<&pd_gpu>;
1060 #address-cells = <1>; 1060 #address-cells = <1>;
1061 #size-cells = <0>; 1061 #size-cells = <0>;
1062 }; 1062 };
1063 }; 1063 };
1064 1064
1065 pd_vpu: vpu-power-domain { 1065 pd_vpu: vpu-power-domain {
1066 compatible = "nxp,imx8-pd"; 1066 compatible = "nxp,imx8-pd";
1067 reg = <SC_R_VPU>; 1067 reg = <SC_R_VPU>;
1068 #power-domain-cells = <0>; 1068 #power-domain-cells = <0>;
1069 #address-cells = <1>; 1069 #address-cells = <1>;
1070 #size-cells = <0>; 1070 #size-cells = <0>;
1071 1071
1072 pd_vpu_mu_enc: VPU_ENC_MU { 1072 pd_vpu_mu_enc: VPU_ENC_MU {
1073 reg = <SC_R_VPU_MU_1>; 1073 reg = <SC_R_VPU_MU_1>;
1074 #power-domain-cells = <0>; 1074 #power-domain-cells = <0>;
1075 power-domains =<&pd_vpu>; 1075 power-domains =<&pd_vpu>;
1076 #address-cells = <1>; 1076 #address-cells = <1>;
1077 #size-cells = <0>; 1077 #size-cells = <0>;
1078 1078
1079 pd_vpu_enc: VPU_ENC { 1079 pd_vpu_enc: VPU_ENC {
1080 reg = <SC_R_VPU_ENC_0>; 1080 reg = <SC_R_VPU_ENC_0>;
1081 #power-domain-cells = <0>; 1081 #power-domain-cells = <0>;
1082 power-domains =<&pd_vpu_mu_enc>; 1082 power-domains =<&pd_vpu_mu_enc>;
1083 }; 1083 };
1084 }; 1084 };
1085 1085
1086 pd_vpu_mu_dec: VPU_DEC_MU { 1086 pd_vpu_mu_dec: VPU_DEC_MU {
1087 reg = <SC_R_VPU_MU_0>; 1087 reg = <SC_R_VPU_MU_0>;
1088 #power-domain-cells = <0>; 1088 #power-domain-cells = <0>;
1089 power-domains =<&pd_vpu>; 1089 power-domains =<&pd_vpu>;
1090 #address-cells = <1>; 1090 #address-cells = <1>;
1091 #size-cells = <0>; 1091 #size-cells = <0>;
1092 1092
1093 pd_vpu_dec: VPU_DEC { 1093 pd_vpu_dec: VPU_DEC {
1094 reg = <SC_R_VPU_DEC_0>; 1094 reg = <SC_R_VPU_DEC_0>;
1095 #power-domain-cells = <0>; 1095 #power-domain-cells = <0>;
1096 power-domains =<&pd_vpu_mu_dec>; 1096 power-domains =<&pd_vpu_mu_dec>;
1097 }; 1097 };
1098 }; 1098 };
1099 }; 1099 };
1100 1100
1101 pd_hsio: hsio-power-domain { 1101 pd_hsio: hsio-power-domain {
1102 compatible = "nxp,imx8-pd"; 1102 compatible = "nxp,imx8-pd";
1103 reg = <SC_R_NONE>; 1103 reg = <SC_R_NONE>;
1104 #power-domain-cells = <0>; 1104 #power-domain-cells = <0>;
1105 #address-cells = <1>; 1105 #address-cells = <1>;
1106 #size-cells = <0>; 1106 #size-cells = <0>;
1107 1107
1108 pd_hsio_gpio: PD_HSIO_GPIO { 1108 pd_hsio_gpio: PD_HSIO_GPIO {
1109 reg = <SC_R_HSIO_GPIO>; 1109 reg = <SC_R_HSIO_GPIO>;
1110 #power-domain-cells = <0>; 1110 #power-domain-cells = <0>;
1111 power-domains =<&pd_hsio>; 1111 power-domains =<&pd_hsio>;
1112 #address-cells = <1>; 1112 #address-cells = <1>;
1113 #size-cells = <0>; 1113 #size-cells = <0>;
1114 1114
1115 pd_serdes1: PD_HSIO_SERDES_1 { 1115 pd_serdes1: PD_HSIO_SERDES_1 {
1116 reg = <SC_R_SERDES_1>; 1116 reg = <SC_R_SERDES_1>;
1117 #power-domain-cells = <0>; 1117 #power-domain-cells = <0>;
1118 power-domains =<&pd_hsio_gpio>; 1118 power-domains =<&pd_hsio_gpio>;
1119 #address-cells = <1>; 1119 #address-cells = <1>;
1120 #size-cells = <0>; 1120 #size-cells = <0>;
1121 1121
1122 pd_pcie: PD_HSIO_PCIE_B { 1122 pd_pcie: PD_HSIO_PCIE_B {
1123 reg = <SC_R_PCIE_B>; 1123 reg = <SC_R_PCIE_B>;
1124 #power-domain-cells = <0>; 1124 #power-domain-cells = <0>;
1125 power-domains =<&pd_serdes1>; 1125 power-domains =<&pd_serdes1>;
1126 }; 1126 };
1127 }; 1127 };
1128 }; 1128 };
1129 }; 1129 };
1130 1130
1131 pd_cm40: PD_CM40 { 1131 pd_cm40: PD_CM40 {
1132 compatible = "nxp,imx8-pd"; 1132 compatible = "nxp,imx8-pd";
1133 reg = <SC_R_NONE>; 1133 reg = <SC_R_NONE>;
1134 #power-domain-cells = <0>; 1134 #power-domain-cells = <0>;
1135 #address-cells = <1>; 1135 #address-cells = <1>;
1136 #size-cells = <0>; 1136 #size-cells = <0>;
1137 1137
1138 pd_cm40_i2c: PD_CM40_I2C { 1138 pd_cm40_i2c: PD_CM40_I2C {
1139 reg = <SC_R_M4_0_I2C>; 1139 reg = <SC_R_M4_0_I2C>;
1140 #power-domain-cells = <0>; 1140 #power-domain-cells = <0>;
1141 power-domains =<&pd_cm40>; 1141 power-domains =<&pd_cm40>;
1142 }; 1142 };
1143 1143
1144 pd_cm40_intmux: PD_CM40_INTMUX { 1144 pd_cm40_intmux: PD_CM40_INTMUX {
1145 reg = <SC_R_M4_0_INTMUX>; 1145 reg = <SC_R_M4_0_INTMUX>;
1146 #power-domain-cells = <0>; 1146 #power-domain-cells = <0>;
1147 power-domains =<&pd_cm40>; 1147 power-domains =<&pd_cm40>;
1148 }; 1148 };
1149 }; 1149 };
1150 1150
1151 1151
1152 pd_dc0: PD_DC_0 { 1152 pd_dc0: PD_DC_0 {
1153 compatible = "nxp,imx8-pd"; 1153 compatible = "nxp,imx8-pd";
1154 reg = <SC_R_DC_0>; 1154 reg = <SC_R_DC_0>;
1155 #power-domain-cells = <0>; 1155 #power-domain-cells = <0>;
1156 #address-cells = <1>; 1156 #address-cells = <1>;
1157 #size-cells = <0>; 1157 #size-cells = <0>;
1158 1158
1159 pd_dc0_pll0: PD_DC_0_PLL_0{ 1159 pd_dc0_pll0: PD_DC_0_PLL_0{
1160 reg = <SC_R_DC_0_PLL_0>; 1160 reg = <SC_R_DC_0_PLL_0>;
1161 #power-domain-cells = <0>; 1161 #power-domain-cells = <0>;
1162 power-domains =<&pd_dc0>; 1162 power-domains =<&pd_dc0>;
1163 #address-cells = <1>; 1163 #address-cells = <1>;
1164 #size-cells = <0>; 1164 #size-cells = <0>;
1165 1165
1166 pd_dc0_pll1: PD_DC_0_PLL_1{ 1166 pd_dc0_pll1: PD_DC_0_PLL_1{
1167 reg = <SC_R_DC_0_PLL_1>; 1167 reg = <SC_R_DC_0_PLL_1>;
1168 #power-domain-cells = <0>; 1168 #power-domain-cells = <0>;
1169 power-domains =<&pd_dc0_pll0>; 1169 power-domains =<&pd_dc0_pll0>;
1170 }; 1170 };
1171 }; 1171 };
1172 pd_mipi_dsi0: PD_MIPI_0_DSI { 1172 pd_mipi_dsi0: PD_MIPI_0_DSI {
1173 reg = <SC_R_MIPI_0>; 1173 reg = <SC_R_MIPI_0>;
1174 #power-domain-cells = <0>; 1174 #power-domain-cells = <0>;
1175 power-domains =<&pd_dc0>; 1175 power-domains =<&pd_dc0>;
1176 #address-cells = <1>; 1176 #address-cells = <1>;
1177 #size-cells = <0>; 1177 #size-cells = <0>;
1178 1178
1179 pd_mipi_dsi_0_lvds: PD_LVDS0 { 1179 pd_mipi_dsi_0_lvds: PD_LVDS0 {
1180 reg = <SC_R_LVDS_0>; 1180 reg = <SC_R_LVDS_0>;
1181 #power-domain-cells = <0>; 1181 #power-domain-cells = <0>;
1182 power-domains =<&pd_mipi_dsi0>; 1182 power-domains =<&pd_mipi_dsi0>;
1183 }; 1183 };
1184 1184
1185 pd_mipi_dsi_0_aux_lvds: PD_AUX_LVDS0 { 1185 pd_mipi_dsi_0_aux_lvds: PD_AUX_LVDS0 {
1186 reg = <SC_R_LVDS_0>; 1186 reg = <SC_R_LVDS_0>;
1187 #power-domain-cells = <0>; 1187 #power-domain-cells = <0>;
1188 power-domains = <&pd_mipi_dsi0>; 1188 power-domains = <&pd_mipi_dsi0>;
1189 #address-cells = <1>; 1189 #address-cells = <1>;
1190 #size-cells = <0>; 1190 #size-cells = <0>;
1191 1191
1192 pd_mipi_dsi_1_dual_lvds: PD_DUAL_LVDS1 { 1192 pd_mipi_dsi_1_dual_lvds: PD_DUAL_LVDS1 {
1193 reg = <SC_R_LVDS_1>; 1193 reg = <SC_R_LVDS_1>;
1194 #power-domain-cells = <0>; 1194 #power-domain-cells = <0>;
1195 power-domains = <&pd_mipi_dsi_0_aux_lvds>; 1195 power-domains = <&pd_mipi_dsi_0_aux_lvds>;
1196 }; 1196 };
1197 }; 1197 };
1198 1198
1199 pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { 1199 pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 {
1200 reg = <SC_R_MIPI_0_I2C_0>; 1200 reg = <SC_R_MIPI_0_I2C_0>;
1201 #power-domain-cells = <0>; 1201 #power-domain-cells = <0>;
1202 power-domains =<&pd_mipi_dsi0>; 1202 power-domains =<&pd_mipi_dsi0>;
1203 }; 1203 };
1204 pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { 1204 pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 {
1205 reg = <SC_R_MIPI_0_I2C_1>; 1205 reg = <SC_R_MIPI_0_I2C_1>;
1206 #power-domain-cells = <0>; 1206 #power-domain-cells = <0>;
1207 power-domains =<&pd_mipi_dsi0>; 1207 power-domains =<&pd_mipi_dsi0>;
1208 }; 1208 };
1209 pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { 1209 pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 {
1210 reg = <SC_R_MIPI_0_PWM_0>; 1210 reg = <SC_R_MIPI_0_PWM_0>;
1211 #power-domain-cells = <0>; 1211 #power-domain-cells = <0>;
1212 power-domains =<&pd_mipi_dsi0>; 1212 power-domains =<&pd_mipi_dsi0>;
1213 }; 1213 };
1214 }; 1214 };
1215 1215
1216 pd_mipi_dsi1: PD_MIPI_1_DSI { 1216 pd_mipi_dsi1: PD_MIPI_1_DSI {
1217 reg = <SC_R_MIPI_1>; 1217 reg = <SC_R_MIPI_1>;
1218 #power-domain-cells = <0>; 1218 #power-domain-cells = <0>;
1219 power-domains =<&pd_dc0>; 1219 power-domains =<&pd_dc0>;
1220 #address-cells = <1>; 1220 #address-cells = <1>;
1221 #size-cells = <0>; 1221 #size-cells = <0>;
1222 1222
1223 pd_mipi_dsi_1_lvds: PD_LVDS1 { 1223 pd_mipi_dsi_1_lvds: PD_LVDS1 {
1224 reg = <SC_R_LVDS_1>; 1224 reg = <SC_R_LVDS_1>;
1225 #power-domain-cells = <0>; 1225 #power-domain-cells = <0>;
1226 power-domains =<&pd_mipi_dsi1>; 1226 power-domains =<&pd_mipi_dsi1>;
1227 }; 1227 };
1228 1228
1229 pd_mipi_dsi_1_aux_lvds: PD_AUX_LVDS1 { 1229 pd_mipi_dsi_1_aux_lvds: PD_AUX_LVDS1 {
1230 reg = <SC_R_LVDS_1>; 1230 reg = <SC_R_LVDS_1>;
1231 #power-domain-cells = <0>; 1231 #power-domain-cells = <0>;
1232 power-domains = <&pd_mipi_dsi1>; 1232 power-domains = <&pd_mipi_dsi1>;
1233 #address-cells = <1>; 1233 #address-cells = <1>;
1234 #size-cells = <0>; 1234 #size-cells = <0>;
1235 1235
1236 pd_mipi_dsi_0_dual_lvds: PD_DUAL_LVDS0 { 1236 pd_mipi_dsi_0_dual_lvds: PD_DUAL_LVDS0 {
1237 reg = <SC_R_LVDS_0>; 1237 reg = <SC_R_LVDS_0>;
1238 #power-domain-cells = <0>; 1238 #power-domain-cells = <0>;
1239 power-domains = <&pd_mipi_dsi_1_aux_lvds>; 1239 power-domains = <&pd_mipi_dsi_1_aux_lvds>;
1240 }; 1240 };
1241 }; 1241 };
1242 1242
1243 pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { 1243 pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 {
1244 reg = <SC_R_MIPI_1_I2C_0>; 1244 reg = <SC_R_MIPI_1_I2C_0>;
1245 #power-domain-cells = <0>; 1245 #power-domain-cells = <0>;
1246 power-domains =<&pd_mipi_dsi1>; 1246 power-domains =<&pd_mipi_dsi1>;
1247 }; 1247 };
1248 pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { 1248 pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 {
1249 reg = <SC_R_MIPI_1_I2C_1>; 1249 reg = <SC_R_MIPI_1_I2C_1>;
1250 #power-domain-cells = <0>; 1250 #power-domain-cells = <0>;
1251 power-domains =<&pd_mipi_dsi1>; 1251 power-domains =<&pd_mipi_dsi1>;
1252 }; 1252 };
1253 pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { 1253 pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 {
1254 reg = <SC_R_MIPI_1_PWM_0>; 1254 reg = <SC_R_MIPI_1_PWM_0>;
1255 #power-domain-cells = <0>; 1255 #power-domain-cells = <0>;
1256 power-domains =<&pd_mipi_dsi1>; 1256 power-domains =<&pd_mipi_dsi1>;
1257 }; 1257 };
1258 }; 1258 };
1259 }; 1259 };
1260 1260
1261 pd_isi_ch0: PD_IMAGING { 1261 pd_isi_ch0: PD_IMAGING {
1262 compatible = "nxp,imx8-pd"; 1262 compatible = "nxp,imx8-pd";
1263 reg = <SC_R_ISI_CH0>; 1263 reg = <SC_R_ISI_CH0>;
1264 #power-domain-cells = <0>; 1264 #power-domain-cells = <0>;
1265 #address-cells = <1>; 1265 #address-cells = <1>;
1266 #size-cells = <0>; 1266 #size-cells = <0>;
1267 1267
1268 pd_mipi_csi: PD_MIPI_CSI0 { 1268 pd_mipi_csi: PD_MIPI_CSI0 {
1269 reg = <SC_R_CSI_0>; 1269 reg = <SC_R_CSI_0>;
1270 #power-domain-cells = <0>; 1270 #power-domain-cells = <0>;
1271 #address-cells = <1>; 1271 #address-cells = <1>;
1272 #size-cells = <0>; 1272 #size-cells = <0>;
1273 power-domains =<&pd_isi_ch0>; 1273 power-domains =<&pd_isi_ch0>;
1274 1274
1275 pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C0 { 1275 pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C0 {
1276 reg = <SC_R_CSI_0_I2C_0>; 1276 reg = <SC_R_CSI_0_I2C_0>;
1277 #power-domain-cells = <0>; 1277 #power-domain-cells = <0>;
1278 power-domains =<&pd_mipi_csi>; 1278 power-domains =<&pd_mipi_csi>;
1279 }; 1279 };
1280 1280
1281 pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { 1281 pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM {
1282 name = "mipi_csi0_pwm"; 1282 name = "mipi_csi0_pwm";
1283 reg = <SC_R_CSI_0_PWM_0>; 1283 reg = <SC_R_CSI_0_PWM_0>;
1284 #power-domain-cells = <0>; 1284 #power-domain-cells = <0>;
1285 power-domains =<&pd_mipi_csi>; 1285 power-domains =<&pd_mipi_csi>;
1286 }; 1286 };
1287 }; 1287 };
1288 1288
1289 pd_parallel_csi: PD_PARALLEL_CSI { 1289 pd_parallel_csi: PD_PARALLEL_CSI {
1290 reg = <SC_R_PI_0>; 1290 reg = <SC_R_PI_0>;
1291 #power-domain-cells = <0>; 1291 #power-domain-cells = <0>;
1292 #address-cells = <1>; 1292 #address-cells = <1>;
1293 #size-cells = <0>; 1293 #size-cells = <0>;
1294 power-domains =<&pd_isi_ch0>; 1294 power-domains =<&pd_isi_ch0>;
1295 1295
1296 pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C { 1296 pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C {
1297 name = "parallel_csi_i2c"; 1297 name = "parallel_csi_i2c";
1298 reg = <SC_R_PI_0_I2C_0>; 1298 reg = <SC_R_PI_0_I2C_0>;
1299 #power-domain-cells = <0>; 1299 #power-domain-cells = <0>;
1300 power-domains =<&pd_parallel_csi>; 1300 power-domains =<&pd_parallel_csi>;
1301 }; 1301 };
1302 1302
1303 pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM { 1303 pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM {
1304 name = "parallel_csi_pwm"; 1304 name = "parallel_csi_pwm";
1305 reg = <SC_R_PI_0_PWM_0>; 1305 reg = <SC_R_PI_0_PWM_0>;
1306 #power-domain-cells = <0>; 1306 #power-domain-cells = <0>;
1307 power-domains =<&pd_parallel_csi>; 1307 power-domains =<&pd_parallel_csi>;
1308 }; 1308 };
1309 1309
1310 pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL { 1310 pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL {
1311 name = "parallel_csi_pll"; 1311 name = "parallel_csi_pll";
1312 reg = <SC_R_PI_0_PLL>; 1312 reg = <SC_R_PI_0_PLL>;
1313 #power-domain-cells = <0>; 1313 #power-domain-cells = <0>;
1314 power-domains =<&pd_parallel_csi>; 1314 power-domains =<&pd_parallel_csi>;
1315 }; 1315 };
1316 }; 1316 };
1317 1317
1318 pd_isi_ch1: PD_IMAGING_PDMA1 { 1318 pd_isi_ch1: PD_IMAGING_PDMA1 {
1319 reg = <SC_R_ISI_CH1>; 1319 reg = <SC_R_ISI_CH1>;
1320 #power-domain-cells = <0>; 1320 #power-domain-cells = <0>;
1321 power-domains =<&pd_isi_ch0>; 1321 power-domains =<&pd_isi_ch0>;
1322 }; 1322 };
1323 1323
1324 pd_isi_ch2: PD_IMAGING_PDMA2 { 1324 pd_isi_ch2: PD_IMAGING_PDMA2 {
1325 reg = <SC_R_ISI_CH2>; 1325 reg = <SC_R_ISI_CH2>;
1326 #power-domain-cells = <0>; 1326 #power-domain-cells = <0>;
1327 power-domains =<&pd_isi_ch0>; 1327 power-domains =<&pd_isi_ch0>;
1328 }; 1328 };
1329 1329
1330 pd_isi_ch3: PD_IMAGING_PDMA3 { 1330 pd_isi_ch3: PD_IMAGING_PDMA3 {
1331 reg = <SC_R_ISI_CH3>; 1331 reg = <SC_R_ISI_CH3>;
1332 #power-domain-cells = <0>; 1332 #power-domain-cells = <0>;
1333 power-domains =<&pd_isi_ch0>; 1333 power-domains =<&pd_isi_ch0>;
1334 }; 1334 };
1335 1335
1336 pd_isi_ch4: PD_IMAGING_PDMA4 { 1336 pd_isi_ch4: PD_IMAGING_PDMA4 {
1337 reg = <SC_R_ISI_CH4>; 1337 reg = <SC_R_ISI_CH4>;
1338 #power-domain-cells = <0>; 1338 #power-domain-cells = <0>;
1339 power-domains =<&pd_isi_ch0>; 1339 power-domains =<&pd_isi_ch0>;
1340 }; 1340 };
1341 1341
1342 pd_isi_ch5: PD_IMAGING_PDMA5 { 1342 pd_isi_ch5: PD_IMAGING_PDMA5 {
1343 reg = <SC_R_ISI_CH5>; 1343 reg = <SC_R_ISI_CH5>;
1344 #power-domain-cells = <0>; 1344 #power-domain-cells = <0>;
1345 power-domains =<&pd_isi_ch0>; 1345 power-domains =<&pd_isi_ch0>;
1346 }; 1346 };
1347 1347
1348 pd_isi_ch6: PD_IMAGING_PDMA6 { 1348 pd_isi_ch6: PD_IMAGING_PDMA6 {
1349 reg = <SC_R_ISI_CH6>; 1349 reg = <SC_R_ISI_CH6>;
1350 #power-domain-cells = <0>; 1350 #power-domain-cells = <0>;
1351 power-domains =<&pd_isi_ch0>; 1351 power-domains =<&pd_isi_ch0>;
1352 }; 1352 };
1353 1353
1354 pd_isi_ch7: PD_IMAGING_PDMA7 { 1354 pd_isi_ch7: PD_IMAGING_PDMA7 {
1355 reg = <SC_R_ISI_CH7>; 1355 reg = <SC_R_ISI_CH7>;
1356 #power-domain-cells = <0>; 1356 #power-domain-cells = <0>;
1357 power-domains =<&pd_isi_ch0>; 1357 power-domains =<&pd_isi_ch0>;
1358 }; 1358 };
1359 1359
1360 pd_jpeg_dec_mp: PD_JPEG_DEC_MP{ 1360 pd_jpeg_dec_mp: PD_JPEG_DEC_MP{
1361 reg = <SC_R_MJPEG_DEC_MP>; 1361 reg = <SC_R_MJPEG_DEC_MP>;
1362 #power-domain-cells = <0>; 1362 #power-domain-cells = <0>;
1363 power-domains =<&pd_isi_ch0>; 1363 power-domains =<&pd_isi_ch0>;
1364 #address-cells = <1>; 1364 #address-cells = <1>;
1365 #size-cells = <0>; 1365 #size-cells = <0>;
1366 1366
1367 pd_jpgdec: PD_IMAGING_JPEG_DEC { 1367 pd_jpgdec: PD_IMAGING_JPEG_DEC {
1368 reg = <SC_R_MJPEG_DEC_S0>; 1368 reg = <SC_R_MJPEG_DEC_S0>;
1369 #power-domain-cells = <0>; 1369 #power-domain-cells = <0>;
1370 power-domains =<&pd_jpeg_dec_mp>; 1370 power-domains =<&pd_jpeg_dec_mp>;
1371 }; 1371 };
1372 }; 1372 };
1373 1373
1374 pd_jpeg_enc_mp: PD_JPEG_ENC_MP{ 1374 pd_jpeg_enc_mp: PD_JPEG_ENC_MP{
1375 reg = <SC_R_MJPEG_ENC_MP>; 1375 reg = <SC_R_MJPEG_ENC_MP>;
1376 #power-domain-cells = <0>; 1376 #power-domain-cells = <0>;
1377 power-domains =<&pd_isi_ch0>; 1377 power-domains =<&pd_isi_ch0>;
1378 #address-cells = <1>; 1378 #address-cells = <1>;
1379 #size-cells = <0>; 1379 #size-cells = <0>;
1380 1380
1381 pd_jpgenc: PD_IMAGING_JPEG_ENC { 1381 pd_jpgenc: PD_IMAGING_JPEG_ENC {
1382 reg = <SC_R_MJPEG_ENC_S0>; 1382 reg = <SC_R_MJPEG_ENC_S0>;
1383 #power-domain-cells = <0>; 1383 #power-domain-cells = <0>;
1384 power-domains =<&pd_jpeg_enc_mp>; 1384 power-domains =<&pd_jpeg_enc_mp>;
1385 }; 1385 };
1386 }; 1386 };
1387 }; 1387 };
1388 pd_caam: PD_CAAM { 1388 pd_caam: PD_CAAM {
1389 compatible = "nxp,imx8-pd"; 1389 compatible = "nxp,imx8-pd";
1390 reg = <SC_R_NONE>; 1390 reg = <SC_R_NONE>;
1391 #power-domain-cells = <0>; 1391 #power-domain-cells = <0>;
1392 #address-cells = <1>; 1392 #address-cells = <1>;
1393 #size-cells = <0>; 1393 #size-cells = <0>;
1394 1394
1395 pd_caam_jr1: PD_CAAM_JR1 { 1395 pd_caam_jr1: PD_CAAM_JR1 {
1396 reg = <SC_R_CAAM_JR1>; 1396 reg = <SC_R_CAAM_JR1>;
1397 #power-domain-cells = <0>; 1397 #power-domain-cells = <0>;
1398 power-domains = <&pd_caam>; 1398 power-domains = <&pd_caam>;
1399 }; 1399 };
1400 pd_caam_jr2: PD_CAAM_JR2 { 1400 pd_caam_jr2: PD_CAAM_JR2 {
1401 reg = <SC_R_CAAM_JR2>; 1401 reg = <SC_R_CAAM_JR2>;
1402 #power-domain-cells = <0>; 1402 #power-domain-cells = <0>;
1403 power-domains = <&pd_caam>; 1403 power-domains = <&pd_caam>;
1404 }; 1404 };
1405 pd_caam_jr3: PD_CAAM_JR3 { 1405 pd_caam_jr3: PD_CAAM_JR3 {
1406 reg = <SC_R_CAAM_JR3>; 1406 reg = <SC_R_CAAM_JR3>;
1407 #power-domain-cells = <0>; 1407 #power-domain-cells = <0>;
1408 power-domains = <&pd_caam>; 1408 power-domains = <&pd_caam>;
1409 }; 1409 };
1410 }; 1410 };
1411 }; 1411 };
1412 1412
1413 tsens: thermal-sensor { 1413 tsens: thermal-sensor {
1414 compatible = "nxp,imx8qxp-sc-tsens"; 1414 compatible = "nxp,imx8qxp-sc-tsens";
1415 u-boot,dm-pre-reloc; 1415 u-boot,dm-pre-reloc;
1416 /* number of the temp sensor on the chip */ 1416 /* number of the temp sensor on the chip */
1417 tsens-num = <2>; 1417 tsens-num = <2>;
1418 #thermal-sensor-cells = <1>; 1418 #thermal-sensor-cells = <1>;
1419 }; 1419 };
1420 1420
1421 thermal_zones: thermal-zones { 1421 thermal_zones: thermal-zones {
1422 /* cpu thermal */ 1422 /* cpu thermal */
1423 cpu-thermal0 { 1423 cpu-thermal0 {
1424 polling-delay-passive = <250>; 1424 polling-delay-passive = <250>;
1425 polling-delay = <2000>; 1425 polling-delay = <2000>;
1426 /*the slope and offset of the temp sensor */ 1426 /*the slope and offset of the temp sensor */
1427 thermal-sensors = <&tsens 0>; 1427 thermal-sensors = <&tsens 0>;
1428 trips { 1428 trips {
1429 cpu_alert0: trip0 { 1429 cpu_alert0: trip0 {
1430 temperature = <107000>; 1430 temperature = <107000>;
1431 hysteresis = <2000>; 1431 hysteresis = <2000>;
1432 type = "passive"; 1432 type = "passive";
1433 }; 1433 };
1434 cpu_crit0: trip1 { 1434 cpu_crit0: trip1 {
1435 temperature = <127000>; 1435 temperature = <127000>;
1436 hysteresis = <2000>; 1436 hysteresis = <2000>;
1437 type = "critical"; 1437 type = "critical";
1438 }; 1438 };
1439 }; 1439 };
1440 cooling-maps { 1440 cooling-maps {
1441 map0 { 1441 map0 {
1442 trip = <&cpu_alert0>; 1442 trip = <&cpu_alert0>;
1443 cooling-device = 1443 cooling-device =
1444 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1444 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1445 }; 1445 };
1446 }; 1446 };
1447 }; 1447 };
1448 1448
1449 drc-thermal0 { 1449 drc-thermal0 {
1450 polling-delay-passive = <250>; 1450 polling-delay-passive = <250>;
1451 polling-delay = <2000>; 1451 polling-delay = <2000>;
1452 thermal-sensors = <&tsens 1>; 1452 thermal-sensors = <&tsens 1>;
1453 status = "disabled"; 1453 status = "disabled";
1454 trips { 1454 trips {
1455 drc_alert0: trip0 { 1455 drc_alert0: trip0 {
1456 temperature = <107000>; 1456 temperature = <107000>;
1457 hysteresis = <2000>; 1457 hysteresis = <2000>;
1458 type = "passive"; 1458 type = "passive";
1459 }; 1459 };
1460 drc_crit0: trip1 { 1460 drc_crit0: trip1 {
1461 temperature = <127000>; 1461 temperature = <127000>;
1462 hysteresis = <2000>; 1462 hysteresis = <2000>;
1463 type = "critical"; 1463 type = "critical";
1464 }; 1464 };
1465 }; 1465 };
1466 }; 1466 };
1467 }; 1467 };
1468 1468
1469 irqsteer_csi: irqsteer@58220000 { 1469 irqsteer_csi: irqsteer@58220000 {
1470 compatible = "nxp,imx-irqsteer"; 1470 compatible = "nxp,imx-irqsteer";
1471 reg = <0x0 0x58220000 0x0 0x1000>; 1471 reg = <0x0 0x58220000 0x0 0x1000>;
1472 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 1472 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
1473 interrupt-controller; 1473 interrupt-controller;
1474 interrupt-parent = <&gic>; 1474 interrupt-parent = <&gic>;
1475 #interrupt-cells = <2>; 1475 #interrupt-cells = <2>;
1476 clocks = <&clk IMX8QXP_CLK_DUMMY>; 1476 clocks = <&clk IMX8QXP_CLK_DUMMY>;
1477 clock-names = "ipg"; 1477 clock-names = "ipg";
1478 power-domains = <&pd_mipi_csi>; 1478 power-domains = <&pd_mipi_csi>;
1479 }; 1479 };
1480 1480
1481 i2c0_csi0: i2c@58226000 { 1481 i2c0_csi0: i2c@58226000 {
1482 compatible = "fsl,imx8qm-lpi2c"; 1482 compatible = "fsl,imx8qm-lpi2c";
1483 reg = <0x0 0x58226000 0x0 0x1000>; 1483 reg = <0x0 0x58226000 0x0 0x1000>;
1484 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1484 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1485 interrupt-parent = <&irqsteer_csi>; 1485 interrupt-parent = <&irqsteer_csi>;
1486 clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, 1486 clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>,
1487 <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; 1487 <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>;
1488 clock-names = "per", "ipg"; 1488 clock-names = "per", "ipg";
1489 assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; 1489 assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>;
1490 assigned-clock-rates = <24000000>; 1490 assigned-clock-rates = <24000000>;
1491 power-domains = <&pd_mipi_csi_i2c0>; 1491 power-domains = <&pd_mipi_csi_i2c0>;
1492 #address-cells = <1>; 1492 #address-cells = <1>;
1493 #size-cells = <0>; 1493 #size-cells = <0>;
1494 status = "disabled"; 1494 status = "disabled";
1495 }; 1495 };
1496 1496
1497 intmux_cm40: intmux@37400000 { 1497 intmux_cm40: intmux@37400000 {
1498 compatible = "nxp,imx-intmux"; 1498 compatible = "nxp,imx-intmux";
1499 reg = <0x0 0x37400000 0x0 0x1000>; 1499 reg = <0x0 0x37400000 0x0 0x1000>;
1500 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1500 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1507 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-controller; 1508 interrupt-controller;
1509 interrupt-parent = <&gic>; 1509 interrupt-parent = <&gic>;
1510 #interrupt-cells = <2>; 1510 #interrupt-cells = <2>;
1511 clocks = <&clk IMX8QXP_CM40_IPG_CLK>; 1511 clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
1512 clock-names = "ipg"; 1512 clock-names = "ipg";
1513 power-domains = <&pd_cm40_intmux>; 1513 power-domains = <&pd_cm40_intmux>;
1514 status = "disabled"; 1514 status = "disabled";
1515 }; 1515 };
1516 1516
1517 i2c0_cm40: i2c@37230000 { 1517 i2c0_cm40: i2c@37230000 {
1518 compatible = "fsl,imx8qm-lpi2c"; 1518 compatible = "fsl,imx8qm-lpi2c";
1519 reg = <0x0 0x37230000 0x0 0x1000>; 1519 reg = <0x0 0x37230000 0x0 0x1000>;
1520 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1521 interrupt-parent = <&intmux_cm40>; 1521 interrupt-parent = <&intmux_cm40>;
1522 clocks = <&clk IMX8QXP_CM40_I2C_CLK>, 1522 clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
1523 <&clk IMX8QXP_CM40_I2C_IPG_CLK>; 1523 <&clk IMX8QXP_CM40_I2C_IPG_CLK>;
1524 clock-names = "per", "ipg"; 1524 clock-names = "per", "ipg";
1525 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; 1525 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
1526 assigned-clock-rates = <24000000>; 1526 assigned-clock-rates = <24000000>;
1527 power-domains = <&pd_cm40_i2c>; 1527 power-domains = <&pd_cm40_i2c>;
1528 #address-cells = <1>; 1528 #address-cells = <1>;
1529 #size-cells = <0>; 1529 #size-cells = <0>;
1530 status = "disabled"; 1530 status = "disabled";
1531 }; 1531 };
1532 1532
1533 dpu_intsteer: dpu_intsteer@56000000 { 1533 dpu_intsteer: dpu_intsteer@56000000 {
1534 compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; 1534 compatible = "fsl,imx8qxp-dpu-intsteer", "syscon";
1535 reg = <0x0 0x56000000 0x0 0x10000>; 1535 reg = <0x0 0x56000000 0x0 0x10000>;
1536 }; 1536 };
1537 1537
1538 pixel_combiner: pixel-combiner@56020000 { 1538 pixel_combiner: pixel-combiner@56020000 {
1539 compatible = "fsl,imx8qxp-pixel-combiner"; 1539 compatible = "fsl,imx8qxp-pixel-combiner";
1540 reg = <0x0 0x56020000 0x0 0x10000>; 1540 reg = <0x0 0x56020000 0x0 0x10000>;
1541 power-domains = <&pd_dc0>; 1541 power-domains = <&pd_dc0>;
1542 status = "disabled"; 1542 status = "disabled";
1543 }; 1543 };
1544 1544
1545 prg1: prg@56040000 { 1545 prg1: prg@56040000 {
1546 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1546 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1547 reg = <0x0 0x56040000 0x0 0x10000>; 1547 reg = <0x0 0x56040000 0x0 0x10000>;
1548 clocks = <&clk IMX8QXP_DC0_PRG0_APB_CLK>, 1548 clocks = <&clk IMX8QXP_DC0_PRG0_APB_CLK>,
1549 <&clk IMX8QXP_DC0_PRG0_RTRAM_CLK>; 1549 <&clk IMX8QXP_DC0_PRG0_RTRAM_CLK>;
1550 clock-names = "apb", "rtram"; 1550 clock-names = "apb", "rtram";
1551 power-domains = <&pd_dc0>; 1551 power-domains = <&pd_dc0>;
1552 status = "disabled"; 1552 status = "disabled";
1553 }; 1553 };
1554 1554
1555 prg2: prg@56050000 { 1555 prg2: prg@56050000 {
1556 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1556 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1557 reg = <0x0 0x56050000 0x0 0x10000>; 1557 reg = <0x0 0x56050000 0x0 0x10000>;
1558 clocks = <&clk IMX8QXP_DC0_PRG1_APB_CLK>, 1558 clocks = <&clk IMX8QXP_DC0_PRG1_APB_CLK>,
1559 <&clk IMX8QXP_DC0_PRG1_RTRAM_CLK>; 1559 <&clk IMX8QXP_DC0_PRG1_RTRAM_CLK>;
1560 clock-names = "apb", "rtram"; 1560 clock-names = "apb", "rtram";
1561 power-domains = <&pd_dc0>; 1561 power-domains = <&pd_dc0>;
1562 status = "disabled"; 1562 status = "disabled";
1563 }; 1563 };
1564 1564
1565 prg3: prg@56060000 { 1565 prg3: prg@56060000 {
1566 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1566 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1567 reg = <0x0 0x56060000 0x0 0x10000>; 1567 reg = <0x0 0x56060000 0x0 0x10000>;
1568 clocks = <&clk IMX8QXP_DC0_PRG2_APB_CLK>, 1568 clocks = <&clk IMX8QXP_DC0_PRG2_APB_CLK>,
1569 <&clk IMX8QXP_DC0_PRG2_RTRAM_CLK>; 1569 <&clk IMX8QXP_DC0_PRG2_RTRAM_CLK>;
1570 clock-names = "apb", "rtram"; 1570 clock-names = "apb", "rtram";
1571 power-domains = <&pd_dc0>; 1571 power-domains = <&pd_dc0>;
1572 status = "disabled"; 1572 status = "disabled";
1573 }; 1573 };
1574 1574
1575 prg4: prg@56070000 { 1575 prg4: prg@56070000 {
1576 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1576 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1577 reg = <0x0 0x56070000 0x0 0x10000>; 1577 reg = <0x0 0x56070000 0x0 0x10000>;
1578 clocks = <&clk IMX8QXP_DC0_PRG3_APB_CLK>, 1578 clocks = <&clk IMX8QXP_DC0_PRG3_APB_CLK>,
1579 <&clk IMX8QXP_DC0_PRG3_RTRAM_CLK>; 1579 <&clk IMX8QXP_DC0_PRG3_RTRAM_CLK>;
1580 clock-names = "apb", "rtram"; 1580 clock-names = "apb", "rtram";
1581 power-domains = <&pd_dc0>; 1581 power-domains = <&pd_dc0>;
1582 status = "disabled"; 1582 status = "disabled";
1583 }; 1583 };
1584 1584
1585 prg5: prg@56080000 { 1585 prg5: prg@56080000 {
1586 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1586 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1587 reg = <0x0 0x56080000 0x0 0x10000>; 1587 reg = <0x0 0x56080000 0x0 0x10000>;
1588 clocks = <&clk IMX8QXP_DC0_PRG4_APB_CLK>, 1588 clocks = <&clk IMX8QXP_DC0_PRG4_APB_CLK>,
1589 <&clk IMX8QXP_DC0_PRG4_RTRAM_CLK>; 1589 <&clk IMX8QXP_DC0_PRG4_RTRAM_CLK>;
1590 clock-names = "apb", "rtram"; 1590 clock-names = "apb", "rtram";
1591 power-domains = <&pd_dc0>; 1591 power-domains = <&pd_dc0>;
1592 status = "disabled"; 1592 status = "disabled";
1593 }; 1593 };
1594 1594
1595 prg6: prg@56090000 { 1595 prg6: prg@56090000 {
1596 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1596 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1597 reg = <0x0 0x56090000 0x0 0x10000>; 1597 reg = <0x0 0x56090000 0x0 0x10000>;
1598 clocks = <&clk IMX8QXP_DC0_PRG5_APB_CLK>, 1598 clocks = <&clk IMX8QXP_DC0_PRG5_APB_CLK>,
1599 <&clk IMX8QXP_DC0_PRG5_RTRAM_CLK>; 1599 <&clk IMX8QXP_DC0_PRG5_RTRAM_CLK>;
1600 clock-names = "apb", "rtram"; 1600 clock-names = "apb", "rtram";
1601 power-domains = <&pd_dc0>; 1601 power-domains = <&pd_dc0>;
1602 status = "disabled"; 1602 status = "disabled";
1603 }; 1603 };
1604 1604
1605 prg7: prg@560a0000 { 1605 prg7: prg@560a0000 {
1606 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1606 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1607 reg = <0x0 0x560a0000 0x0 0x10000>; 1607 reg = <0x0 0x560a0000 0x0 0x10000>;
1608 clocks = <&clk IMX8QXP_DC0_PRG6_APB_CLK>, 1608 clocks = <&clk IMX8QXP_DC0_PRG6_APB_CLK>,
1609 <&clk IMX8QXP_DC0_PRG6_RTRAM_CLK>; 1609 <&clk IMX8QXP_DC0_PRG6_RTRAM_CLK>;
1610 clock-names = "apb", "rtram"; 1610 clock-names = "apb", "rtram";
1611 power-domains = <&pd_dc0>; 1611 power-domains = <&pd_dc0>;
1612 status = "disabled"; 1612 status = "disabled";
1613 }; 1613 };
1614 1614
1615 prg8: prg@560b0000 { 1615 prg8: prg@560b0000 {
1616 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1616 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1617 reg = <0x0 0x560b0000 0x0 0x10000>; 1617 reg = <0x0 0x560b0000 0x0 0x10000>;
1618 clocks = <&clk IMX8QXP_DC0_PRG7_APB_CLK>, 1618 clocks = <&clk IMX8QXP_DC0_PRG7_APB_CLK>,
1619 <&clk IMX8QXP_DC0_PRG7_RTRAM_CLK>; 1619 <&clk IMX8QXP_DC0_PRG7_RTRAM_CLK>;
1620 clock-names = "apb", "rtram"; 1620 clock-names = "apb", "rtram";
1621 power-domains = <&pd_dc0>; 1621 power-domains = <&pd_dc0>;
1622 status = "disabled"; 1622 status = "disabled";
1623 }; 1623 };
1624 1624
1625 prg9: prg@560c0000 { 1625 prg9: prg@560c0000 {
1626 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; 1626 compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg";
1627 reg = <0x0 0x560c0000 0x0 0x10000>; 1627 reg = <0x0 0x560c0000 0x0 0x10000>;
1628 clocks = <&clk IMX8QXP_DC0_PRG8_APB_CLK>, 1628 clocks = <&clk IMX8QXP_DC0_PRG8_APB_CLK>,
1629 <&clk IMX8QXP_DC0_PRG8_RTRAM_CLK>; 1629 <&clk IMX8QXP_DC0_PRG8_RTRAM_CLK>;
1630 clock-names = "apb", "rtram"; 1630 clock-names = "apb", "rtram";
1631 power-domains = <&pd_dc0>; 1631 power-domains = <&pd_dc0>;
1632 status = "disabled"; 1632 status = "disabled";
1633 }; 1633 };
1634 1634
1635 dpr1_channel1: dpr-channel@560d0000 { 1635 dpr1_channel1: dpr-channel@560d0000 {
1636 compatible = "fsl,imx8qxp-dpr-channel", 1636 compatible = "fsl,imx8qxp-dpr-channel",
1637 "fsl,imx8qm-dpr-channel"; 1637 "fsl,imx8qm-dpr-channel";
1638 reg = <0x0 0x560d0000 0x0 0x10000>; 1638 reg = <0x0 0x560d0000 0x0 0x10000>;
1639 fsl,sc-resource = <SC_R_DC_0_BLIT0>; 1639 fsl,sc-resource = <SC_R_DC_0_BLIT0>;
1640 fsl,prgs = <&prg1>; 1640 fsl,prgs = <&prg1>;
1641 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, 1641 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
1642 <&clk IMX8QXP_DC0_DPR0_B_CLK>, 1642 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
1643 <&clk IMX8QXP_DC0_RTRAM0_CLK>; 1643 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
1644 clock-names = "apb", "b", "rtram"; 1644 clock-names = "apb", "b", "rtram";
1645 power-domains = <&pd_dc0>; 1645 power-domains = <&pd_dc0>;
1646 status = "disabled"; 1646 status = "disabled";
1647 }; 1647 };
1648 1648
1649 dpr1_channel2: dpr-channel@560e0000 { 1649 dpr1_channel2: dpr-channel@560e0000 {
1650 compatible = "fsl,imx8qxp-dpr-channel", 1650 compatible = "fsl,imx8qxp-dpr-channel",
1651 "fsl,imx8qm-dpr-channel"; 1651 "fsl,imx8qm-dpr-channel";
1652 reg = <0x0 0x560e0000 0x0 0x10000>; 1652 reg = <0x0 0x560e0000 0x0 0x10000>;
1653 fsl,sc-resource = <SC_R_DC_0_BLIT1>; 1653 fsl,sc-resource = <SC_R_DC_0_BLIT1>;
1654 fsl,prgs = <&prg2>, <&prg1>; 1654 fsl,prgs = <&prg2>, <&prg1>;
1655 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, 1655 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
1656 <&clk IMX8QXP_DC0_DPR0_B_CLK>, 1656 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
1657 <&clk IMX8QXP_DC0_RTRAM0_CLK>; 1657 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
1658 clock-names = "apb", "b", "rtram"; 1658 clock-names = "apb", "b", "rtram";
1659 power-domains = <&pd_dc0>; 1659 power-domains = <&pd_dc0>;
1660 status = "disabled"; 1660 status = "disabled";
1661 }; 1661 };
1662 1662
1663 dpr1_channel3: dpr-channel@560f0000 { 1663 dpr1_channel3: dpr-channel@560f0000 {
1664 compatible = "fsl,imx8qxp-dpr-channel", 1664 compatible = "fsl,imx8qxp-dpr-channel",
1665 "fsl,imx8qm-dpr-channel"; 1665 "fsl,imx8qm-dpr-channel";
1666 reg = <0x0 0x560f0000 0x0 0x10000>; 1666 reg = <0x0 0x560f0000 0x0 0x10000>;
1667 fsl,sc-resource = <SC_R_DC_0_FRAC0>; 1667 fsl,sc-resource = <SC_R_DC_0_FRAC0>;
1668 fsl,prgs = <&prg3>; 1668 fsl,prgs = <&prg3>;
1669 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, 1669 clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>,
1670 <&clk IMX8QXP_DC0_DPR0_B_CLK>, 1670 <&clk IMX8QXP_DC0_DPR0_B_CLK>,
1671 <&clk IMX8QXP_DC0_RTRAM0_CLK>; 1671 <&clk IMX8QXP_DC0_RTRAM0_CLK>;
1672 clock-names = "apb", "b", "rtram"; 1672 clock-names = "apb", "b", "rtram";
1673 power-domains = <&pd_dc0>; 1673 power-domains = <&pd_dc0>;
1674 status = "disabled"; 1674 status = "disabled";
1675 }; 1675 };
1676 1676
1677 dpr2_channel1: dpr-channel@56100000 { 1677 dpr2_channel1: dpr-channel@56100000 {
1678 compatible = "fsl,imx8qxp-dpr-channel", 1678 compatible = "fsl,imx8qxp-dpr-channel",
1679 "fsl,imx8qm-dpr-channel"; 1679 "fsl,imx8qm-dpr-channel";
1680 reg = <0x0 0x56100000 0x0 0x10000>; 1680 reg = <0x0 0x56100000 0x0 0x10000>;
1681 fsl,sc-resource = <SC_R_DC_0_VIDEO0>; 1681 fsl,sc-resource = <SC_R_DC_0_VIDEO0>;
1682 fsl,prgs = <&prg4>, <&prg5>; 1682 fsl,prgs = <&prg4>, <&prg5>;
1683 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, 1683 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
1684 <&clk IMX8QXP_DC0_DPR1_B_CLK>, 1684 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
1685 <&clk IMX8QXP_DC0_RTRAM1_CLK>; 1685 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
1686 clock-names = "apb", "b", "rtram"; 1686 clock-names = "apb", "b", "rtram";
1687 power-domains = <&pd_dc0>; 1687 power-domains = <&pd_dc0>;
1688 status = "disabled"; 1688 status = "disabled";
1689 }; 1689 };
1690 1690
1691 dpr2_channel2: dpr-channel@56110000 { 1691 dpr2_channel2: dpr-channel@56110000 {
1692 compatible = "fsl,imx8qxp-dpr-channel", 1692 compatible = "fsl,imx8qxp-dpr-channel",
1693 "fsl,imx8qm-dpr-channel"; 1693 "fsl,imx8qm-dpr-channel";
1694 reg = <0x0 0x56110000 0x0 0x10000>; 1694 reg = <0x0 0x56110000 0x0 0x10000>;
1695 fsl,sc-resource = <SC_R_DC_0_VIDEO1>; 1695 fsl,sc-resource = <SC_R_DC_0_VIDEO1>;
1696 fsl,prgs = <&prg6>, <&prg7>; 1696 fsl,prgs = <&prg6>, <&prg7>;
1697 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, 1697 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
1698 <&clk IMX8QXP_DC0_DPR1_B_CLK>, 1698 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
1699 <&clk IMX8QXP_DC0_RTRAM1_CLK>; 1699 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
1700 clock-names = "apb", "b", "rtram"; 1700 clock-names = "apb", "b", "rtram";
1701 power-domains = <&pd_dc0>; 1701 power-domains = <&pd_dc0>;
1702 status = "disabled"; 1702 status = "disabled";
1703 }; 1703 };
1704 1704
1705 dpr2_channel3: dpr-channel@56120000 { 1705 dpr2_channel3: dpr-channel@56120000 {
1706 compatible = "fsl,imx8qxp-dpr-channel", 1706 compatible = "fsl,imx8qxp-dpr-channel",
1707 "fsl,imx8qm-dpr-channel"; 1707 "fsl,imx8qm-dpr-channel";
1708 reg = <0x0 0x56120000 0x0 0x10000>; 1708 reg = <0x0 0x56120000 0x0 0x10000>;
1709 fsl,sc-resource = <SC_R_DC_0_WARP>; 1709 fsl,sc-resource = <SC_R_DC_0_WARP>;
1710 fsl,prgs = <&prg8>, <&prg9>; 1710 fsl,prgs = <&prg8>, <&prg9>;
1711 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, 1711 clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>,
1712 <&clk IMX8QXP_DC0_DPR1_B_CLK>, 1712 <&clk IMX8QXP_DC0_DPR1_B_CLK>,
1713 <&clk IMX8QXP_DC0_RTRAM1_CLK>; 1713 <&clk IMX8QXP_DC0_RTRAM1_CLK>;
1714 clock-names = "apb", "b", "rtram"; 1714 clock-names = "apb", "b", "rtram";
1715 power-domains = <&pd_dc0>; 1715 power-domains = <&pd_dc0>;
1716 status = "disabled"; 1716 status = "disabled";
1717 }; 1717 };
1718 1718
1719 dpu1: dpu@56180000 { 1719 dpu1: dpu@56180000 {
1720 #address-cells = <1>; 1720 #address-cells = <1>;
1721 #size-cells = <0>; 1721 #size-cells = <0>;
1722 compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; 1722 compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu";
1723 reg = <0x0 0x56180000 0x0 0x40000>; 1723 reg = <0x0 0x56180000 0x0 0x40000>;
1724 intsteer = <&dpu_intsteer>; 1724 intsteer = <&dpu_intsteer>;
1725 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1725 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1734 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1735 interrupt-names = "irq_common", 1735 interrupt-names = "irq_common",
1736 "irq_stream0a", 1736 "irq_stream0a",
1737 "irq_stream0b", /* to M4? */ 1737 "irq_stream0b", /* to M4? */
1738 "irq_stream1a", 1738 "irq_stream1a",
1739 "irq_stream1b", /* to M4? */ 1739 "irq_stream1b", /* to M4? */
1740 "irq_reserved0", 1740 "irq_reserved0",
1741 "irq_reserved1", 1741 "irq_reserved1",
1742 "irq_blit", 1742 "irq_blit",
1743 "irq_dpr0", 1743 "irq_dpr0",
1744 "irq_dpr1"; 1744 "irq_dpr1";
1745 clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, 1745 clocks = <&clk IMX8QXP_DC0_PLL0_CLK>,
1746 <&clk IMX8QXP_DC0_PLL1_CLK>, 1746 <&clk IMX8QXP_DC0_PLL1_CLK>,
1747 <&clk IMX8QXP_DC0_DISP0_CLK>, 1747 <&clk IMX8QXP_DC0_DISP0_CLK>,
1748 <&clk IMX8QXP_DC0_DISP1_CLK>; 1748 <&clk IMX8QXP_DC0_DISP1_CLK>;
1749 clock-names = "pll0", "pll1", "disp0", "disp1"; 1749 clock-names = "pll0", "pll1", "disp0", "disp1";
1750 power-domains = <&pd_dc0_pll1>; 1750 power-domains = <&pd_dc0_pll1>;
1751 fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, 1751 fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>,
1752 <&dpr1_channel3>, <&dpr2_channel1>, 1752 <&dpr1_channel3>, <&dpr2_channel1>,
1753 <&dpr2_channel2>, <&dpr2_channel3>; 1753 <&dpr2_channel2>, <&dpr2_channel3>;
1754 fsl,pixel-combiner = <&pixel_combiner>; 1754 fsl,pixel-combiner = <&pixel_combiner>;
1755 status = "disabled"; 1755 status = "disabled";
1756 1756
1757 dpu_disp0: port@0 { 1757 dpu_disp0: port@0 {
1758 reg = <0>; 1758 reg = <0>;
1759 1759
1760 dpu_disp0_lvds0_ch0: lvds0-endpoint { 1760 dpu_disp0_lvds0_ch0: lvds0-endpoint {
1761 remote-endpoint = <&ldb1_ch0>; 1761 remote-endpoint = <&ldb1_ch0>;
1762 }; 1762 };
1763 1763
1764 dpu_disp0_lvds0_ch1: lvds1-endpoint { 1764 dpu_disp0_lvds0_ch1: lvds1-endpoint {
1765 remote-endpoint = <&ldb1_ch1>; 1765 remote-endpoint = <&ldb1_ch1>;
1766 }; 1766 };
1767 1767
1768 dpu_disp0_mipi_dsi: mipi-dsi-endpoint { 1768 dpu_disp0_mipi_dsi: mipi-dsi-endpoint {
1769 remote-endpoint = <&mipi_dsi1_in>; 1769 remote-endpoint = <&mipi_dsi1_in>;
1770 }; 1770 };
1771 }; 1771 };
1772 1772
1773 dpu_disp1: port@1 { 1773 dpu_disp1: port@1 {
1774 reg = <1>; 1774 reg = <1>;
1775 1775
1776 dpu_disp1_lvds1_ch0: lvds0-endpoint { 1776 dpu_disp1_lvds1_ch0: lvds0-endpoint {
1777 remote-endpoint = <&ldb2_ch0>; 1777 remote-endpoint = <&ldb2_ch0>;
1778 }; 1778 };
1779 1779
1780 dpu_disp1_lvds1_ch1: lvds1-endpoint { 1780 dpu_disp1_lvds1_ch1: lvds1-endpoint {
1781 remote-endpoint = <&ldb2_ch1>; 1781 remote-endpoint = <&ldb2_ch1>;
1782 }; 1782 };
1783 1783
1784 dpu_disp1_mipi_dsi: mipi-dsi-endpoint { 1784 dpu_disp1_mipi_dsi: mipi-dsi-endpoint {
1785 remote-endpoint = <&mipi_dsi2_in>; 1785 remote-endpoint = <&mipi_dsi2_in>;
1786 }; 1786 };
1787 }; 1787 };
1788 }; 1788 };
1789 1789
1790 irqsteer_mipi_lvds0: irqsteer@56220000 { 1790 irqsteer_mipi_lvds0: irqsteer@56220000 {
1791 compatible = "nxp,imx-irqsteer"; 1791 compatible = "nxp,imx-irqsteer";
1792 reg = <0x0 0x56220000 0x0 0x1000>; 1792 reg = <0x0 0x56220000 0x0 0x1000>;
1793 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1793 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1794 interrupt-controller; 1794 interrupt-controller;
1795 interrupt-parent = <&gic>; 1795 interrupt-parent = <&gic>;
1796 #interrupt-cells = <2>; 1796 #interrupt-cells = <2>;
1797 clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; 1797 clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>;
1798 clock-names = "ipg"; 1798 clock-names = "ipg";
1799 power-domains = <&pd_mipi_dsi0>; 1799 power-domains = <&pd_mipi_dsi0>;
1800 }; 1800 };
1801 1801
1802 adma_lcdif: lcdif@5a180000 { 1802 adma_lcdif: lcdif@5a180000 {
1803 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; 1803 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
1804 reg = <0x0 0x5a180000 0x0 0x10000>; 1804 reg = <0x0 0x5a180000 0x0 0x10000>;
1805 clocks = <&clk IMX8QXP_LCD_CLK>, 1805 clocks = <&clk IMX8QXP_LCD_CLK>,
1806 <&clk IMX8QXP_LCD_PXL_CLK>, 1806 <&clk IMX8QXP_LCD_PXL_CLK>,
1807 <&clk IMX8QXP_LCD_IPG_CLK>; 1807 <&clk IMX8QXP_LCD_IPG_CLK>;
1808 clock-names = "pix", "disp_axi", "axi"; 1808 clock-names = "pix", "disp_axi", "axi";
1809 assigned-clocks = <&clk IMX8QXP_LCD_SEL>, 1809 assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
1810 <&clk IMX8QXP_LCD_PXL_SEL>, 1810 <&clk IMX8QXP_LCD_PXL_SEL>,
1811 <&clk IMX8QXP_ELCDIF_PLL_DIV>; 1811 <&clk IMX8QXP_ELCDIF_PLL_DIV>;
1812 assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, 1812 assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>,
1813 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; 1813 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
1814 assigned-clock-rates = <0>, <24000000>, <804000000>; 1814 assigned-clock-rates = <0>, <24000000>, <804000000>;
1815 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1815 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1816 power-domains = <&pd_dma_lcd0>; 1816 power-domains = <&pd_dma_lcd0>;
1817 status = "disabled"; 1817 status = "disabled";
1818 }; 1818 };
1819 1819
1820 pwm_adma_lcdif: pwm@5a190000 { 1820 pwm_adma_lcdif: pwm@5a190000 {
1821 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 1821 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
1822 reg = <0x0 0x5a190000 0 0x1000>; 1822 reg = <0x0 0x5a190000 0 0x1000>;
1823 clocks = <&clk IMX8QXP_PWM_IPG_CLK>, 1823 clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
1824 <&clk IMX8QXP_PWM_CLK>; 1824 <&clk IMX8QXP_PWM_CLK>;
1825 clock-names = "ipg", "per"; 1825 clock-names = "ipg", "per";
1826 assigned-clocks = <&clk IMX8QXP_PWM_CLK>; 1826 assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
1827 assigned-clock-rates = <24000000>; 1827 assigned-clock-rates = <24000000>;
1828 #pwm-cells = <2>; 1828 #pwm-cells = <2>;
1829 power-domains = <&pd_dma_pwm0>; 1829 power-domains = <&pd_dma_pwm0>;
1830 status = "disabled"; 1830 status = "disabled";
1831 }; 1831 };
1832 1832
1833 mipi_dsi_csr1: csr@56221000 { 1833 mipi_dsi_csr1: csr@56221000 {
1834 compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; 1834 compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
1835 reg = <0x0 0x56221000 0x0 0x1000>; 1835 reg = <0x0 0x56221000 0x0 0x1000>;
1836 }; 1836 };
1837 1837
1838 mipi_dsi_phy1: dsi_phy@56228300 { 1838 mipi_dsi_phy1: dsi_phy@56228300 {
1839 #address-cells = <1>; 1839 #address-cells = <1>;
1840 #size-cells = <0>; 1840 #size-cells = <0>;
1841 compatible = "mixel,imx8qxp-mipi-dsi-phy"; 1841 compatible = "mixel,imx8qxp-mipi-dsi-phy";
1842 reg = <0x0 0x56228300 0x0 0x100>; 1842 reg = <0x0 0x56228300 0x0 0x100>;
1843 #phy-cells = <0>; 1843 #phy-cells = <0>;
1844 status = "disabled"; 1844 status = "disabled";
1845 }; 1845 };
1846 1846
1847 mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { 1847 mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
1848 #address-cells = <1>; 1848 #address-cells = <1>;
1849 #size-cells = <0>; 1849 #size-cells = <0>;
1850 compatible = "nwl,mipi-dsi"; 1850 compatible = "nwl,mipi-dsi";
1851 reg = <0x0 0x56228000 0x0 0x300>; 1851 reg = <0x0 0x56228000 0x0 0x300>;
1852 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 1852 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
1853 interrupt-parent = <&irqsteer_mipi_lvds0>; 1853 interrupt-parent = <&irqsteer_mipi_lvds0>;
1854 clocks = 1854 clocks =
1855 <&clk IMX8QXP_MIPI0_BYPASS_CLK>, 1855 <&clk IMX8QXP_MIPI0_BYPASS_CLK>,
1856 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, 1856 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
1857 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; 1857 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
1858 clock-names = "phy_ref", "tx_esc", "rx_esc"; 1858 clock-names = "phy_ref", "tx_esc", "rx_esc";
1859 assigned-clocks = 1859 assigned-clocks =
1860 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, 1860 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>,
1861 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, 1861 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>,
1862 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, 1862 <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>,
1863 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; 1863 <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>;
1864 assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; 1864 assigned-clock-rates = <0>, <0>, <18000000>, <72000000>;
1865 assigned-clock-parents = 1865 assigned-clock-parents =
1866 <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, 1866 <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>,
1867 <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; 1867 <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>;
1868 power-domains = <&pd_mipi_dsi0>; 1868 power-domains = <&pd_mipi_dsi0>;
1869 phys = <&mipi_dsi_phy1>; 1869 phys = <&mipi_dsi_phy1>;
1870 phy-names = "dphy"; 1870 phy-names = "dphy";
1871 status = "disabled"; 1871 status = "disabled";
1872 1872
1873 port@0 { 1873 port@0 {
1874 mipi_dsi_bridge1_in: endpoint { 1874 mipi_dsi_bridge1_in: endpoint {
1875 remote-endpoint = <&mipi_dsi1_out>; 1875 remote-endpoint = <&mipi_dsi1_out>;
1876 }; 1876 };
1877 }; 1877 };
1878 }; 1878 };
1879 1879
1880 mipi_dsi1: mipi_dsi@56228000 { 1880 mipi_dsi1: mipi_dsi@56228000 {
1881 compatible = "fsl,imx8qxp-mipi-dsi"; 1881 compatible = "fsl,imx8qxp-mipi-dsi";
1882 clocks = 1882 clocks =
1883 <&clk IMX8QXP_MIPI0_PIXEL_CLK>, 1883 <&clk IMX8QXP_MIPI0_PIXEL_CLK>,
1884 <&clk IMX8QXP_MIPI0_BYPASS_CLK>, 1884 <&clk IMX8QXP_MIPI0_BYPASS_CLK>,
1885 <&clk IMX8QXP_CLK_DUMMY>; 1885 <&clk IMX8QXP_CLK_DUMMY>;
1886 clock-names = "pixel", "bypass", "phy_ref"; 1886 clock-names = "pixel", "bypass", "phy_ref";
1887 power-domains = <&pd_mipi_dsi0>; 1887 power-domains = <&pd_mipi_dsi0>;
1888 csr = <&mipi_dsi_csr1>; 1888 csr = <&mipi_dsi_csr1>;
1889 phys = <&mipi_dsi_phy1>; 1889 phys = <&mipi_dsi_phy1>;
1890 phy-names = "dphy"; 1890 phy-names = "dphy";
1891 status = "disabled"; 1891 status = "disabled";
1892 1892
1893 port@0 { 1893 port@0 {
1894 mipi_dsi1_in: endpoint { 1894 mipi_dsi1_in: endpoint {
1895 remote-endpoint = <&dpu_disp0_mipi_dsi>; 1895 remote-endpoint = <&dpu_disp0_mipi_dsi>;
1896 }; 1896 };
1897 }; 1897 };
1898 1898
1899 port@1 { 1899 port@1 {
1900 mipi_dsi1_out: endpoint { 1900 mipi_dsi1_out: endpoint {
1901 remote-endpoint = <&mipi_dsi_bridge1_in>; 1901 remote-endpoint = <&mipi_dsi_bridge1_in>;
1902 }; 1902 };
1903 }; 1903 };
1904 }; 1904 };
1905 1905
1906 lvds_region1: lvds_region@56220000 { 1906 lvds_region1: lvds_region@56220000 {
1907 compatible = "fsl,imx8qxp-lvds-region", "syscon"; 1907 compatible = "fsl,imx8qxp-lvds-region", "syscon";
1908 reg = <0x0 0x56220000 0x0 0x10000>; 1908 reg = <0x0 0x56220000 0x0 0x10000>;
1909 }; 1909 };
1910 1910
1911 ldb1_phy: ldb_phy@56221000 { 1911 ldb1_phy: ldb_phy@56221000 {
1912 compatible = "mixel,lvds-combo-phy"; 1912 compatible = "mixel,lvds-combo-phy";
1913 reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; 1913 reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>;
1914 #phy-cells = <0>; 1914 #phy-cells = <0>;
1915 clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; 1915 clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>;
1916 clock-names = "phy"; 1916 clock-names = "phy";
1917 status = "disabled"; 1917 status = "disabled";
1918 }; 1918 };
1919 1919
1920 ldb1: ldb@562210e0 { 1920 ldb1: ldb@562210e0 {
1921 #address-cells = <1>; 1921 #address-cells = <1>;
1922 #size-cells = <0>; 1922 #size-cells = <0>;
1923 compatible = "fsl,imx8qxp-ldb"; 1923 compatible = "fsl,imx8qxp-ldb";
1924 clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, 1924 clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>,
1925 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>, 1925 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>,
1926 <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, 1926 <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>,
1927 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; 1927 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>;
1928 clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; 1928 clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
1929 power-domains = <&pd_mipi_dsi_0_lvds>; 1929 power-domains = <&pd_mipi_dsi_0_lvds>;
1930 gpr = <&lvds_region1>; 1930 gpr = <&lvds_region1>;
1931 aux-gpr = <&lvds_region2>; 1931 aux-gpr = <&lvds_region2>;
1932 status = "disabled"; 1932 status = "disabled";
1933 1933
1934 lvds-channel@0 { 1934 lvds-channel@0 {
1935 #address-cells = <1>; 1935 #address-cells = <1>;
1936 #size-cells = <0>; 1936 #size-cells = <0>;
1937 reg = <0>; 1937 reg = <0>;
1938 phys = <&ldb1_phy>, <&ldb2_phy>; 1938 phys = <&ldb1_phy>, <&ldb2_phy>;
1939 phy-names = "ldb_phy", "aux_ldb_phy"; 1939 phy-names = "ldb_phy", "aux_ldb_phy";
1940 status = "disabled"; 1940 status = "disabled";
1941 1941
1942 port@0 { 1942 port@0 {
1943 reg = <0>; 1943 reg = <0>;
1944 1944
1945 ldb1_ch0: endpoint { 1945 ldb1_ch0: endpoint {
1946 remote-endpoint = <&dpu_disp0_lvds0_ch0>; 1946 remote-endpoint = <&dpu_disp0_lvds0_ch0>;
1947 }; 1947 };
1948 }; 1948 };
1949 }; 1949 };
1950 1950
1951 lvds-channel@1 { 1951 lvds-channel@1 {
1952 #address-cells = <1>; 1952 #address-cells = <1>;
1953 #size-cells = <0>; 1953 #size-cells = <0>;
1954 reg = <1>; 1954 reg = <1>;
1955 phys = <&ldb1_phy>; 1955 phys = <&ldb1_phy>;
1956 phy-names = "ldb_phy"; 1956 phy-names = "ldb_phy";
1957 status = "disabled"; 1957 status = "disabled";
1958 1958
1959 port@0 { 1959 port@0 {
1960 reg = <0>; 1960 reg = <0>;
1961 1961
1962 ldb1_ch1: endpoint { 1962 ldb1_ch1: endpoint {
1963 remote-endpoint = <&dpu_disp0_lvds0_ch1>; 1963 remote-endpoint = <&dpu_disp0_lvds0_ch1>;
1964 }; 1964 };
1965 }; 1965 };
1966 }; 1966 };
1967 }; 1967 };
1968 1968
1969 pwm_mipi_lvds0: pwm@56224000 { 1969 pwm_mipi_lvds0: pwm@56224000 {
1970 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 1970 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
1971 reg = <0x0 0x56224000 0 0x1000>; 1971 reg = <0x0 0x56224000 0 0x1000>;
1972 clocks = <&clk IMX8QXP_MIPI0_PWM_IPG_CLK>, 1972 clocks = <&clk IMX8QXP_MIPI0_PWM_IPG_CLK>,
1973 <&clk IMX8QXP_MIPI0_PWM_CLK>, 1973 <&clk IMX8QXP_MIPI0_PWM_CLK>,
1974 <&clk IMX8QXP_MIPI0_PWM_32K_CLK>; 1974 <&clk IMX8QXP_MIPI0_PWM_32K_CLK>;
1975 clock-names = "ipg", "per", "32k"; 1975 clock-names = "ipg", "per", "32k";
1976 assigned-clocks = <&clk IMX8QXP_MIPI0_PWM_CLK>; 1976 assigned-clocks = <&clk IMX8QXP_MIPI0_PWM_CLK>;
1977 assigned-clock-rates = <24000000>; 1977 assigned-clock-rates = <24000000>;
1978 #pwm-cells = <2>; 1978 #pwm-cells = <2>;
1979 power-domains = <&pd_mipi_0_pwm0>; 1979 power-domains = <&pd_mipi_0_pwm0>;
1980 status = "disabled"; 1980 status = "disabled";
1981 }; 1981 };
1982 1982
1983 i2c0_mipi_lvds0: i2c@56226000 { 1983 i2c0_mipi_lvds0: i2c@56226000 {
1984 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; 1984 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
1985 reg = <0x0 0x56226000 0x0 0x1000>; 1985 reg = <0x0 0x56226000 0x0 0x1000>;
1986 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1986 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1987 interrupt-parent = <&irqsteer_mipi_lvds0>; 1987 interrupt-parent = <&irqsteer_mipi_lvds0>;
1988 clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, 1988 clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>,
1989 <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; 1989 <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>;
1990 clock-names = "per", "ipg"; 1990 clock-names = "per", "ipg";
1991 assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; 1991 assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>;
1992 assigned-clock-rates = <24000000>; 1992 assigned-clock-rates = <24000000>;
1993 power-domains = <&pd_mipi_dsi_0_i2c0>; 1993 power-domains = <&pd_mipi_dsi_0_i2c0>;
1994 #address-cells = <1>; 1994 #address-cells = <1>;
1995 #size-cells = <0>; 1995 #size-cells = <0>;
1996 status = "disabled"; 1996 status = "disabled";
1997 }; 1997 };
1998 1998
1999 irqsteer_mipi_lvds1: irqsteer@56240000 { 1999 irqsteer_mipi_lvds1: irqsteer@56240000 {
2000 compatible = "nxp,imx-irqsteer"; 2000 compatible = "nxp,imx-irqsteer";
2001 reg = <0x0 0x56240000 0x0 0x1000>; 2001 reg = <0x0 0x56240000 0x0 0x1000>;
2002 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 2002 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
2003 interrupt-controller; 2003 interrupt-controller;
2004 interrupt-parent = <&gic>; 2004 interrupt-parent = <&gic>;
2005 #interrupt-cells = <2>; 2005 #interrupt-cells = <2>;
2006 clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; 2006 clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>;
2007 clock-names = "ipg"; 2007 clock-names = "ipg";
2008 power-domains = <&pd_mipi_dsi1>; 2008 power-domains = <&pd_mipi_dsi1>;
2009 }; 2009 };
2010 2010
2011 mipi_dsi_csr2: csr@56241000 { 2011 mipi_dsi_csr2: csr@56241000 {
2012 compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; 2012 compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
2013 reg = <0x0 0x56241000 0x0 0x1000>; 2013 reg = <0x0 0x56241000 0x0 0x1000>;
2014 }; 2014 };
2015 2015
2016 mipi_dsi_phy2: dsi_phy@56248300 { 2016 mipi_dsi_phy2: dsi_phy@56248300 {
2017 #address-cells = <1>; 2017 #address-cells = <1>;
2018 #size-cells = <0>; 2018 #size-cells = <0>;
2019 compatible = "mixel,imx8qxp-mipi-dsi-phy"; 2019 compatible = "mixel,imx8qxp-mipi-dsi-phy";
2020 reg = <0x0 0x56248300 0x0 0x100>; 2020 reg = <0x0 0x56248300 0x0 0x100>;
2021 #phy-cells = <0>; 2021 #phy-cells = <0>;
2022 status = "disabled"; 2022 status = "disabled";
2023 }; 2023 };
2024 2024
2025 mipi_dsi_bridge2: mipi_dsi_bridge@56248000 { 2025 mipi_dsi_bridge2: mipi_dsi_bridge@56248000 {
2026 #address-cells = <1>; 2026 #address-cells = <1>;
2027 #size-cells = <0>; 2027 #size-cells = <0>;
2028 compatible = "nwl,mipi-dsi"; 2028 compatible = "nwl,mipi-dsi";
2029 reg = <0x0 0x56248000 0x0 0x300>; 2029 reg = <0x0 0x56248000 0x0 0x300>;
2030 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 2030 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
2031 interrupt-parent = <&irqsteer_mipi_lvds1>; 2031 interrupt-parent = <&irqsteer_mipi_lvds1>;
2032 clocks = 2032 clocks =
2033 <&clk IMX8QXP_MIPI1_BYPASS_CLK>, 2033 <&clk IMX8QXP_MIPI1_BYPASS_CLK>,
2034 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, 2034 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>,
2035 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; 2035 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>;
2036 clock-names = "phy_ref", "tx_esc", "rx_esc"; 2036 clock-names = "phy_ref", "tx_esc", "rx_esc";
2037 assigned-clocks = 2037 assigned-clocks =
2038 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>, 2038 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>,
2039 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>, 2039 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>,
2040 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, 2040 <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>,
2041 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; 2041 <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>;
2042 assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; 2042 assigned-clock-rates = <0>, <0>, <18000000>, <72000000>;
2043 assigned-clock-parents = 2043 assigned-clock-parents =
2044 <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, 2044 <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>,
2045 <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>; 2045 <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>;
2046 power-domains = <&pd_mipi_dsi1>; 2046 power-domains = <&pd_mipi_dsi1>;
2047 phys = <&mipi_dsi_phy2>; 2047 phys = <&mipi_dsi_phy2>;
2048 phy-names = "dphy"; 2048 phy-names = "dphy";
2049 status = "disabled"; 2049 status = "disabled";
2050 2050
2051 port@0 { 2051 port@0 {
2052 mipi_dsi_bridge2_in: endpoint { 2052 mipi_dsi_bridge2_in: endpoint {
2053 remote-endpoint = <&mipi_dsi2_out>; 2053 remote-endpoint = <&mipi_dsi2_out>;
2054 }; 2054 };
2055 }; 2055 };
2056 }; 2056 };
2057 2057
2058 mipi_dsi2: mipi_dsi@56248000 { 2058 mipi_dsi2: mipi_dsi@56248000 {
2059 compatible = "fsl,imx8qxp-mipi-dsi"; 2059 compatible = "fsl,imx8qxp-mipi-dsi";
2060 clocks = 2060 clocks =
2061 <&clk IMX8QXP_MIPI1_PIXEL_CLK>, 2061 <&clk IMX8QXP_MIPI1_PIXEL_CLK>,
2062 <&clk IMX8QXP_MIPI1_BYPASS_CLK>, 2062 <&clk IMX8QXP_MIPI1_BYPASS_CLK>,
2063 <&clk IMX8QXP_CLK_DUMMY>; 2063 <&clk IMX8QXP_CLK_DUMMY>;
2064 clock-names = "pixel", "bypass", "phy_ref"; 2064 clock-names = "pixel", "bypass", "phy_ref";
2065 power-domains = <&pd_mipi_dsi1>; 2065 power-domains = <&pd_mipi_dsi1>;
2066 csr = <&mipi_dsi_csr2>; 2066 csr = <&mipi_dsi_csr2>;
2067 phys = <&mipi_dsi_phy2>; 2067 phys = <&mipi_dsi_phy2>;
2068 phy-names = "dphy"; 2068 phy-names = "dphy";
2069 status = "disabled"; 2069 status = "disabled";
2070 2070
2071 port@0 { 2071 port@0 {
2072 mipi_dsi2_in: endpoint { 2072 mipi_dsi2_in: endpoint {
2073 remote-endpoint = <&dpu_disp1_mipi_dsi>; 2073 remote-endpoint = <&dpu_disp1_mipi_dsi>;
2074 }; 2074 };
2075 }; 2075 };
2076 2076
2077 port@1 { 2077 port@1 {
2078 mipi_dsi2_out: endpoint { 2078 mipi_dsi2_out: endpoint {
2079 remote-endpoint = <&mipi_dsi_bridge2_in>; 2079 remote-endpoint = <&mipi_dsi_bridge2_in>;
2080 }; 2080 };
2081 }; 2081 };
2082 }; 2082 };
2083 2083
2084 lvds_region2: lvds_region@56240000 { 2084 lvds_region2: lvds_region@56240000 {
2085 compatible = "fsl,imx8qxp-lvds-region", "syscon"; 2085 compatible = "fsl,imx8qxp-lvds-region", "syscon";
2086 reg = <0x0 0x56240000 0x0 0x10000>; 2086 reg = <0x0 0x56240000 0x0 0x10000>;
2087 }; 2087 };
2088 2088
2089 ldb2_phy: ldb_phy@56241000 { 2089 ldb2_phy: ldb_phy@56241000 {
2090 compatible = "mixel,lvds-combo-phy"; 2090 compatible = "mixel,lvds-combo-phy";
2091 reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; 2091 reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>;
2092 #phy-cells = <0>; 2092 #phy-cells = <0>;
2093 clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; 2093 clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>;
2094 clock-names = "phy"; 2094 clock-names = "phy";
2095 status = "disabled"; 2095 status = "disabled";
2096 }; 2096 };
2097 2097
2098 ldb2: ldb@562410e0 { 2098 ldb2: ldb@562410e0 {
2099 #address-cells = <1>; 2099 #address-cells = <1>;
2100 #size-cells = <0>; 2100 #size-cells = <0>;
2101 compatible = "fsl,imx8qxp-ldb"; 2101 compatible = "fsl,imx8qxp-ldb";
2102 clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, 2102 clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>,
2103 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>, 2103 <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>,
2104 <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, 2104 <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>,
2105 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; 2105 <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>;
2106 clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; 2106 clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass";
2107 power-domains = <&pd_mipi_dsi_1_lvds>; 2107 power-domains = <&pd_mipi_dsi_1_lvds>;
2108 gpr = <&lvds_region2>; 2108 gpr = <&lvds_region2>;
2109 aux-gpr = <&lvds_region1>; 2109 aux-gpr = <&lvds_region1>;
2110 status = "disabled"; 2110 status = "disabled";
2111 2111
2112 lvds-channel@0 { 2112 lvds-channel@0 {
2113 #address-cells = <1>; 2113 #address-cells = <1>;
2114 #size-cells = <0>; 2114 #size-cells = <0>;
2115 reg = <0>; 2115 reg = <0>;
2116 phys = <&ldb2_phy>, <&ldb1_phy>; 2116 phys = <&ldb2_phy>, <&ldb1_phy>;
2117 phy-names = "ldb_phy", "aux_ldb_phy"; 2117 phy-names = "ldb_phy", "aux_ldb_phy";
2118 status = "disabled"; 2118 status = "disabled";
2119 2119
2120 port@0 { 2120 port@0 {
2121 reg = <0>; 2121 reg = <0>;
2122 2122
2123 ldb2_ch0: endpoint { 2123 ldb2_ch0: endpoint {
2124 remote-endpoint = <&dpu_disp1_lvds1_ch0>; 2124 remote-endpoint = <&dpu_disp1_lvds1_ch0>;
2125 }; 2125 };
2126 }; 2126 };
2127 }; 2127 };
2128 2128
2129 lvds-channel@1 { 2129 lvds-channel@1 {
2130 #address-cells = <1>; 2130 #address-cells = <1>;
2131 #size-cells = <0>; 2131 #size-cells = <0>;
2132 reg = <1>; 2132 reg = <1>;
2133 phys = <&ldb2_phy>; 2133 phys = <&ldb2_phy>;
2134 phy-names = "ldb_phy"; 2134 phy-names = "ldb_phy";
2135 status = "disabled"; 2135 status = "disabled";
2136 2136
2137 port@0 { 2137 port@0 {
2138 reg = <0>; 2138 reg = <0>;
2139 2139
2140 ldb2_ch1: endpoint { 2140 ldb2_ch1: endpoint {
2141 remote-endpoint = <&dpu_disp1_lvds1_ch1>; 2141 remote-endpoint = <&dpu_disp1_lvds1_ch1>;
2142 }; 2142 };
2143 }; 2143 };
2144 }; 2144 };
2145 }; 2145 };
2146 2146
2147 cameradev: camera { 2147 cameradev: camera {
2148 compatible = "fsl,mxc-md", "simple-bus"; 2148 compatible = "fsl,mxc-md", "simple-bus";
2149 #address-cells = <2>; 2149 #address-cells = <2>;
2150 #size-cells = <2>; 2150 #size-cells = <2>;
2151 ranges; 2151 ranges;
2152 2152
2153 isi_0: isi@58100000 { 2153 isi_0: isi@58100000 {
2154 compatible = "fsl,imx8-isi"; 2154 compatible = "fsl,imx8-isi";
2155 reg = <0x0 0x58100000 0x0 0x10000>; 2155 reg = <0x0 0x58100000 0x0 0x10000>;
2156 interrupts = <0 297 0>; 2156 interrupts = <0 297 0>;
2157 interface = <2 0 2>; /* <Input MIPI_VCx Output> 2157 interface = <2 0 2>; /* <Input MIPI_VCx Output>
2158 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM 2158 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
2159 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only 2159 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
2160 Output: 0-DC0, 1-DC1, 2-MEM */ 2160 Output: 0-DC0, 1-DC1, 2-MEM */
2161 clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; 2161 clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
2162 clock-names = "per"; 2162 clock-names = "per";
2163 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; 2163 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>;
2164 assigned-clock-rates = <600000000>; 2164 assigned-clock-rates = <600000000>;
2165 power-domains =<&pd_isi_ch0>; 2165 power-domains =<&pd_isi_ch0>;
2166 status = "disabled"; 2166 status = "disabled";
2167 }; 2167 };
2168 2168
2169 isi_1: isi@58110000 { 2169 isi_1: isi@58110000 {
2170 compatible = "fsl,imx8-isi"; 2170 compatible = "fsl,imx8-isi";
2171 reg = <0x0 0x58110000 0x0 0x10000>; 2171 reg = <0x0 0x58110000 0x0 0x10000>;
2172 interrupts = <0 298 0>; 2172 interrupts = <0 298 0>;
2173 interface = <2 1 2>; 2173 interface = <2 1 2>;
2174 clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; 2174 clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
2175 clock-names = "per"; 2175 clock-names = "per";
2176 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; 2176 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>;
2177 assigned-clock-rates = <600000000>; 2177 assigned-clock-rates = <600000000>;
2178 power-domains =<&pd_isi_ch1>; 2178 power-domains =<&pd_isi_ch1>;
2179 status = "disabled"; 2179 status = "disabled";
2180 }; 2180 };
2181 2181
2182 isi_2: isi@58120000 { 2182 isi_2: isi@58120000 {
2183 compatible = "fsl,imx8-isi"; 2183 compatible = "fsl,imx8-isi";
2184 reg = <0x0 0x58120000 0x0 0x10000>; 2184 reg = <0x0 0x58120000 0x0 0x10000>;
2185 interrupts = <0 299 0>; 2185 interrupts = <0 299 0>;
2186 interface = <2 2 2>; 2186 interface = <2 2 2>;
2187 clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; 2187 clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
2188 clock-names = "per"; 2188 clock-names = "per";
2189 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; 2189 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>;
2190 assigned-clock-rates = <600000000>; 2190 assigned-clock-rates = <600000000>;
2191 power-domains =<&pd_isi_ch2>; 2191 power-domains =<&pd_isi_ch2>;
2192 status = "disabled"; 2192 status = "disabled";
2193 }; 2193 };
2194 2194
2195 isi_3: isi@58130000 { 2195 isi_3: isi@58130000 {
2196 compatible = "fsl,imx8-isi"; 2196 compatible = "fsl,imx8-isi";
2197 reg = <0x0 0x58130000 0x0 0x10000>; 2197 reg = <0x0 0x58130000 0x0 0x10000>;
2198 interrupts = <0 300 0>; 2198 interrupts = <0 300 0>;
2199 interface = <2 3 2>; 2199 interface = <2 3 2>;
2200 clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; 2200 clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
2201 clock-names = "per"; 2201 clock-names = "per";
2202 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; 2202 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>;
2203 assigned-clock-rates = <600000000>; 2203 assigned-clock-rates = <600000000>;
2204 power-domains =<&pd_isi_ch3>; 2204 power-domains =<&pd_isi_ch3>;
2205 status = "disabled"; 2205 status = "disabled";
2206 }; 2206 };
2207 2207
2208 isi_4: isi@58140000 { 2208 isi_4: isi@58140000 {
2209 compatible = "fsl,imx8-isi"; 2209 compatible = "fsl,imx8-isi";
2210 reg = <0x0 0x58140000 0x0 0x10000>; 2210 reg = <0x0 0x58140000 0x0 0x10000>;
2211 interrupts = <0 301 0>; 2211 interrupts = <0 301 0>;
2212 interface = <3 0 2>; 2212 interface = <3 0 2>;
2213 clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; 2213 clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
2214 clock-names = "per"; 2214 clock-names = "per";
2215 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; 2215 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>;
2216 assigned-clock-rates = <600000000>; 2216 assigned-clock-rates = <600000000>;
2217 power-domains =<&pd_isi_ch4>; 2217 power-domains =<&pd_isi_ch4>;
2218 status = "disabled"; 2218 status = "disabled";
2219 }; 2219 };
2220 2220
2221 isi_5: isi@58150000 { 2221 isi_5: isi@58150000 {
2222 compatible = "fsl,imx8-isi"; 2222 compatible = "fsl,imx8-isi";
2223 reg = <0x0 0x58150000 0x0 0x10000>; 2223 reg = <0x0 0x58150000 0x0 0x10000>;
2224 interrupts = <0 302 0>; 2224 interrupts = <0 302 0>;
2225 interface = <3 1 2>; 2225 interface = <3 1 2>;
2226 clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; 2226 clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
2227 clock-names = "per"; 2227 clock-names = "per";
2228 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; 2228 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>;
2229 assigned-clock-rates = <600000000>; 2229 assigned-clock-rates = <600000000>;
2230 power-domains =<&pd_isi_ch5>; 2230 power-domains =<&pd_isi_ch5>;
2231 status = "disabled"; 2231 status = "disabled";
2232 }; 2232 };
2233 2233
2234 isi_6: isi@58160000 { 2234 isi_6: isi@58160000 {
2235 compatible = "fsl,imx8-isi"; 2235 compatible = "fsl,imx8-isi";
2236 reg = <0x0 0x58160000 0x0 0x10000>; 2236 reg = <0x0 0x58160000 0x0 0x10000>;
2237 interrupts = <0 303 0>; 2237 interrupts = <0 303 0>;
2238 interface = <3 2 2>; 2238 interface = <3 2 2>;
2239 clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; 2239 clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
2240 clock-names = "per"; 2240 clock-names = "per";
2241 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; 2241 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>;
2242 assigned-clock-rates = <600000000>; 2242 assigned-clock-rates = <600000000>;
2243 power-domains =<&pd_isi_ch6>; 2243 power-domains =<&pd_isi_ch6>;
2244 status = "disabled"; 2244 status = "disabled";
2245 }; 2245 };
2246 2246
2247 isi_7: isi@58170000 { 2247 isi_7: isi@58170000 {
2248 compatible = "fsl,imx8-isi"; 2248 compatible = "fsl,imx8-isi";
2249 reg = <0x0 0x58170000 0x0 0x10000>; 2249 reg = <0x0 0x58170000 0x0 0x10000>;
2250 interrupts = <0 304 0>; 2250 interrupts = <0 304 0>;
2251 interface = <3 3 2>; 2251 interface = <3 3 2>;
2252 clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; 2252 clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
2253 clock-names = "per"; 2253 clock-names = "per";
2254 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; 2254 assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>;
2255 assigned-clock-rates = <600000000>; 2255 assigned-clock-rates = <600000000>;
2256 power-domains =<&pd_isi_ch7>; 2256 power-domains =<&pd_isi_ch7>;
2257 status = "disabled"; 2257 status = "disabled";
2258 }; 2258 };
2259 2259
2260 mipi_csi_0: csi@58227000 { 2260 mipi_csi_0: csi@58227000 {
2261 compatible = "fsl,mxc-mipi-csi2"; 2261 compatible = "fsl,mxc-mipi-csi2";
2262 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ 2262 reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */
2263 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ 2263 <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */
2264 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 2264 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
2265 interrupt-parent = <&irqsteer_csi>; 2265 interrupt-parent = <&irqsteer_csi>;
2266 clocks = <&clk IMX8QXP_CLK_DUMMY>, 2266 clocks = <&clk IMX8QXP_CLK_DUMMY>,
2267 <&clk IMX8QXP_CSI0_CORE_CLK>, 2267 <&clk IMX8QXP_CSI0_CORE_CLK>,
2268 <&clk IMX8QXP_CSI0_ESC_CLK>, 2268 <&clk IMX8QXP_CSI0_ESC_CLK>,
2269 <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; 2269 <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>;
2270 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; 2270 clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";
2271 assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, 2271 assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>,
2272 <&clk IMX8QXP_CSI0_ESC_CLK>; 2272 <&clk IMX8QXP_CSI0_ESC_CLK>;
2273 assigned-clock-rates = <360000000>, <72000000>; 2273 assigned-clock-rates = <360000000>, <72000000>;
2274 power-domains = <&pd_mipi_csi>; 2274 power-domains = <&pd_mipi_csi>;
2275 status = "disabled"; 2275 status = "disabled";
2276 }; 2276 };
2277 2277
2278 parallel_csi: pcsi@58261000 { 2278 parallel_csi: pcsi@58261000 {
2279 compatible = "fsl,mxc-parallel-csi"; 2279 compatible = "fsl,mxc-parallel-csi";
2280 reg = <0x0 0x58261000 0x0 0x1000>; 2280 reg = <0x0 0x58261000 0x0 0x1000>;
2281 clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>, 2281 clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>,
2282 <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>, 2282 <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>,
2283 <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, 2283 <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>,
2284 <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>, 2284 <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>,
2285 <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; 2285 <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>;
2286 clock-names = "pixel", "ipg", "sel", "div", "dpll"; 2286 clock-names = "pixel", "ipg", "sel", "div", "dpll";
2287 assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, 2287 assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>,
2288 <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>; 2288 <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>;
2289 assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; 2289 assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>;
2290 assigned-clock-rates = <0>, <160000000>; /* 160MHz */ 2290 assigned-clock-rates = <0>, <160000000>; /* 160MHz */
2291 power-domains = <&pd_parallel_csi>; 2291 power-domains = <&pd_parallel_csi>;
2292 status = "disabled"; 2292 status = "disabled";
2293 }; 2293 };
2294 2294
2295 jpegdec: jpegdec@58400000 { 2295 jpegdec: jpegdec@58400000 {
2296 compatible = "fsl,imx8-jpgdec"; 2296 compatible = "fsl,imx8-jpgdec";
2297 reg = <0x0 0x58400000 0x0 0x00040020 >; 2297 reg = <0x0 0x58400000 0x0 0x00040020 >;
2298 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2298 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2299 clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, 2299 clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >,
2300 <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; 2300 <&clk IMX8QXP_IMG_JPEG_DEC_CLK >;
2301 clock-names = "ipg", "per"; 2301 clock-names = "ipg", "per";
2302 assigned-clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, 2302 assigned-clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >,
2303 <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; 2303 <&clk IMX8QXP_IMG_JPEG_DEC_CLK >;
2304 assigned-clock-rates = <200000000>; 2304 assigned-clock-rates = <200000000>;
2305 power-domains =<&pd_jpgdec>; 2305 power-domains =<&pd_jpgdec>;
2306 status = "okay"; 2306 status = "okay";
2307 }; 2307 };
2308 2308
2309 jpegenc: jpegenc@58450000 { 2309 jpegenc: jpegenc@58450000 {
2310 compatible = "fsl,imx8-jpgenc"; 2310 compatible = "fsl,imx8-jpgenc";
2311 reg = <0x0 0x58450000 0x0 0x00240020 >; 2311 reg = <0x0 0x58450000 0x0 0x00240020 >;
2312 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2312 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2313 clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, 2313 clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >,
2314 <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; 2314 <&clk IMX8QXP_IMG_JPEG_ENC_CLK >;
2315 clock-names = "ipg", "per"; 2315 clock-names = "ipg", "per";
2316 assigned-clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, 2316 assigned-clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >,
2317 <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; 2317 <&clk IMX8QXP_IMG_JPEG_ENC_CLK >;
2318 assigned-clock-rates = <200000000>; 2318 assigned-clock-rates = <200000000>;
2319 power-domains =<&pd_jpgenc>; 2319 power-domains =<&pd_jpgenc>;
2320 status = "okay"; 2320 status = "okay";
2321 }; 2321 };
2322 }; 2322 };
2323 2323
2324 i2c_rpbus_1: i2c-rpbus-1 { 2324 i2c_rpbus_1: i2c-rpbus-1 {
2325 compatible = "fsl,i2c-rpbus"; 2325 compatible = "fsl,i2c-rpbus";
2326 status = "disabled"; 2326 status = "disabled";
2327 }; 2327 };
2328 2328
2329 i2c_rpbus_5: i2c-rpbus-5 { 2329 i2c_rpbus_5: i2c-rpbus-5 {
2330 compatible = "fsl,i2c-rpbus"; 2330 compatible = "fsl,i2c-rpbus";
2331 status = "disabled"; 2331 status = "disabled";
2332 }; 2332 };
2333 2333
2334 i2c_rpbus_12: i2c-rpbus-12 { 2334 i2c_rpbus_12: i2c-rpbus-12 {
2335 compatible = "fsl,i2c-rpbus"; 2335 compatible = "fsl,i2c-rpbus";
2336 status = "disabled"; 2336 status = "disabled";
2337 }; 2337 };
2338 2338
2339 i2c_rpbus_13: i2c-rpbus-13 { 2339 i2c_rpbus_13: i2c-rpbus-13 {
2340 compatible = "fsl,i2c-rpbus"; 2340 compatible = "fsl,i2c-rpbus";
2341 status = "disabled"; 2341 status = "disabled";
2342 }; 2342 };
2343 2343
2344 i2c_rpbus_14: i2c-rpbus-14 { 2344 i2c_rpbus_14: i2c-rpbus-14 {
2345 compatible = "fsl,i2c-rpbus"; 2345 compatible = "fsl,i2c-rpbus";
2346 status = "disabled"; 2346 status = "disabled";
2347 }; 2347 };
2348 2348
2349 i2c_rpbus_15: i2c-rpbus-15 { 2349 i2c_rpbus_15: i2c-rpbus-15 {
2350 compatible = "fsl,i2c-rpbus"; 2350 compatible = "fsl,i2c-rpbus";
2351 status = "disabled"; 2351 status = "disabled";
2352 }; 2352 };
2353 2353
2354 pwm_mipi_lvds1: pwm@56244000 { 2354 pwm_mipi_lvds1: pwm@56244000 {
2355 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 2355 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
2356 reg = <0x0 0x56244000 0 0x1000>; 2356 reg = <0x0 0x56244000 0 0x1000>;
2357 clocks = <&clk IMX8QXP_MIPI1_PWM_IPG_CLK>, 2357 clocks = <&clk IMX8QXP_MIPI1_PWM_IPG_CLK>,
2358 <&clk IMX8QXP_MIPI1_PWM_CLK>, 2358 <&clk IMX8QXP_MIPI1_PWM_CLK>,
2359 <&clk IMX8QXP_MIPI1_PWM_32K_CLK>; 2359 <&clk IMX8QXP_MIPI1_PWM_32K_CLK>;
2360 clock-names = "ipg", "per", "32k"; 2360 clock-names = "ipg", "per", "32k";
2361 assigned-clocks = <&clk IMX8QXP_MIPI1_PWM_CLK>; 2361 assigned-clocks = <&clk IMX8QXP_MIPI1_PWM_CLK>;
2362 assigned-clock-rates = <24000000>; 2362 assigned-clock-rates = <24000000>;
2363 #pwm-cells = <2>; 2363 #pwm-cells = <2>;
2364 power-domains = <&pd_mipi_1_pwm0>; 2364 power-domains = <&pd_mipi_1_pwm0>;
2365 status = "disabled"; 2365 status = "disabled";
2366 }; 2366 };
2367 2367
2368 i2c0_mipi_lvds1: i2c@56246000 { 2368 i2c0_mipi_lvds1: i2c@56246000 {
2369 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; 2369 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c";
2370 reg = <0x0 0x56246000 0x0 0x1000>; 2370 reg = <0x0 0x56246000 0x0 0x1000>;
2371 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 2371 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
2372 interrupt-parent = <&irqsteer_mipi_lvds1>; 2372 interrupt-parent = <&irqsteer_mipi_lvds1>;
2373 clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, 2373 clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>,
2374 <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; 2374 <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>;
2375 clock-names = "per", "ipg"; 2375 clock-names = "per", "ipg";
2376 assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; 2376 assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>;
2377 assigned-clock-rates = <24000000>; 2377 assigned-clock-rates = <24000000>;
2378 power-domains = <&pd_mipi_dsi_1_i2c0>; 2378 power-domains = <&pd_mipi_dsi_1_i2c0>;
2379 #address-cells = <1>; 2379 #address-cells = <1>;
2380 #size-cells = <0>; 2380 #size-cells = <0>;
2381 status = "disabled"; 2381 status = "disabled";
2382 }; 2382 };
2383 2383
2384 adc0: adc@5a880000 { 2384 adc0: adc@5a880000 {
2385 compatible = "fsl,imx8qxp-adc"; 2385 compatible = "fsl,imx8qxp-adc";
2386 reg = <0x0 0x5a880000 0x0 0x10000>; 2386 reg = <0x0 0x5a880000 0x0 0x10000>;
2387 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 2387 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
2388 interrupt-parent = <&gic>; 2388 interrupt-parent = <&gic>;
2389 clocks = <&clk IMX8QXP_ADC0_CLK>, 2389 clocks = <&clk IMX8QXP_ADC0_CLK>,
2390 <&clk IMX8QXP_ADC0_IPG_CLK>; 2390 <&clk IMX8QXP_ADC0_IPG_CLK>;
2391 clock-names = "per", "ipg"; 2391 clock-names = "per", "ipg";
2392 assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; 2392 assigned-clocks = <&clk IMX8QXP_ADC0_CLK>;
2393 assigned-clock-rates = <24000000>; 2393 assigned-clock-rates = <24000000>;
2394 power-domains = <&pd_dma_adc0>; 2394 power-domains = <&pd_dma_adc0>;
2395 status = "disabled"; 2395 status = "disabled";
2396 }; 2396 };
2397 2397
2398 i2c0: i2c@5a800000 { 2398 i2c0: i2c@5a800000 {
2399 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 2399 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
2400 reg = <0x0 0x5a800000 0x0 0x4000>; 2400 reg = <0x0 0x5a800000 0x0 0x4000>;
2401 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2401 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2402 interrupt-parent = <&gic>; 2402 interrupt-parent = <&gic>;
2403 clocks = <&clk IMX8QXP_I2C0_CLK>, 2403 clocks = <&clk IMX8QXP_I2C0_CLK>,
2404 <&clk IMX8QXP_I2C0_IPG_CLK>; 2404 <&clk IMX8QXP_I2C0_IPG_CLK>;
2405 clock-names = "per", "ipg"; 2405 clock-names = "per", "ipg";
2406 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; 2406 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
2407 assigned-clock-rates = <24000000>; 2407 assigned-clock-rates = <24000000>;
2408 power-domains = <&pd_dma_lpi2c0>; 2408 power-domains = <&pd_dma_lpi2c0>;
2409 #address-cells = <1>; 2409 #address-cells = <1>;
2410 #size-cells = <0>; 2410 #size-cells = <0>;
2411 status = "disabled"; 2411 status = "disabled";
2412 }; 2412 };
2413 2413
2414 i2c1: i2c@5a810000 { 2414 i2c1: i2c@5a810000 {
2415 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 2415 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
2416 reg = <0x0 0x5a810000 0x0 0x4000>; 2416 reg = <0x0 0x5a810000 0x0 0x4000>;
2417 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2417 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2418 interrupt-parent = <&gic>; 2418 interrupt-parent = <&gic>;
2419 clocks = <&clk IMX8QXP_I2C1_CLK>, 2419 clocks = <&clk IMX8QXP_I2C1_CLK>,
2420 <&clk IMX8QXP_I2C1_IPG_CLK>; 2420 <&clk IMX8QXP_I2C1_IPG_CLK>;
2421 clock-names = "per", "ipg"; 2421 clock-names = "per", "ipg";
2422 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; 2422 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
2423 assigned-clock-rates = <24000000>; 2423 assigned-clock-rates = <24000000>;
2424 power-domains = <&pd_dma_lpi2c1>; 2424 power-domains = <&pd_dma_lpi2c1>;
2425 #address-cells = <1>; 2425 #address-cells = <1>;
2426 #size-cells = <0>; 2426 #size-cells = <0>;
2427 status = "disabled"; 2427 status = "disabled";
2428 }; 2428 };
2429 2429
2430 i2c2: i2c@5a820000 { 2430 i2c2: i2c@5a820000 {
2431 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 2431 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
2432 reg = <0x0 0x5a820000 0x0 0x4000>; 2432 reg = <0x0 0x5a820000 0x0 0x4000>;
2433 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2433 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2434 interrupt-parent = <&gic>; 2434 interrupt-parent = <&gic>;
2435 clocks = <&clk IMX8QXP_I2C2_CLK>, 2435 clocks = <&clk IMX8QXP_I2C2_CLK>,
2436 <&clk IMX8QXP_I2C2_IPG_CLK>; 2436 <&clk IMX8QXP_I2C2_IPG_CLK>;
2437 clock-names = "per", "ipg"; 2437 clock-names = "per", "ipg";
2438 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; 2438 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
2439 assigned-clock-rates = <24000000>; 2439 assigned-clock-rates = <24000000>;
2440 power-domains = <&pd_dma_lpi2c2>; 2440 power-domains = <&pd_dma_lpi2c2>;
2441 #address-cells = <1>; 2441 #address-cells = <1>;
2442 #size-cells = <0>; 2442 #size-cells = <0>;
2443 status = "disabled"; 2443 status = "disabled";
2444 }; 2444 };
2445 2445
2446 i2c3: i2c@5a830000 { 2446 i2c3: i2c@5a830000 {
2447 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 2447 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
2448 reg = <0x0 0x5a830000 0x0 0x4000>; 2448 reg = <0x0 0x5a830000 0x0 0x4000>;
2449 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2449 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
2450 interrupt-parent = <&gic>; 2450 interrupt-parent = <&gic>;
2451 clocks = <&clk IMX8QXP_I2C3_CLK>, 2451 clocks = <&clk IMX8QXP_I2C3_CLK>,
2452 <&clk IMX8QXP_I2C3_IPG_CLK>; 2452 <&clk IMX8QXP_I2C3_IPG_CLK>;
2453 clock-names = "per", "ipg"; 2453 clock-names = "per", "ipg";
2454 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; 2454 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
2455 assigned-clock-rates = <24000000>; 2455 assigned-clock-rates = <24000000>;
2456 power-domains = <&pd_dma_lpi2c3>; 2456 power-domains = <&pd_dma_lpi2c3>;
2457 #address-cells = <1>; 2457 #address-cells = <1>;
2458 #size-cells = <0>; 2458 #size-cells = <0>;
2459 status = "disabled"; 2459 status = "disabled";
2460 }; 2460 };
2461 2461
2462 usbmisc1: usbmisc@5b0d0200 { 2462 usbmisc1: usbmisc@5b0d0200 {
2463 #index-cells = <1>; 2463 #index-cells = <1>;
2464 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 2464 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
2465 reg = <0x0 0x5b0d0200 0x0 0x200>; 2465 reg = <0x0 0x5b0d0200 0x0 0x200>;
2466 }; 2466 };
2467 2467
2468 usbphy1: usbphy@0x5b100000 { 2468 usbphy1: usbphy@0x5b100000 {
2469 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 2469 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
2470 reg = <0x0 0x5b100000 0x0 0x1000>; 2470 reg = <0x0 0x5b100000 0x0 0x1000>;
2471 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; 2471 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
2472 power-domains = <&pd_conn_usbotg0_phy>; 2472 power-domains = <&pd_conn_usbotg0_phy>;
2473 }; 2473 };
2474 2474
2475 usbotg1: usb@5b0d0000 { 2475 usbotg1: usb@5b0d0000 {
2476 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; 2476 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
2477 reg = <0x0 0x5b0d0000 0x0 0x200>; 2477 reg = <0x0 0x5b0d0000 0x0 0x200>;
2478 interrupt-parent = <&wu>; 2478 interrupt-parent = <&wu>;
2479 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 2479 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
2480 fsl,usbphy = <&usbphy1>; 2480 fsl,usbphy = <&usbphy1>;
2481 fsl,usbmisc = <&usbmisc1 0>; 2481 fsl,usbmisc = <&usbmisc1 0>;
2482 clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; 2482 clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>;
2483 ahb-burst-config = <0x0>; 2483 ahb-burst-config = <0x0>;
2484 tx-burst-size-dword = <0x10>; 2484 tx-burst-size-dword = <0x10>;
2485 rx-burst-size-dword = <0x10>; 2485 rx-burst-size-dword = <0x10>;
2486 #stream-id-cells = <1>; 2486 #stream-id-cells = <1>;
2487 power-domains = <&pd_conn_usbotg0>; 2487 power-domains = <&pd_conn_usbotg0>;
2488 status = "disabled"; 2488 status = "disabled";
2489 }; 2489 };
2490 2490
2491 flexcan1: can@5a8d0000 { 2491 flexcan1: can@5a8d0000 {
2492 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 2492 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
2493 reg = <0x0 0x5a8d0000 0x0 0x10000>; 2493 reg = <0x0 0x5a8d0000 0x0 0x10000>;
2494 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 2494 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
2495 interrupt-parent = <&wu>; 2495 interrupt-parent = <&wu>;
2496 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 2496 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
2497 <&clk IMX8QXP_CAN0_CLK>; 2497 <&clk IMX8QXP_CAN0_CLK>;
2498 clock-names = "ipg", "per"; 2498 clock-names = "ipg", "per";
2499 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 2499 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
2500 assigned-clock-rates = <40000000>; 2500 assigned-clock-rates = <40000000>;
2501 power-domains = <&pd_dma_flexcan0>; 2501 power-domains = <&pd_dma_flexcan0>;
2502 /* SLSlice[4] */ 2502 /* SLSlice[4] */
2503 clk-src = <0>; 2503 clk-src = <0>;
2504 status = "disabled"; 2504 status = "disabled";
2505 }; 2505 };
2506 2506
2507 flexcan2: can@5a8e0000 { 2507 flexcan2: can@5a8e0000 {
2508 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 2508 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
2509 reg = <0x0 0x5a8e0000 0x0 0x10000>; 2509 reg = <0x0 0x5a8e0000 0x0 0x10000>;
2510 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 2510 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
2511 interrupt-parent = <&wu>; 2511 interrupt-parent = <&wu>;
2512 /* CAN0 clock and PD is shared among all CAN instances */ 2512 /* CAN0 clock and PD is shared among all CAN instances */
2513 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 2513 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
2514 <&clk IMX8QXP_CAN0_CLK>; 2514 <&clk IMX8QXP_CAN0_CLK>;
2515 clock-names = "ipg", "per"; 2515 clock-names = "ipg", "per";
2516 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 2516 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
2517 assigned-clock-rates = <40000000>; 2517 assigned-clock-rates = <40000000>;
2518 power-domains = <&pd_dma_flexcan1>; 2518 power-domains = <&pd_dma_flexcan1>;
2519 /* SLSlice[4] */ 2519 /* SLSlice[4] */
2520 clk-src = <0>; 2520 clk-src = <0>;
2521 status = "disabled"; 2521 status = "disabled";
2522 }; 2522 };
2523 2523
2524 flexcan3: can@5a8f0000 { 2524 flexcan3: can@5a8f0000 {
2525 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 2525 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
2526 reg = <0x0 0x5a8f0000 0x0 0x10000>; 2526 reg = <0x0 0x5a8f0000 0x0 0x10000>;
2527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 2527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
2528 interrupt-parent = <&wu>; 2528 interrupt-parent = <&wu>;
2529 /* CAN0 clock and PD is shared among all CAN instances */ 2529 /* CAN0 clock and PD is shared among all CAN instances */
2530 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 2530 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
2531 <&clk IMX8QXP_CAN0_CLK>; 2531 <&clk IMX8QXP_CAN0_CLK>;
2532 clock-names = "ipg", "per"; 2532 clock-names = "ipg", "per";
2533 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 2533 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
2534 assigned-clock-rates = <40000000>; 2534 assigned-clock-rates = <40000000>;
2535 power-domains = <&pd_dma_flexcan2>; 2535 power-domains = <&pd_dma_flexcan2>;
2536 /* SLSlice[4] */ 2536 /* SLSlice[4] */
2537 clk-src = <0>; 2537 clk-src = <0>;
2538 status = "disabled"; 2538 status = "disabled";
2539 }; 2539 };
2540 2540
2541 dma_apbh: dma-apbh@5b810000 { 2541 dma_apbh: dma-apbh@5b810000 {
2542 compatible = "fsl,imx28-dma-apbh"; 2542 compatible = "fsl,imx28-dma-apbh";
2543 reg = <0x0 0x5b810000 0x0 0x2000>; 2543 reg = <0x0 0x5b810000 0x0 0x2000>;
2544 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2544 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2545 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2546 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
2547 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 2547 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
2548 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 2548 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
2549 #dma-cells = <1>; 2549 #dma-cells = <1>;
2550 dma-channels = <4>; 2550 dma-channels = <4>;
2551 clocks = <&clk IMX8QXP_APBHDMA_CLK>; 2551 clocks = <&clk IMX8QXP_APBHDMA_CLK>;
2552 power-domains = <&pd_conn_nand>; 2552 power-domains = <&pd_conn_nand>;
2553 }; 2553 };
2554 2554
2555 gpmi: gpmi-nand@5b812000{ 2555 gpmi: gpmi-nand@5b812000{
2556 compatible = "fsl,imx8qxp-gpmi-nand"; 2556 compatible = "fsl,imx8qxp-gpmi-nand";
2557 #address-cells = <1>; 2557 #address-cells = <1>;
2558 #size-cells = <1>; 2558 #size-cells = <1>;
2559 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; 2559 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>;
2560 reg-names = "gpmi-nand", "bch"; 2560 reg-names = "gpmi-nand", "bch";
2561 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2561 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
2562 interrupt-names = "bch"; 2562 interrupt-names = "bch";
2563 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, 2563 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>,
2564 <&clk IMX8QXP_GPMI_APB_CLK>, 2564 <&clk IMX8QXP_GPMI_APB_CLK>,
2565 <&clk IMX8QXP_GPMI_BCH_CLK>, 2565 <&clk IMX8QXP_GPMI_BCH_CLK>,
2566 <&clk IMX8QXP_GPMI_APB_BCH_CLK>, 2566 <&clk IMX8QXP_GPMI_APB_BCH_CLK>,
2567 <&clk IMX8QXP_APBHDMA_CLK>; 2567 <&clk IMX8QXP_APBHDMA_CLK>;
2568 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma"; 2568 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma";
2569 dmas = <&dma_apbh 0>; 2569 dmas = <&dma_apbh 0>;
2570 dma-names = "rx-tx"; 2570 dma-names = "rx-tx";
2571 power-domains = <&pd_conn_nand>; 2571 power-domains = <&pd_conn_nand>;
2572 assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; 2572 assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>;
2573 assigned-clock-rates = <50000000>; 2573 assigned-clock-rates = <50000000>;
2574 status = "disabled"; 2574 status = "disabled";
2575 }; 2575 };
2576 2576
2577 usbphynop1: usbphynop1 { 2577 usbphynop1: usbphynop1 {
2578 compatible = "usb-nop-xceiv"; 2578 compatible = "usb-nop-xceiv";
2579 clocks = <&clk IMX8QXP_USB3_PHY_CLK>; 2579 clocks = <&clk IMX8QXP_USB3_PHY_CLK>;
2580 clock-names = "main_clk"; 2580 clock-names = "main_clk";
2581 power-domains = <&pd_conn_usb2_phy>; 2581 power-domains = <&pd_conn_usb2_phy>;
2582 }; 2582 };
2583 2583
2584 usbotg3: usb3@5b110000 { 2584 usbotg3: usb3@5b110000 {
2585 compatible = "Cadence,usb3"; 2585 compatible = "Cadence,usb3";
2586 reg = <0x0 0x5B110000 0x0 0x10000>, 2586 reg = <0x0 0x5B110000 0x0 0x10000>,
2587 <0x0 0x5B130000 0x0 0x10000>, 2587 <0x0 0x5B130000 0x0 0x10000>,
2588 <0x0 0x5B140000 0x0 0x10000>, 2588 <0x0 0x5B140000 0x0 0x10000>,
2589 <0x0 0x5B160000 0x0 0x40000>, 2589 <0x0 0x5B160000 0x0 0x40000>,
2590 <0x0 0x5B120000 0x0 0x10000>; 2590 <0x0 0x5B120000 0x0 0x10000>;
2591 reg-names = "none-core", "xhci", "dev", "phy", "otg"; 2591 reg-names = "none-core", "xhci", "dev", "phy", "otg";
2592 interrupt-parent = <&wu>; 2592 interrupt-parent = <&wu>;
2593 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; 2593 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
2594 clocks = <&clk IMX8QXP_USB3_LPM_CLK>, 2594 clocks = <&clk IMX8QXP_USB3_LPM_CLK>,
2595 <&clk IMX8QXP_USB3_BUS_CLK>, 2595 <&clk IMX8QXP_USB3_BUS_CLK>,
2596 <&clk IMX8QXP_USB3_ACLK>, 2596 <&clk IMX8QXP_USB3_ACLK>,
2597 <&clk IMX8QXP_USB3_IPG_CLK>, 2597 <&clk IMX8QXP_USB3_IPG_CLK>,
2598 <&clk IMX8QXP_USB3_CORE_PCLK>; 2598 <&clk IMX8QXP_USB3_CORE_PCLK>;
2599 clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", 2599 clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
2600 "usb3_ipg_clk", "usb3_core_pclk"; 2600 "usb3_ipg_clk", "usb3_core_pclk";
2601 assigned-clocks = <&clk IMX8QXP_USB3_ACLK_DIV>, 2601 assigned-clocks = <&clk IMX8QXP_USB3_ACLK_DIV>,
2602 <&clk IMX8QXP_USB3_LPM_DIV>, 2602 <&clk IMX8QXP_USB3_LPM_DIV>,
2603 <&clk IMX8QXP_USB3_BUS_DIV>; 2603 <&clk IMX8QXP_USB3_BUS_DIV>;
2604 assigned-clock-rates = <125000000>, <12000000>, <250000000>; 2604 assigned-clock-rates = <125000000>, <12000000>, <250000000>;
2605 power-domains = <&pd_conn_usb2>; 2605 power-domains = <&pd_conn_usb2>;
2606 cdns3,usbphy = <&usbphynop1>; 2606 cdns3,usbphy = <&usbphynop1>;
2607 status = "disabled"; 2607 status = "disabled";
2608 }; 2608 };
2609 2609
2610 wu: wu { 2610 wu: wu {
2611 compatible = "fsl,imx8-wu"; 2611 compatible = "fsl,imx8-wu";
2612 interrupt-controller; 2612 interrupt-controller;
2613 #interrupt-cells = <3>; 2613 #interrupt-cells = <3>;
2614 interrupt-parent = <&gic>; 2614 interrupt-parent = <&gic>;
2615 }; 2615 };
2616 2616
2617 gpio0: gpio@5d080000 { 2617 gpio0: gpio@5d080000 {
2618 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2618 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2619 reg = <0x0 0x5d080000 0x0 0x10000>; 2619 reg = <0x0 0x5d080000 0x0 0x10000>;
2620 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2620 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
2621 gpio-controller; 2621 gpio-controller;
2622 #gpio-cells = <2>; 2622 #gpio-cells = <2>;
2623 power-domains = <&pd_lsio_gpio0>; 2623 power-domains = <&pd_lsio_gpio0>;
2624 interrupt-controller; 2624 interrupt-controller;
2625 #interrupt-cells = <2>; 2625 #interrupt-cells = <2>;
2626 }; 2626 };
2627 2627
2628 gpio1: gpio@5d090000 { 2628 gpio1: gpio@5d090000 {
2629 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2629 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2630 reg = <0x0 0x5d090000 0x0 0x10000>; 2630 reg = <0x0 0x5d090000 0x0 0x10000>;
2631 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2631 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
2632 gpio-controller; 2632 gpio-controller;
2633 #gpio-cells = <2>; 2633 #gpio-cells = <2>;
2634 power-domains = <&pd_lsio_gpio1>; 2634 power-domains = <&pd_lsio_gpio1>;
2635 interrupt-controller; 2635 interrupt-controller;
2636 #interrupt-cells = <2>; 2636 #interrupt-cells = <2>;
2637 }; 2637 };
2638 2638
2639 gpio2: gpio@5d0a0000 { 2639 gpio2: gpio@5d0a0000 {
2640 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2640 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2641 reg = <0x0 0x5d0a0000 0x0 0x10000>; 2641 reg = <0x0 0x5d0a0000 0x0 0x10000>;
2642 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2642 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
2643 gpio-controller; 2643 gpio-controller;
2644 #gpio-cells = <2>; 2644 #gpio-cells = <2>;
2645 power-domains = <&pd_lsio_gpio2>; 2645 power-domains = <&pd_lsio_gpio2>;
2646 interrupt-controller; 2646 interrupt-controller;
2647 #interrupt-cells = <2>; 2647 #interrupt-cells = <2>;
2648 }; 2648 };
2649 2649
2650 gpio3: gpio@5d0b0000 { 2650 gpio3: gpio@5d0b0000 {
2651 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2651 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2652 reg = <0x0 0x5d0b0000 0x0 0x10000>; 2652 reg = <0x0 0x5d0b0000 0x0 0x10000>;
2653 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 2653 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
2654 gpio-controller; 2654 gpio-controller;
2655 #gpio-cells = <2>; 2655 #gpio-cells = <2>;
2656 power-domains = <&pd_lsio_gpio3>; 2656 power-domains = <&pd_lsio_gpio3>;
2657 interrupt-controller; 2657 interrupt-controller;
2658 #interrupt-cells = <2>; 2658 #interrupt-cells = <2>;
2659 }; 2659 };
2660 2660
2661 gpio4: gpio@5d0c0000 { 2661 gpio4: gpio@5d0c0000 {
2662 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2662 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2663 reg = <0x0 0x5d0c0000 0x0 0x10000>; 2663 reg = <0x0 0x5d0c0000 0x0 0x10000>;
2664 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2664 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2665 gpio-controller; 2665 gpio-controller;
2666 #gpio-cells = <2>; 2666 #gpio-cells = <2>;
2667 power-domains = <&pd_lsio_gpio4>; 2667 power-domains = <&pd_lsio_gpio4>;
2668 interrupt-controller; 2668 interrupt-controller;
2669 #interrupt-cells = <2>; 2669 #interrupt-cells = <2>;
2670 }; 2670 };
2671 2671
2672 gpio5: gpio@5d0d0000 { 2672 gpio5: gpio@5d0d0000 {
2673 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2673 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2674 reg = <0x0 0x5d0d0000 0x0 0x10000>; 2674 reg = <0x0 0x5d0d0000 0x0 0x10000>;
2675 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 2675 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
2676 gpio-controller; 2676 gpio-controller;
2677 #gpio-cells = <2>; 2677 #gpio-cells = <2>;
2678 power-domains = <&pd_lsio_gpio5>; 2678 power-domains = <&pd_lsio_gpio5>;
2679 interrupt-controller; 2679 interrupt-controller;
2680 #interrupt-cells = <2>; 2680 #interrupt-cells = <2>;
2681 }; 2681 };
2682 2682
2683 gpio6: gpio@5d0e0000 { 2683 gpio6: gpio@5d0e0000 {
2684 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2684 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2685 reg = <0x0 0x5d0e0000 0x0 0x10000>; 2685 reg = <0x0 0x5d0e0000 0x0 0x10000>;
2686 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 2686 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
2687 gpio-controller; 2687 gpio-controller;
2688 #gpio-cells = <2>; 2688 #gpio-cells = <2>;
2689 power-domains = <&pd_lsio_gpio6>; 2689 power-domains = <&pd_lsio_gpio6>;
2690 interrupt-controller; 2690 interrupt-controller;
2691 #interrupt-cells = <2>; 2691 #interrupt-cells = <2>;
2692 }; 2692 };
2693 2693
2694 gpio7: gpio@5d0f0000 { 2694 gpio7: gpio@5d0f0000 {
2695 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2695 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2696 reg = <0x0 0x5d0f0000 0x0 0x10000>; 2696 reg = <0x0 0x5d0f0000 0x0 0x10000>;
2697 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 2697 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
2698 gpio-controller; 2698 gpio-controller;
2699 #gpio-cells = <2>; 2699 #gpio-cells = <2>;
2700 power-domains = <&pd_lsio_gpio7>; 2700 power-domains = <&pd_lsio_gpio7>;
2701 interrupt-controller; 2701 interrupt-controller;
2702 #interrupt-cells = <2>; 2702 #interrupt-cells = <2>;
2703 }; 2703 };
2704 2704
2705 gpio0_mipi_csi0: gpio@58222000 { 2705 gpio0_mipi_csi0: gpio@58222000 {
2706 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 2706 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
2707 reg = <0x0 0x58222000 0x0 0x1000>; 2707 reg = <0x0 0x58222000 0x0 0x1000>;
2708 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2708 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2709 interrupt-parent = <&irqsteer_csi>; 2709 interrupt-parent = <&irqsteer_csi>;
2710 gpio-controller; 2710 gpio-controller;
2711 #gpio-cells = <2>; 2711 #gpio-cells = <2>;
2712 interrupt-controller; 2712 interrupt-controller;
2713 #interrupt-cells = <2>; 2713 #interrupt-cells = <2>;
2714 power-domains = <&pd_mipi_csi>; 2714 power-domains = <&pd_mipi_csi>;
2715 }; 2715 };
2716 2716
2717 gpu_3d0: gpu@53100000 { 2717 gpu_3d0: gpu@53100000 {
2718 compatible = "fsl,imx8-gpu"; 2718 compatible = "fsl,imx8-gpu";
2719 reg = <0x0 0x53100000 0 0x40000>; 2719 reg = <0x0 0x53100000 0 0x40000>;
2720 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 2720 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
2721 clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; 2721 clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
2722 clock-names = "core", "shader"; 2722 clock-names = "core", "shader";
2723 assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; 2723 assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>;
2724 assigned-clock-rates = <700000000>, <850000000>; 2724 assigned-clock-rates = <700000000>, <850000000>;
2725 power-domains = <&pd_gpu0>; 2725 power-domains = <&pd_gpu0>;
2726 status = "disabled"; 2726 status = "disabled";
2727 }; 2727 };
2728 2728
2729 imx8_gpu_ss: imx8_gpu_ss { 2729 imx8_gpu_ss: imx8_gpu_ss {
2730 compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; 2730 compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
2731 cores = <&gpu_3d0>; 2731 cores = <&gpu_3d0>;
2732 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; 2732 reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
2733 reg-names = "phys_baseaddr", "contiguous_mem"; 2733 reg-names = "phys_baseaddr", "contiguous_mem";
2734 status = "disabled"; 2734 status = "disabled";
2735 }; 2735 };
2736 2736
2737 ddr_pmu0: ddr_pmu@5c020000 { 2737 ddr_pmu0: ddr_pmu@5c020000 {
2738 compatible = "fsl,imx8-ddr-pmu"; 2738 compatible = "fsl,imx8-ddr-pmu";
2739 reg = <0x0 0x5c020000 0x0 0x10000>; 2739 reg = <0x0 0x5c020000 0x0 0x10000>;
2740 interrupt-parent = <&gic>; 2740 interrupt-parent = <&gic>;
2741 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2741 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2742 }; 2742 };
2743 2743
2744 lpspi0: lpspi@5a000000 { 2744 lpspi0: lpspi@5a000000 {
2745 compatible = "fsl,imx7ulp-spi"; 2745 compatible = "fsl,imx7ulp-spi";
2746 reg = <0x0 0x5a000000 0x0 0x10000>; 2746 reg = <0x0 0x5a000000 0x0 0x10000>;
2747 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2747 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
2748 interrupt-parent = <&gic>; 2748 interrupt-parent = <&gic>;
2749 clocks = <&clk IMX8QXP_SPI0_CLK>, 2749 clocks = <&clk IMX8QXP_SPI0_CLK>,
2750 <&clk IMX8QXP_SPI0_IPG_CLK>; 2750 <&clk IMX8QXP_SPI0_IPG_CLK>;
2751 clock-names = "per", "ipg"; 2751 clock-names = "per", "ipg";
2752 assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; 2752 assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
2753 assigned-clock-rates = <20000000>; 2753 assigned-clock-rates = <20000000>;
2754 power-domains = <&pd_dma_lpspi0>; 2754 power-domains = <&pd_dma_lpspi0>;
2755 status = "disabled"; 2755 status = "disabled";
2756 }; 2756 };
2757 2757
2758 lpspi2: lpspi@5a020000 { 2758 lpspi2: lpspi@5a020000 {
2759 compatible = "fsl,imx7ulp-spi"; 2759 compatible = "fsl,imx7ulp-spi";
2760 reg = <0x0 0x5a020000 0x0 0x10000>; 2760 reg = <0x0 0x5a020000 0x0 0x10000>;
2761 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2761 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2762 interrupt-parent = <&gic>; 2762 interrupt-parent = <&gic>;
2763 clocks = <&clk IMX8QXP_SPI2_CLK>, 2763 clocks = <&clk IMX8QXP_SPI2_CLK>,
2764 <&clk IMX8QXP_SPI2_IPG_CLK>; 2764 <&clk IMX8QXP_SPI2_IPG_CLK>;
2765 clock-names = "per", "ipg"; 2765 clock-names = "per", "ipg";
2766 assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; 2766 assigned-clocks = <&clk IMX8QXP_SPI2_CLK>;
2767 assigned-clock-rates = <20000000>; 2767 assigned-clock-rates = <20000000>;
2768 power-domains = <&pd_dma_lpspi2>; 2768 power-domains = <&pd_dma_lpspi2>;
2769 status = "disabled"; 2769 status = "disabled";
2770 }; 2770 };
2771 2771
2772 lpuart0: serial@5a060000 { 2772 lpuart0: serial@5a060000 {
2773 compatible = "fsl,imx8qm-lpuart"; 2773 compatible = "fsl,imx8qm-lpuart";
2774 reg = <0x0 0x5a060000 0x0 0x1000>; 2774 reg = <0x0 0x5a060000 0x0 0x1000>;
2775 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 2775 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
2776 interrupt-parent = <&wu>; 2776 interrupt-parent = <&wu>;
2777 clocks = <&clk IMX8QXP_UART0_CLK>, 2777 clocks = <&clk IMX8QXP_UART0_CLK>,
2778 <&clk IMX8QXP_UART0_IPG_CLK>; 2778 <&clk IMX8QXP_UART0_IPG_CLK>;
2779 clock-names = "per", "ipg"; 2779 clock-names = "per", "ipg";
2780 assigned-clocks = <&clk IMX8QXP_UART0_CLK>; 2780 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
2781 assigned-clock-rates = <80000000>; 2781 assigned-clock-rates = <80000000>;
2782 power-domains = <&pd_dma_lpuart0>; 2782 power-domains = <&pd_dma_lpuart0>;
2783 status = "disabled"; 2783 status = "disabled";
2784 }; 2784 };
2785 2785
2786 lpuart1: serial@5a070000 { 2786 lpuart1: serial@5a070000 {
2787 compatible = "fsl,imx8qm-lpuart"; 2787 compatible = "fsl,imx8qm-lpuart";
2788 reg = <0x0 0x5a070000 0x0 0x1000>; 2788 reg = <0x0 0x5a070000 0x0 0x1000>;
2789 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 2789 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
2790 interrupt-parent = <&wu>; 2790 interrupt-parent = <&wu>;
2791 clocks = <&clk IMX8QXP_UART1_CLK>, 2791 clocks = <&clk IMX8QXP_UART1_CLK>,
2792 <&clk IMX8QXP_UART1_IPG_CLK>; 2792 <&clk IMX8QXP_UART1_IPG_CLK>;
2793 clock-names = "per", "ipg"; 2793 clock-names = "per", "ipg";
2794 assigned-clocks = <&clk IMX8QXP_UART1_CLK>; 2794 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
2795 assigned-clock-rates = <80000000>; 2795 assigned-clock-rates = <80000000>;
2796 power-domains = <&pd_dma2_chan11>; 2796 power-domains = <&pd_dma2_chan11>;
2797 dma-names = "tx","rx"; 2797 dma-names = "tx","rx";
2798 dmas = <&edma2 11 0 0>, 2798 dmas = <&edma2 11 0 0>,
2799 <&edma2 10 0 1>; 2799 <&edma2 10 0 1>;
2800 status = "disabled"; 2800 status = "disabled";
2801 }; 2801 };
2802 2802
2803 lpuart2: serial@5a080000 { 2803 lpuart2: serial@5a080000 {
2804 compatible = "fsl,imx8qm-lpuart"; 2804 compatible = "fsl,imx8qm-lpuart";
2805 reg = <0x0 0x5a080000 0x0 0x1000>; 2805 reg = <0x0 0x5a080000 0x0 0x1000>;
2806 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 2806 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
2807 interrupt-parent = <&wu>; 2807 interrupt-parent = <&wu>;
2808 clocks = <&clk IMX8QXP_UART2_CLK>, 2808 clocks = <&clk IMX8QXP_UART2_CLK>,
2809 <&clk IMX8QXP_UART2_IPG_CLK>; 2809 <&clk IMX8QXP_UART2_IPG_CLK>;
2810 clock-names = "per", "ipg"; 2810 clock-names = "per", "ipg";
2811 assigned-clocks = <&clk IMX8QXP_UART2_CLK>; 2811 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
2812 assigned-clock-rates = <80000000>; 2812 assigned-clock-rates = <80000000>;
2813 power-domains = <&pd_dma2_chan13>; 2813 power-domains = <&pd_dma2_chan13>;
2814 dma-names = "tx","rx"; 2814 dma-names = "tx","rx";
2815 dmas = <&edma2 13 0 0>, 2815 dmas = <&edma2 13 0 0>,
2816 <&edma2 12 0 1>; 2816 <&edma2 12 0 1>;
2817 status = "disabled"; 2817 status = "disabled";
2818 }; 2818 };
2819 2819
2820 lpuart3: serial@5a090000 { 2820 lpuart3: serial@5a090000 {
2821 compatible = "fsl,imx8qm-lpuart"; 2821 compatible = "fsl,imx8qm-lpuart";
2822 reg = <0x0 0x5a090000 0x0 0x1000>; 2822 reg = <0x0 0x5a090000 0x0 0x1000>;
2823 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 2823 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
2824 interrupt-parent = <&wu>; 2824 interrupt-parent = <&wu>;
2825 clocks = <&clk IMX8QXP_UART3_CLK>, 2825 clocks = <&clk IMX8QXP_UART3_CLK>,
2826 <&clk IMX8QXP_UART3_IPG_CLK>; 2826 <&clk IMX8QXP_UART3_IPG_CLK>;
2827 clock-names = "per", "ipg"; 2827 clock-names = "per", "ipg";
2828 assigned-clocks = <&clk IMX8QXP_UART3_CLK>; 2828 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
2829 assigned-clock-rates = <80000000>; 2829 assigned-clock-rates = <80000000>;
2830 power-domains = <&pd_dma3_chan15>; 2830 power-domains = <&pd_dma3_chan15>;
2831 dma-names = "tx","rx"; 2831 dma-names = "tx","rx";
2832 dmas = <&edma2 15 0 0>, 2832 dmas = <&edma2 15 0 0>,
2833 <&edma2 14 0 1>; 2833 <&edma2 14 0 1>;
2834 status = "disabled"; 2834 status = "disabled";
2835 }; 2835 };
2836 2836
2837 edma2: dma-controller@5a1f0000 { 2837 edma2: dma-controller@5a1f0000 {
2838 compatible = "fsl,imx8qm-edma"; 2838 compatible = "fsl,imx8qm-edma";
2839 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ 2839 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
2840 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ 2840 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
2841 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ 2841 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
2842 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ 2842 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
2843 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ 2843 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
2844 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ 2844 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
2845 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ 2845 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
2846 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ 2846 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
2847 #dma-cells = <3>; 2847 #dma-cells = <3>;
2848 dma-channels = <8>; 2848 dma-channels = <8>;
2849 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2849 interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2850 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2851 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
2852 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
2853 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
2854 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
2855 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
2856 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; 2856 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
2857 interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", 2857 interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
2858 "edma2-chan10-rx", "edma2-chan11-tx", 2858 "edma2-chan10-rx", "edma2-chan11-tx",
2859 "edma2-chan12-rx", "edma2-chan13-tx", 2859 "edma2-chan12-rx", "edma2-chan13-tx",
2860 "edma2-chan14-rx", "edma2-chan15-tx"; 2860 "edma2-chan14-rx", "edma2-chan15-tx";
2861 status = "okay"; 2861 status = "okay";
2862 }; 2862 };
2863 2863
2864 edma0: dma-controller@591F0000 { 2864 edma0: dma-controller@591F0000 {
2865 compatible = "fsl,imx8qm-edma"; 2865 compatible = "fsl,imx8qm-edma";
2866 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ 2866 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
2867 <0x0 0x59210000 0x0 0x10000>, 2867 <0x0 0x59210000 0x0 0x10000>,
2868 <0x0 0x59220000 0x0 0x10000>, 2868 <0x0 0x59220000 0x0 0x10000>,
2869 <0x0 0x59230000 0x0 0x10000>, 2869 <0x0 0x59230000 0x0 0x10000>,
2870 <0x0 0x59240000 0x0 0x10000>, 2870 <0x0 0x59240000 0x0 0x10000>,
2871 <0x0 0x59250000 0x0 0x10000>, 2871 <0x0 0x59250000 0x0 0x10000>,
2872 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ 2872 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
2873 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ 2873 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
2874 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ 2874 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
2875 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ 2875 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
2876 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ 2876 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
2877 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ 2877 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
2878 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ 2878 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
2879 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ 2879 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
2880 <0x0 0x59350000 0x0 0x10000>, 2880 <0x0 0x59350000 0x0 0x10000>,
2881 <0x0 0x59370000 0x0 0x10000>; 2881 <0x0 0x59370000 0x0 0x10000>;
2882 #dma-cells = <3>; 2882 #dma-cells = <3>;
2883 shared-interrupt; 2883 shared-interrupt;
2884 dma-channels = <16>; 2884 dma-channels = <16>;
2885 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ 2885 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
2886 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2887 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
2888 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
2889 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
2890 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
2891 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ 2891 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
2892 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
2893 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 2893 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
2894 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
2895 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 2895 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
2896 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
2897 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 2897 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
2898 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
2899 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
2900 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 2900 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
2901 interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ 2901 interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
2902 "edma0-chan2-rx", "edma0-chan3-tx", 2902 "edma0-chan2-rx", "edma0-chan3-tx",
2903 "edma0-chan4-tx", "edma0-chan5-tx", 2903 "edma0-chan4-tx", "edma0-chan5-tx",
2904 "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ 2904 "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
2905 "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ 2905 "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
2906 "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ 2906 "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
2907 "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ 2907 "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
2908 "edma0-chan21-tx", /* gpt5 */ 2908 "edma0-chan21-tx", /* gpt5 */
2909 "edma0-chan23-rx"; /* gpt7 */ 2909 "edma0-chan23-rx"; /* gpt7 */
2910 status = "okay"; 2910 status = "okay";
2911 }; 2911 };
2912 2912
2913 edma1: dma-controller@599F0000 { 2913 edma1: dma-controller@599F0000 {
2914 compatible = "fsl,imx8qm-edma"; 2914 compatible = "fsl,imx8qm-edma";
2915 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ 2915 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
2916 <0x0 0x59A10000 0x0 0x10000>, 2916 <0x0 0x59A10000 0x0 0x10000>,
2917 <0x0 0x59A20000 0x0 0x10000>, 2917 <0x0 0x59A20000 0x0 0x10000>,
2918 <0x0 0x59A30000 0x0 0x10000>, 2918 <0x0 0x59A30000 0x0 0x10000>,
2919 <0x0 0x59A40000 0x0 0x10000>, 2919 <0x0 0x59A40000 0x0 0x10000>,
2920 <0x0 0x59A50000 0x0 0x10000>, 2920 <0x0 0x59A50000 0x0 0x10000>,
2921 <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ 2921 <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */
2922 <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ 2922 <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */
2923 <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ 2923 <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */
2924 #dma-cells = <3>; 2924 #dma-cells = <3>;
2925 shared-interrupt; 2925 shared-interrupt;
2926 dma-channels = <9>; 2926 dma-channels = <9>;
2927 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ 2927 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
2928 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
2929 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
2930 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
2931 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
2932 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
2933 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 2933 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
2934 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
2935 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 2935 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
2936 interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ 2936 interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
2937 "edma1-chan2-rx", "edma1-chan3-tx", 2937 "edma1-chan2-rx", "edma1-chan3-tx",
2938 "edma1-chan4-tx", "edma1-chan5-tx", 2938 "edma1-chan4-tx", "edma1-chan5-tx",
2939 "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ 2939 "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
2940 "edma1-chan10-tx"; /* sai5 */ 2940 "edma1-chan10-tx"; /* sai5 */
2941 status = "okay"; 2941 status = "okay";
2942 }; 2942 };
2943 2943
2944 acm: acm@59e00000 { 2944 acm: acm@59e00000 {
2945 compatible = "nxp,imx8qm-acm"; 2945 compatible = "nxp,imx8qm-acm";
2946 reg = <0x0 0x59e00000 0x0 0x1D0000>; 2946 reg = <0x0 0x59e00000 0x0 0x1D0000>;
2947 status = "disabled"; 2947 status = "disabled";
2948 }; 2948 };
2949 2949
2950 sai0: sai@59040000 { 2950 sai0: sai@59040000 {
2951 compatible = "fsl,imx8qm-sai"; 2951 compatible = "fsl,imx8qm-sai";
2952 reg = <0x0 0x59040000 0x0 0x10000>; 2952 reg = <0x0 0x59040000 0x0 0x10000>;
2953 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 2953 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
2954 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, 2954 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
2955 <&clk IMX8QXP_CLK_DUMMY>, 2955 <&clk IMX8QXP_CLK_DUMMY>,
2956 <&clk IMX8QXP_AUD_SAI_0_MCLK>, 2956 <&clk IMX8QXP_AUD_SAI_0_MCLK>,
2957 <&clk IMX8QXP_CLK_DUMMY>, 2957 <&clk IMX8QXP_CLK_DUMMY>,
2958 <&clk IMX8QXP_CLK_DUMMY>; 2958 <&clk IMX8QXP_CLK_DUMMY>;
2959 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2959 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2960 dma-names = "rx", "tx"; 2960 dma-names = "rx", "tx";
2961 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; 2961 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
2962 status = "disabled"; 2962 status = "disabled";
2963 power-domains = <&pd_sai0>; 2963 power-domains = <&pd_sai0>;
2964 }; 2964 };
2965 2965
2966 sai1: sai@59050000 { 2966 sai1: sai@59050000 {
2967 compatible = "fsl,imx8qm-sai"; 2967 compatible = "fsl,imx8qm-sai";
2968 reg = <0x0 0x59050000 0x0 0x10000>; 2968 reg = <0x0 0x59050000 0x0 0x10000>;
2969 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 2969 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
2970 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, 2970 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
2971 <&clk IMX8QXP_CLK_DUMMY>, 2971 <&clk IMX8QXP_CLK_DUMMY>,
2972 <&clk IMX8QXP_AUD_SAI_1_MCLK>, 2972 <&clk IMX8QXP_AUD_SAI_1_MCLK>,
2973 <&clk IMX8QXP_CLK_DUMMY>, 2973 <&clk IMX8QXP_CLK_DUMMY>,
2974 <&clk IMX8QXP_CLK_DUMMY>; 2974 <&clk IMX8QXP_CLK_DUMMY>;
2975 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2975 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2976 dma-names = "rx", "tx"; 2976 dma-names = "rx", "tx";
2977 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; 2977 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
2978 status = "disabled"; 2978 status = "disabled";
2979 power-domains = <&pd_sai1>; 2979 power-domains = <&pd_sai1>;
2980 }; 2980 };
2981 2981
2982 sai2: sai@59060000 { 2982 sai2: sai@59060000 {
2983 compatible = "fsl,imx8qm-sai"; 2983 compatible = "fsl,imx8qm-sai";
2984 reg = <0x0 0x59060000 0x0 0x10000>; 2984 reg = <0x0 0x59060000 0x0 0x10000>;
2985 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 2985 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
2986 clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, 2986 clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>,
2987 <&clk IMX8QXP_CLK_DUMMY>, 2987 <&clk IMX8QXP_CLK_DUMMY>,
2988 <&clk IMX8QXP_AUD_SAI_2_MCLK>, 2988 <&clk IMX8QXP_AUD_SAI_2_MCLK>,
2989 <&clk IMX8QXP_CLK_DUMMY>, 2989 <&clk IMX8QXP_CLK_DUMMY>,
2990 <&clk IMX8QXP_CLK_DUMMY>; 2990 <&clk IMX8QXP_CLK_DUMMY>;
2991 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2991 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
2992 dma-names = "rx"; 2992 dma-names = "rx";
2993 dmas = <&edma0 16 0 1>; 2993 dmas = <&edma0 16 0 1>;
2994 status = "disabled"; 2994 status = "disabled";
2995 power-domains = <&pd_sai2>; 2995 power-domains = <&pd_sai2>;
2996 }; 2996 };
2997 2997
2998 sai3: sai@59070000 { 2998 sai3: sai@59070000 {
2999 compatible = "fsl,imx8qm-sai"; 2999 compatible = "fsl,imx8qm-sai";
3000 reg = <0x0 0x59070000 0x0 0x10000>; 3000 reg = <0x0 0x59070000 0x0 0x10000>;
3001 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 3001 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
3002 clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, 3002 clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>,
3003 <&clk IMX8QXP_CLK_DUMMY>, 3003 <&clk IMX8QXP_CLK_DUMMY>,
3004 <&clk IMX8QXP_AUD_SAI_3_MCLK>, 3004 <&clk IMX8QXP_AUD_SAI_3_MCLK>,
3005 <&clk IMX8QXP_CLK_DUMMY>, 3005 <&clk IMX8QXP_CLK_DUMMY>,
3006 <&clk IMX8QXP_CLK_DUMMY>; 3006 <&clk IMX8QXP_CLK_DUMMY>;
3007 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 3007 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3008 dma-names = "rx"; 3008 dma-names = "rx";
3009 dmas = <&edma0 17 0 1>; 3009 dmas = <&edma0 17 0 1>;
3010 status = "disabled"; 3010 status = "disabled";
3011 power-domains = <&pd_sai3>; 3011 power-domains = <&pd_sai3>;
3012 }; 3012 };
3013 3013
3014 sai4: sai@59820000 { 3014 sai4: sai@59820000 {
3015 compatible = "fsl,imx8qm-sai"; 3015 compatible = "fsl,imx8qm-sai";
3016 reg = <0x0 0x59820000 0x0 0x10000>; 3016 reg = <0x0 0x59820000 0x0 0x10000>;
3017 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 3017 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
3018 clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, 3018 clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>,
3019 <&clk IMX8QXP_CLK_DUMMY>, 3019 <&clk IMX8QXP_CLK_DUMMY>,
3020 <&clk IMX8QXP_AUD_SAI_4_MCLK>, 3020 <&clk IMX8QXP_AUD_SAI_4_MCLK>,
3021 <&clk IMX8QXP_CLK_DUMMY>, 3021 <&clk IMX8QXP_CLK_DUMMY>,
3022 <&clk IMX8QXP_CLK_DUMMY>; 3022 <&clk IMX8QXP_CLK_DUMMY>;
3023 dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; 3023 dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
3024 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 3024 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3025 dma-names = "rx", "tx"; 3025 dma-names = "rx", "tx";
3026 status = "disabled"; 3026 status = "disabled";
3027 power-domains = <&pd_sai4>; 3027 power-domains = <&pd_sai4>;
3028 }; 3028 };
3029 3029
3030 sai5: sai@59830000 { 3030 sai5: sai@59830000 {
3031 compatible = "fsl,imx8qm-sai"; 3031 compatible = "fsl,imx8qm-sai";
3032 reg = <0x0 0x59830000 0x0 0x10000>; 3032 reg = <0x0 0x59830000 0x0 0x10000>;
3033 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 3033 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
3034 clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, 3034 clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>,
3035 <&clk IMX8QXP_CLK_DUMMY>, 3035 <&clk IMX8QXP_CLK_DUMMY>,
3036 <&clk IMX8QXP_AUD_SAI_5_MCLK>, 3036 <&clk IMX8QXP_AUD_SAI_5_MCLK>,
3037 <&clk IMX8QXP_CLK_DUMMY>, 3037 <&clk IMX8QXP_CLK_DUMMY>,
3038 <&clk IMX8QXP_CLK_DUMMY>; 3038 <&clk IMX8QXP_CLK_DUMMY>;
3039 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 3039 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
3040 dma-names = "tx"; 3040 dma-names = "tx";
3041 dmas = <&edma1 10 0 0>; 3041 dmas = <&edma1 10 0 0>;
3042 status = "disabled"; 3042 status = "disabled";
3043 power-domains = <&pd_sai5>; 3043 power-domains = <&pd_sai5>;
3044 }; 3044 };
3045 3045
3046 amix: amix@59840000 { 3046 amix: amix@59840000 {
3047 compatible = "fsl,imx8qm-amix"; 3047 compatible = "fsl,imx8qm-amix";
3048 reg = <0x0 0x59840000 0x0 0x10000>; 3048 reg = <0x0 0x59840000 0x0 0x10000>;
3049 clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; 3049 clocks = <&clk IMX8QXP_AUD_AMIX_IPG>;
3050 clock-names = "ipg"; 3050 clock-names = "ipg";
3051 power-domains = <&pd_amix>; 3051 power-domains = <&pd_amix>;
3052 status = "disabled"; 3052 status = "disabled";
3053 }; 3053 };
3054 3054
3055 asrc0: asrc@59000000 { 3055 asrc0: asrc@59000000 {
3056 compatible = "fsl,imx8qm-asrc0"; 3056 compatible = "fsl,imx8qm-asrc0";
3057 reg = <0x0 0x59000000 0x0 0x10000>; 3057 reg = <0x0 0x59000000 0x0 0x10000>;
3058 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 3058 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
3059 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 3059 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
3060 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, 3060 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
3061 <&clk IMX8QXP_CLK_DUMMY>, 3061 <&clk IMX8QXP_CLK_DUMMY>,
3062 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, 3062 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
3063 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, 3063 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
3064 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, 3064 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
3065 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, 3065 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
3066 <&clk IMX8QXP_CLK_DUMMY>, 3066 <&clk IMX8QXP_CLK_DUMMY>,
3067 <&clk IMX8QXP_CLK_DUMMY>, 3067 <&clk IMX8QXP_CLK_DUMMY>,
3068 <&clk IMX8QXP_CLK_DUMMY>, 3068 <&clk IMX8QXP_CLK_DUMMY>,
3069 <&clk IMX8QXP_CLK_DUMMY>, 3069 <&clk IMX8QXP_CLK_DUMMY>,
3070 <&clk IMX8QXP_CLK_DUMMY>, 3070 <&clk IMX8QXP_CLK_DUMMY>,
3071 <&clk IMX8QXP_CLK_DUMMY>, 3071 <&clk IMX8QXP_CLK_DUMMY>,
3072 <&clk IMX8QXP_CLK_DUMMY>, 3072 <&clk IMX8QXP_CLK_DUMMY>,
3073 <&clk IMX8QXP_CLK_DUMMY>, 3073 <&clk IMX8QXP_CLK_DUMMY>,
3074 <&clk IMX8QXP_CLK_DUMMY>, 3074 <&clk IMX8QXP_CLK_DUMMY>,
3075 <&clk IMX8QXP_CLK_DUMMY>, 3075 <&clk IMX8QXP_CLK_DUMMY>,
3076 <&clk IMX8QXP_CLK_DUMMY>, 3076 <&clk IMX8QXP_CLK_DUMMY>,
3077 <&clk IMX8QXP_CLK_DUMMY>, 3077 <&clk IMX8QXP_CLK_DUMMY>,
3078 <&clk IMX8QXP_CLK_DUMMY>; 3078 <&clk IMX8QXP_CLK_DUMMY>;
3079 clock-names = "ipg", "mem", 3079 clock-names = "ipg", "mem",
3080 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 3080 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
3081 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 3081 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
3082 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 3082 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
3083 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 3083 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
3084 "spba"; 3084 "spba";
3085 dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, 3085 dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
3086 <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; 3086 <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
3087 dma-names = "rxa", "rxb", "rxc", 3087 dma-names = "rxa", "rxb", "rxc",
3088 "txa", "txb", "txc"; 3088 "txa", "txb", "txc";
3089 fsl,asrc-rate = <8000>; 3089 fsl,asrc-rate = <8000>;
3090 fsl,asrc-width = <16>; 3090 fsl,asrc-width = <16>;
3091 power-domains = <&pd_asrc0>; 3091 power-domains = <&pd_asrc0>;
3092 status = "disabled"; 3092 status = "disabled";
3093 }; 3093 };
3094 3094
3095 asrc1: asrc@59800000 { 3095 asrc1: asrc@59800000 {
3096 compatible = "fsl,imx8qm-asrc1"; 3096 compatible = "fsl,imx8qm-asrc1";
3097 reg = <0x0 0x59800000 0x0 0x10000>; 3097 reg = <0x0 0x59800000 0x0 0x10000>;
3098 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 3098 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3099 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 3099 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
3100 clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, 3100 clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>,
3101 <&clk IMX8QXP_CLK_DUMMY>, 3101 <&clk IMX8QXP_CLK_DUMMY>,
3102 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, 3102 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
3103 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, 3103 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
3104 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, 3104 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
3105 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, 3105 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
3106 <&clk IMX8QXP_CLK_DUMMY>, 3106 <&clk IMX8QXP_CLK_DUMMY>,
3107 <&clk IMX8QXP_CLK_DUMMY>, 3107 <&clk IMX8QXP_CLK_DUMMY>,
3108 <&clk IMX8QXP_CLK_DUMMY>, 3108 <&clk IMX8QXP_CLK_DUMMY>,
3109 <&clk IMX8QXP_CLK_DUMMY>, 3109 <&clk IMX8QXP_CLK_DUMMY>,
3110 <&clk IMX8QXP_CLK_DUMMY>, 3110 <&clk IMX8QXP_CLK_DUMMY>,
3111 <&clk IMX8QXP_CLK_DUMMY>, 3111 <&clk IMX8QXP_CLK_DUMMY>,
3112 <&clk IMX8QXP_CLK_DUMMY>, 3112 <&clk IMX8QXP_CLK_DUMMY>,
3113 <&clk IMX8QXP_CLK_DUMMY>, 3113 <&clk IMX8QXP_CLK_DUMMY>,
3114 <&clk IMX8QXP_CLK_DUMMY>, 3114 <&clk IMX8QXP_CLK_DUMMY>,
3115 <&clk IMX8QXP_CLK_DUMMY>, 3115 <&clk IMX8QXP_CLK_DUMMY>,
3116 <&clk IMX8QXP_CLK_DUMMY>, 3116 <&clk IMX8QXP_CLK_DUMMY>,
3117 <&clk IMX8QXP_CLK_DUMMY>, 3117 <&clk IMX8QXP_CLK_DUMMY>,
3118 <&clk IMX8QXP_CLK_DUMMY>; 3118 <&clk IMX8QXP_CLK_DUMMY>;
3119 clock-names = "ipg", "mem", 3119 clock-names = "ipg", "mem",
3120 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 3120 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
3121 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 3121 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
3122 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 3122 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
3123 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 3123 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
3124 "spba"; 3124 "spba";
3125 dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, 3125 dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
3126 <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; 3126 <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
3127 dma-names = "rxa", "rxb", "rxc", 3127 dma-names = "rxa", "rxb", "rxc",
3128 "txa", "txb", "txc"; 3128 "txa", "txb", "txc";
3129 fsl,asrc-rate = <8000>; 3129 fsl,asrc-rate = <8000>;
3130 fsl,asrc-width = <16>; 3130 fsl,asrc-width = <16>;
3131 power-domains = <&pd_asrc1>; 3131 power-domains = <&pd_asrc1>;
3132 status = "disabled"; 3132 status = "disabled";
3133 }; 3133 };
3134 3134
3135 mqs: mqs@59850000 { 3135 mqs: mqs@59850000 {
3136 compatible = "fsl,imx8qm-mqs"; 3136 compatible = "fsl,imx8qm-mqs";
3137 reg = <0x0 0x59850000 0x0 0x10000>; 3137 reg = <0x0 0x59850000 0x0 0x10000>;
3138 clocks = <&clk IMX8QXP_AUD_MQS_IPG>, 3138 clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
3139 <&clk IMX8QXP_AUD_MQS_HMCLK>; 3139 <&clk IMX8QXP_AUD_MQS_HMCLK>;
3140 clock-names = "core", "mclk"; 3140 clock-names = "core", "mclk";
3141 power-domains = <&pd_mqs0>; 3141 power-domains = <&pd_mqs0>;
3142 status = "disabled"; 3142 status = "disabled";
3143 }; 3143 };
3144 3144
3145 usdhc1: usdhc@5b010000 { 3145 usdhc1: usdhc@5b010000 {
3146 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 3146 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
3147 interrupt-parent = <&gic>; 3147 interrupt-parent = <&gic>;
3148 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 3148 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
3149 reg = <0x0 0x5b010000 0x0 0x10000>; 3149 reg = <0x0 0x5b010000 0x0 0x10000>;
3150 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, 3150 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
3151 <&clk IMX8QXP_SDHC0_CLK>, 3151 <&clk IMX8QXP_SDHC0_CLK>,
3152 <&clk IMX8QXP_SDHC0_AHB_CLK>; 3152 <&clk IMX8QXP_SDHC0_AHB_CLK>;
3153 clock-names = "ipg", "per", "ahb"; 3153 clock-names = "ipg", "per", "ahb";
3154 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; 3154 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
3155 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 3155 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
3156 assigned-clock-rates = <0>, <400000000>; 3156 assigned-clock-rates = <0>, <400000000>;
3157 power-domains = <&pd_conn_sdch0>; 3157 power-domains = <&pd_conn_sdch0>;
3158 fsl,tuning-start-tap = <20>; 3158 fsl,tuning-start-tap = <20>;
3159 fsl,tuning-step= <2>; 3159 fsl,tuning-step= <2>;
3160 status = "disabled"; 3160 status = "disabled";
3161 }; 3161 };
3162 3162
3163 usdhc2: usdhc@5b020000 { 3163 usdhc2: usdhc@5b020000 {
3164 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 3164 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
3165 interrupt-parent = <&gic>; 3165 interrupt-parent = <&gic>;
3166 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 3166 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
3167 reg = <0x0 0x5b020000 0x0 0x10000>; 3167 reg = <0x0 0x5b020000 0x0 0x10000>;
3168 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, 3168 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
3169 <&clk IMX8QXP_SDHC1_CLK>, 3169 <&clk IMX8QXP_SDHC1_CLK>,
3170 <&clk IMX8QXP_SDHC1_AHB_CLK>; 3170 <&clk IMX8QXP_SDHC1_AHB_CLK>;
3171 clock-names = "ipg", "per", "ahb"; 3171 clock-names = "ipg", "per", "ahb";
3172 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; 3172 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
3173 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 3173 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
3174 assigned-clock-rates = <0>, <200000000>; 3174 assigned-clock-rates = <0>, <200000000>;
3175 power-domains = <&pd_conn_sdch1>; 3175 power-domains = <&pd_conn_sdch1>;
3176 fsl,tuning-start-tap = <20>; 3176 fsl,tuning-start-tap = <20>;
3177 fsl,tuning-step= <2>; 3177 fsl,tuning-step= <2>;
3178 status = "disabled"; 3178 status = "disabled";
3179 }; 3179 };
3180 3180
3181 usdhc3: usdhc@5b030000 { 3181 usdhc3: usdhc@5b030000 {
3182 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 3182 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
3183 interrupt-parent = <&gic>; 3183 interrupt-parent = <&gic>;
3184 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 3184 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
3185 reg = <0x0 0x5b030000 0x0 0x10000>; 3185 reg = <0x0 0x5b030000 0x0 0x10000>;
3186 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, 3186 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
3187 <&clk IMX8QXP_SDHC2_CLK>, 3187 <&clk IMX8QXP_SDHC2_CLK>,
3188 <&clk IMX8QXP_SDHC2_AHB_CLK>; 3188 <&clk IMX8QXP_SDHC2_AHB_CLK>;
3189 clock-names = "ipg", "per", "ahb"; 3189 clock-names = "ipg", "per", "ahb";
3190 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; 3190 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
3191 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 3191 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
3192 assigned-clock-rates = <0>, <200000000>; 3192 assigned-clock-rates = <0>, <200000000>;
3193 power-domains = <&pd_conn_sdch2>; 3193 power-domains = <&pd_conn_sdch2>;
3194 status = "disabled"; 3194 status = "disabled";
3195 }; 3195 };
3196 3196
3197 fec1: ethernet@5b040000 { 3197 fec1: ethernet@5b040000 {
3198 compatible = "fsl,imx8qm-fec"; 3198 compatible = "fsl,imx8qm-fec";
3199 reg = <0x0 0x5b040000 0x0 0x10000>; 3199 reg = <0x0 0x5b040000 0x0 0x10000>;
3200 interrupt-parent = <&wu>; 3200 interrupt-parent = <&wu>;
3201 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 3201 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3202 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3203 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3204 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 3204 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
3205 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, 3205 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
3206 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; 3206 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
3207 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 3207 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
3208 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, 3208 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
3209 <&clk IMX8QXP_ENET0_REF_DIV>; 3209 <&clk IMX8QXP_ENET0_REF_DIV>;
3210 assigned-clock-rates = <250000000>, <125000000>; 3210 assigned-clock-rates = <250000000>, <125000000>;
3211 fsl,num-tx-queues=<3>; 3211 fsl,num-tx-queues=<3>;
3212 fsl,num-rx-queues=<3>; 3212 fsl,num-rx-queues=<3>;
3213 fsl,wakeup_irq = <0>; 3213 fsl,wakeup_irq = <0>;
3214 power-domains = <&pd_conn_enet0>; 3214 power-domains = <&pd_conn_enet0>;
3215 status = "disabled"; 3215 status = "disabled";
3216 }; 3216 };
3217 3217
3218 fec2: ethernet@5b050000 { 3218 fec2: ethernet@5b050000 {
3219 compatible = "fsl,imx8qm-fec"; 3219 compatible = "fsl,imx8qm-fec";
3220 reg = <0x0 0x5b050000 0x0 0x10000>; 3220 reg = <0x0 0x5b050000 0x0 0x10000>;
3221 interrupt-parent = <&wu>; 3221 interrupt-parent = <&wu>;
3222 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3222 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3223 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3224 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3225 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 3225 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
3226 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, 3226 clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>,
3227 <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; 3227 <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>;
3228 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 3228 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
3229 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, 3229 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>,
3230 <&clk IMX8QXP_ENET1_REF_DIV>; 3230 <&clk IMX8QXP_ENET1_REF_DIV>;
3231 assigned-clock-rates = <250000000>, <125000000>; 3231 assigned-clock-rates = <250000000>, <125000000>;
3232 fsl,num-tx-queues=<3>; 3232 fsl,num-tx-queues=<3>;
3233 fsl,num-rx-queues=<3>; 3233 fsl,num-rx-queues=<3>;
3234 fsl,wakeup_irq = <0>; 3234 fsl,wakeup_irq = <0>;
3235 power-domains = <&pd_conn_enet1>; 3235 power-domains = <&pd_conn_enet1>;
3236 status = "disabled"; 3236 status = "disabled";
3237 }; 3237 };
3238 3238
3239 mlb: mlb@5B060000 { 3239 mlb: mlb@5B060000 {
3240 compatible = "fsl,imx6q-mlb150"; 3240 compatible = "fsl,imx6q-mlb150";
3241 reg = <0x0 0x5B060000 0x0 0x10000>; 3241 reg = <0x0 0x5B060000 0x0 0x10000>;
3242 interrupt-parent = <&gic>; 3242 interrupt-parent = <&gic>;
3243 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, 3243 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
3244 <0 266 IRQ_TYPE_LEVEL_HIGH>; 3244 <0 266 IRQ_TYPE_LEVEL_HIGH>;
3245 clocks = <&clk IMX8QXP_MLB_CLK>, 3245 clocks = <&clk IMX8QXP_MLB_CLK>,
3246 <&clk IMX8QXP_MLB_HCLK>, 3246 <&clk IMX8QXP_MLB_HCLK>,
3247 <&clk IMX8QXP_MLB_IPG_CLK>; 3247 <&clk IMX8QXP_MLB_IPG_CLK>;
3248 clock-names = "mlb", "hclk", "ipg"; 3248 clock-names = "mlb", "hclk", "ipg";
3249 assigned-clocks = <&clk IMX8QXP_MLB_CLK>, 3249 assigned-clocks = <&clk IMX8QXP_MLB_CLK>,
3250 <&clk IMX8QXP_MLB_HCLK>, 3250 <&clk IMX8QXP_MLB_HCLK>,
3251 <&clk IMX8QXP_MLB_IPG_CLK>; 3251 <&clk IMX8QXP_MLB_IPG_CLK>;
3252 assigned-clock-rates = <333333333>, <333333333>, <83333333>; 3252 assigned-clock-rates = <333333333>, <333333333>, <83333333>;
3253 power-domains = <&pd_conn_mlb0>; 3253 power-domains = <&pd_conn_mlb0>;
3254 status = "disabled"; 3254 status = "disabled";
3255 }; 3255 };
3256 3256
3257 gpt0: gpt0@5d140000 { 3257 gpt0: gpt0@5d140000 {
3258 compatible = "fsl,imx8qxp-gpt"; 3258 compatible = "fsl,imx8qxp-gpt";
3259 reg = <0x0 0x5d140000 0x0 0x4000>; 3259 reg = <0x0 0x5d140000 0x0 0x4000>;
3260 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 3260 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
3261 clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>; 3261 clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>;
3262 clock-names = "ipg", "per"; 3262 clock-names = "ipg", "per";
3263 power-domains = <&pd_lsio_gpt0>; 3263 power-domains = <&pd_lsio_gpt0>;
3264 }; 3264 };
3265 3265
3266 dsp: dsp@596e8000 { 3266 dsp: dsp@596e8000 {
3267 compatible = "fsl,imx8qxp-dsp"; 3267 compatible = "fsl,imx8qxp-dsp";
3268 reserved-region = <&dsp_reserved>; 3268 reserved-region = <&dsp_reserved>;
3269 reg = <0x0 0x596e8000 0x0 0x88000>; 3269 reg = <0x0 0x596e8000 0x0 0x88000>;
3270 clocks = <&clk IMX8QXP_AUD_DSP_IPG>, 3270 clocks = <&clk IMX8QXP_AUD_DSP_IPG>,
3271 <&clk IMX8QXP_AUD_OCRAM_IPG>, 3271 <&clk IMX8QXP_AUD_OCRAM_IPG>,
3272 <&clk IMX8QXP_AUD_DSP_CORE_CLK>; 3272 <&clk IMX8QXP_AUD_DSP_CORE_CLK>;
3273 clock-names = "ipg", "ocram", "core"; 3273 clock-names = "ipg", "ocram", "core";
3274 fsl,dsp-firmware = "imx/dsp/hifi4.bin"; 3274 fsl,dsp-firmware = "imx/dsp/hifi4.bin";
3275 power-domains = <&pd_dsp>; 3275 power-domains = <&pd_dsp>;
3276 }; 3276 };
3277 3277
3278 esai0: esai@59010000 { 3278 esai0: esai@59010000 {
3279 compatible = "fsl,imx8qm-esai"; 3279 compatible = "fsl,imx8qm-esai";
3280 reg = <0x0 0x59010000 0x0 0x10000>; 3280 reg = <0x0 0x59010000 0x0 0x10000>;
3281 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 3281 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
3282 clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, 3282 clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
3283 <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, 3283 <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
3284 <&clk IMX8QXP_AUD_ESAI_0_IPG>, 3284 <&clk IMX8QXP_AUD_ESAI_0_IPG>,
3285 <&clk IMX8QXP_CLK_DUMMY>; 3285 <&clk IMX8QXP_CLK_DUMMY>;
3286 clock-names = "core", "extal", "fsys", "spba"; 3286 clock-names = "core", "extal", "fsys", "spba";
3287 dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; 3287 dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
3288 dma-names = "rx", "tx"; 3288 dma-names = "rx", "tx";
3289 power-domains = <&pd_esai0>; 3289 power-domains = <&pd_esai0>;
3290 status = "disabled"; 3290 status = "disabled";
3291 }; 3291 };
3292 3292
3293 spdif0: spdif@59020000 { 3293 spdif0: spdif@59020000 {
3294 compatible = "fsl,imx8qm-spdif"; 3294 compatible = "fsl,imx8qm-spdif";
3295 reg = <0x0 0x59020000 0x0 0x10000>; 3295 reg = <0x0 0x59020000 0x0 0x10000>;
3296 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 3296 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
3297 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 3297 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
3298 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ 3298 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
3299 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ 3299 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
3300 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ 3300 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
3301 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ 3301 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
3302 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ 3302 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
3303 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ 3303 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
3304 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ 3304 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
3305 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ 3305 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
3306 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ 3306 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
3307 <&clk IMX8QXP_CLK_DUMMY>; /* spba */ 3307 <&clk IMX8QXP_CLK_DUMMY>; /* spba */
3308 clock-names = "core", "rxtx0", 3308 clock-names = "core", "rxtx0",
3309 "rxtx1", "rxtx2", 3309 "rxtx1", "rxtx2",
3310 "rxtx3", "rxtx4", 3310 "rxtx3", "rxtx4",
3311 "rxtx5", "rxtx6", 3311 "rxtx5", "rxtx6",
3312 "rxtx7", "spba"; 3312 "rxtx7", "spba";
3313 dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; 3313 dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
3314 dma-names = "rx", "tx"; 3314 dma-names = "rx", "tx";
3315 power-domains = <&pd_spdif0>; 3315 power-domains = <&pd_spdif0>;
3316 status = "disabled"; 3316 status = "disabled";
3317 }; 3317 };
3318 3318
3319 flexspi0: flexspi@05d120000 { 3319 flexspi0: flexspi@05d120000 {
3320 #address-cells = <1>; 3320 #address-cells = <1>;
3321 #size-cells = <0>; 3321 #size-cells = <0>;
3322 compatible = "fsl,imx8qxp-flexspi"; 3322 compatible = "fsl,imx8qxp-flexspi";
3323 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; 3323 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>;
3324 reg-names = "FlexSPI", "FlexSPI-memory"; 3324 reg-names = "FlexSPI", "FlexSPI-memory";
3325 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 3325 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3326 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>; 3326 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>;
3327 assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>; 3327 assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>;
3328 assigned-clock-rates = <29000000>; 3328 assigned-clock-rates = <29000000>;
3329 clock-names = "fspi"; 3329 clock-names = "fspi";
3330 power-domains = <&pd_lsio_flexspi0>; 3330 power-domains = <&pd_lsio_flexspi0>;
3331 status = "disabled"; 3331 status = "disabled";
3332 }; 3332 };
3333 3333
3334 display-subsystem { 3334 display-subsystem {
3335 compatible = "fsl,imx-display-subsystem"; 3335 compatible = "fsl,imx-display-subsystem";
3336 ports = <&dpu_disp0>, <&dpu_disp1>; 3336 ports = <&dpu_disp0>, <&dpu_disp1>;
3337 }; 3337 };
3338 3338
3339 dma_cap: dma_cap { 3339 dma_cap: dma_cap {
3340 compatible = "dma-capability"; 3340 compatible = "dma-capability";
3341 only-dma-mask32 = <1>; 3341 only-dma-mask32 = <1>;
3342 }; 3342 };
3343 3343
3344 hsio: hsio@5f080000 { 3344 hsio: hsio@5f080000 {
3345 compatible = "fsl,imx8qm-hsio", "syscon"; 3345 compatible = "fsl,imx8qm-hsio", "syscon";
3346 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ 3346 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
3347 }; 3347 };
3348 3348
3349 ocotp: ocotp { 3349 ocotp: ocotp {
3350 #address-cells = <1>; 3350 #address-cells = <1>;
3351 #size-cells = <1>; 3351 #size-cells = <1>;
3352 compatible = "fsl,imx8qxp-ocotp", "syscon"; 3352 compatible = "fsl,imx8qxp-ocotp", "syscon";
3353 }; 3353 };
3354 3354
3355 pcieb: pcie@0x5f010000 { 3355 pcieb: pcie@0x5f010000 {
3356 /* 3356 /*
3357 * pcieb phyx1 lane1 in default, adjust it refer to the 3357 * pcieb phyx1 lane1 in default, adjust it refer to the
3358 * exact hw design. 3358 * exact hw design.
3359 */ 3359 */
3360 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; 3360 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
3361 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ 3361 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
3362 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ 3362 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
3363 reg-names = "dbi", "config"; 3363 reg-names = "dbi", "config";
3364 reserved-region = <&rpmsg_reserved>; 3364 reserved-region = <&rpmsg_reserved>;
3365 #address-cells = <3>; 3365 #address-cells = <3>;
3366 #size-cells = <2>; 3366 #size-cells = <2>;
3367 device_type = "pci"; 3367 device_type = "pci";
3368 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 3368 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
3369 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ 3369 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
3370 num-lanes = <1>; 3370 num-lanes = <1>;
3371 3371
3372 #interrupt-cells = <1>; 3372 #interrupt-cells = <1>;
3373 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3373 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3374 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 3374 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
3375 interrupt-names = "msi"; 3375 interrupt-names = "msi";
3376 3376
3377 /* 3377 /*
3378 * Set these clocks in default, then clocks should be 3378 * Set these clocks in default, then clocks should be
3379 * refined for exact hw design of imx8 pcie. 3379 * refined for exact hw design of imx8 pcie.
3380 */ 3380 */
3381 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, 3381 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
3382 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, 3382 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
3383 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, 3383 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
3384 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, 3384 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>,
3385 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; 3385 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>,
3386 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; 3386 <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>,
3387 3387 <&clk IMX8QXP_HSIO_MISC_PER_CLK>;
3388 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
3389 "phy_per", "misc_per";
3388 interrupt-map-mask = <0 0 0 0x7>; 3390 interrupt-map-mask = <0 0 0 0x7>;
3389 interrupt-map = <0 0 0 1 &gic 0 105 4>, 3391 interrupt-map = <0 0 0 1 &gic 0 105 4>,
3390 <0 0 0 2 &gic 0 106 4>, 3392 <0 0 0 2 &gic 0 106 4>,
3391 <0 0 0 3 &gic 0 107 4>, 3393 <0 0 0 3 &gic 0 107 4>,
3392 <0 0 0 4 &gic 0 108 4>; 3394 <0 0 0 4 &gic 0 108 4>;
3393 power-domains = <&pd_pcie>; 3395 power-domains = <&pd_pcie>;
3394 fsl,max-link-speed = <3>; 3396 fsl,max-link-speed = <3>;
3395 hsio-cfg = <PCIEAX2PCIEBX1>; 3397 hsio-cfg = <PCIEAX2PCIEBX1>;
3396 hsio = <&hsio>; 3398 hsio = <&hsio>;
3397 ctrl-id = <1>; /* pcieb */ 3399 ctrl-id = <1>; /* pcieb */
3398 cpu-base-addr = <0x80000000>; 3400 cpu-base-addr = <0x80000000>;
3399 status = "disabled"; 3401 status = "disabled";
3400 }; 3402 };
3401 3403
3402 imx_ion { 3404 imx_ion {
3403 compatible = "fsl,mxc-ion"; 3405 compatible = "fsl,mxc-ion";
3404 fsl,heap-id = <0>; 3406 fsl,heap-id = <0>;
3405 }; 3407 };
3406 3408
3407 vpu: vpu@2c000000 { 3409 vpu: vpu@2c000000 {
3408 compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu"; 3410 compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu";
3409 reg = <0x0 0x2c000000 0x0 0x1000000>; 3411 reg = <0x0 0x2c000000 0x0 0x1000000>;
3410 reg-names = "vpu_regs"; 3412 reg-names = "vpu_regs";
3411 interrupts = <0 464 0x4>, /* encoder irq */ 3413 interrupts = <0 464 0x4>, /* encoder irq */
3412 <0 465 0x4>, /* encoder fiq */ 3414 <0 465 0x4>, /* encoder fiq */
3413 <0 466 0x4>, /* decoder irq */ 3415 <0 466 0x4>, /* decoder irq */
3414 <0 467 0x4>, /* decoder fiq */ 3416 <0 467 0x4>, /* decoder fiq */
3415 <0 468 0x4>; /* decoder sif */ 3417 <0 468 0x4>; /* decoder sif */
3416 interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif"; 3418 interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif";
3417 clocks = <&clk IMX8QXP_VPU_DEC_CLK>; 3419 clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
3418 clock-names = "vpu_clk"; 3420 clock-names = "vpu_clk";
3419 assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; 3421 assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>;
3420 power-domains = <&pd_vpu_dec>; 3422 power-domains = <&pd_vpu_dec>;
3421 status = "disabled"; 3423 status = "disabled";
3422 }; 3424 };
3423 3425
3424 vpu_decoder: vpu_decoder@2c000000 { 3426 vpu_decoder: vpu_decoder@2c000000 {
3425 compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; 3427 compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
3426 boot-region = <&decoder_boot>; 3428 boot-region = <&decoder_boot>;
3427 rpc-region = <&decoder_rpc>; 3429 rpc-region = <&decoder_rpc>;
3428 reg = <0x0 0x2c000000 0x0 0x1000000>; 3430 reg = <0x0 0x2c000000 0x0 0x1000000>;
3429 reg-names = "vpu_regs"; 3431 reg-names = "vpu_regs";
3430 power-domains = <&pd_vpu_dec>; 3432 power-domains = <&pd_vpu_dec>;
3431 reg-csr = <0x2d040000>; 3433 reg-csr = <0x2d040000>;
3432 status = "disabled"; 3434 status = "disabled";
3433 }; 3435 };
3434 3436
3435 vpu_encoder: vpu_encoder@2d000000 { 3437 vpu_encoder: vpu_encoder@2d000000 {
3436 compatible = "nxp,imx8qxp-b0-vpuenc"; 3438 compatible = "nxp,imx8qxp-b0-vpuenc";
3437 #address-cells = <1>; 3439 #address-cells = <1>;
3438 #size-cells = <1>; 3440 #size-cells = <1>;
3439 3441
3440 boot-region = <&encoder_boot>; 3442 boot-region = <&encoder_boot>;
3441 rpc-region = <&encoder_rpc>; 3443 rpc-region = <&encoder_rpc>;
3442 reserved-region = <&encoder_reserved>; 3444 reserved-region = <&encoder_reserved>;
3443 reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ 3445 reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/
3444 <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ 3446 <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
3445 reg-names = "vpu_regs"; 3447 reg-names = "vpu_regs";
3446 power-domains = <&pd_vpu_enc>; 3448 power-domains = <&pd_vpu_enc>;
3447 reg-rpc-system = <0x40000000>; 3449 reg-rpc-system = <0x40000000>;
3448 3450
3449 resolution-max = <1920 1080>; 3451 resolution-max = <1920 1080>;
3450 fps-max = <120>; 3452 fps-max = <120>;
3451 status = "disabled"; 3453 status = "disabled";
3452 3454
3453 core0@1020000 { 3455 core0@1020000 {
3454 compatible = "fsl,imx8-mu1-vpu-m0"; 3456 compatible = "fsl,imx8-mu1-vpu-m0";
3455 reg = <0x1020000 0x20000>; 3457 reg = <0x1020000 0x20000>;
3456 reg-csr = <0x1050000 0x10000>; 3458 reg-csr = <0x1050000 0x10000>;
3457 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 3459 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
3458 fsl,vpu_ap_mu_id = <17>; 3460 fsl,vpu_ap_mu_id = <17>;
3459 fw-buf-size = <0x200000>; 3461 fw-buf-size = <0x200000>;
3460 rpc-buf-size = <0x80000>; 3462 rpc-buf-size = <0x80000>;
3461 print-buf-size = <0x80000>; 3463 print-buf-size = <0x80000>;
3462 }; 3464 };
3463 }; 3465 };
3464 imx_rpmsg: imx_rpmsg { 3466 imx_rpmsg: imx_rpmsg {
3465 compatible = "fsl,rpmsg-bus", "simple-bus"; 3467 compatible = "fsl,rpmsg-bus", "simple-bus";
3466 #address-cells = <2>; 3468 #address-cells = <2>;
3467 #size-cells = <2>; 3469 #size-cells = <2>;
3468 ranges; 3470 ranges;
3469 3471
3470 mu_rpmsg: mu_rpmsg@5d200000 { 3472 mu_rpmsg: mu_rpmsg@5d200000 {
3471 compatible = "fsl,imx6sx-mu"; 3473 compatible = "fsl,imx6sx-mu";
3472 reg = <0x0 0x5d200000 0x0 0x10000>; 3474 reg = <0x0 0x5d200000 0x0 0x10000>;
3473 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 3475 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
3474 clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; 3476 clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>;
3475 clock-names = "ipg"; 3477 clock-names = "ipg";
3476 power-domains = <&pd_lsio_mu5a>; 3478 power-domains = <&pd_lsio_mu5a>;
3477 }; 3479 };
3478 3480
3479 rpmsg: rpmsg{ 3481 rpmsg: rpmsg{
3480 compatible = "fsl,imx8qxp-rpmsg"; 3482 compatible = "fsl,imx8qxp-rpmsg";
3481 status = "disabled"; 3483 status = "disabled";
3482 mub-partition = <3>; 3484 mub-partition = <3>;
3483 power-domains = <&pd_lsio_mu5a>; 3485 power-domains = <&pd_lsio_mu5a>;
3484 memory-region = <&rpmsg_dma_reserved>; 3486 memory-region = <&rpmsg_dma_reserved>;
3485 }; 3487 };
3486 }; 3488 };
3487 3489
3488 crypto: caam@0x31400000 { 3490 crypto: caam@0x31400000 {
3489 compatible = "fsl,sec-v4.0"; 3491 compatible = "fsl,sec-v4.0";
3490 reg = <0 0x31400000 0 0x400000>; 3492 reg = <0 0x31400000 0 0x400000>;
3491 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3493 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
3492 #address-cells = <1>; 3494 #address-cells = <1>;
3493 #size-cells = <1>; 3495 #size-cells = <1>;
3494 ranges = <0 0 0x31400000 0x400000>; 3496 ranges = <0 0 0x31400000 0x400000>;
3495 fsl,first-jr-index = <2>; 3497 fsl,first-jr-index = <2>;
3496 fsl,sec-era = <9>; 3498 fsl,sec-era = <9>;
3497 3499
3498 sec_jr1: jr1@0x20000 { 3500 sec_jr1: jr1@0x20000 {
3499 compatible = "fsl,sec-v4.0-job-ring"; 3501 compatible = "fsl,sec-v4.0-job-ring";
3500 reg = <0x20000 0x1000>; 3502 reg = <0x20000 0x1000>;
3501 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 3503 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
3502 power-domains = <&pd_caam_jr1>; 3504 power-domains = <&pd_caam_jr1>;
3503 status = "disabled"; 3505 status = "disabled";
3504 }; 3506 };
3505 3507
3506 sec_jr2: jr2@30000 { 3508 sec_jr2: jr2@30000 {
3507 compatible = "fsl,sec-v4.0-job-ring"; 3509 compatible = "fsl,sec-v4.0-job-ring";
3508 reg = <0x30000 0x1000>; 3510 reg = <0x30000 0x1000>;
3509 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 3511 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
3510 power-domains = <&pd_caam_jr2>; 3512 power-domains = <&pd_caam_jr2>;
3511 status = "okay"; 3513 status = "okay";
3512 }; 3514 };
3513 3515
3514 sec_jr3: jr3@40000 { 3516 sec_jr3: jr3@40000 {
3515 compatible = "fsl,sec-v4.0-job-ring"; 3517 compatible = "fsl,sec-v4.0-job-ring";
3516 reg = <0x40000 0x1000>; 3518 reg = <0x40000 0x1000>;
3517 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 3519 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
3518 power-domains = <&pd_caam_jr3>; 3520 power-domains = <&pd_caam_jr3>;
3519 status = "okay"; 3521 status = "okay";
3520 }; 3522 };
3521 }; 3523 };
3522 3524
3523 caam_sm: caam-sm@31800000 { 3525 caam_sm: caam-sm@31800000 {
3524 compatible = "fsl,imx6q-caam-sm"; 3526 compatible = "fsl,imx6q-caam-sm";
3525 reg = <0 0x31800000 0 0x10000>; 3527 reg = <0 0x31800000 0 0x10000>;
3526 }; 3528 };
3527 3529
3528 sc_pwrkey: sc-powerkey { 3530 sc_pwrkey: sc-powerkey {
3529 compatible = "fsl,imx8-pwrkey"; 3531 compatible = "fsl,imx8-pwrkey";
3530 linux,keycode = <KEY_POWER>; 3532 linux,keycode = <KEY_POWER>;
3531 wakeup-source; 3533 wakeup-source;
3532 }; 3534 };
3533 3535
3534 wdog: wdog { 3536 wdog: wdog {
3535 compatible = "fsl,imx8-wdt"; 3537 compatible = "fsl,imx8-wdt";
3536 }; 3538 };
3537 }; 3539 };
3538 3540
3539 &A35_0 { 3541 &A35_0 {
3540 operating-points = < 3542 operating-points = <
3541 /* kHz uV*/ 3543 /* kHz uV*/
3542 /* voltage is maintained by SCFW, so no need here */ 3544 /* voltage is maintained by SCFW, so no need here */
3543 1200000 0 3545 1200000 0
3544 900000 0 3546 900000 0
3545 >; 3547 >;
3546 clocks = <&clk IMX8QXP_A35_DIV>; 3548 clocks = <&clk IMX8QXP_A35_DIV>;
3547 clock-latency = <61036>; 3549 clock-latency = <61036>;
3548 #cooling-cells = <2>; 3550 #cooling-cells = <2>;
3549 }; 3551 };
3550 3552
3551 /delete-node/ &A35_2; 3553 /delete-node/ &A35_2;
3552 /delete-node/ &A35_3; 3554 /delete-node/ &A35_3;
3553 3555
arch/arm/dts/fsl-imx8dxl.dtsi
Diff comments   View file @ 11ea97f
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2020 NXP 3 * Copyright 2020 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include "fsl-imx8-ca35.dtsi" 7 #include "fsl-imx8-ca35.dtsi"
8 #include <dt-bindings/soc/imx_rsrc.h> 8 #include <dt-bindings/soc/imx_rsrc.h>
9 #include <dt-bindings/soc/imx8_hsio.h> 9 #include <dt-bindings/soc/imx8_hsio.h>
10 #include <dt-bindings/soc/imx8_pd.h> 10 #include <dt-bindings/soc/imx8_pd.h>
11 #include <dt-bindings/clock/imx8qxp-clock.h> 11 #include <dt-bindings/clock/imx8qxp-clock.h>
12 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/pads-imx8dxl.h> 13 #include <dt-bindings/pinctrl/pads-imx8dxl.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/thermal/thermal.h> 15 #include <dt-bindings/thermal/thermal.h>
16 16
17 / { 17 / {
18 model = "NXP i.MX8DXL"; 18 model = "NXP i.MX8DXL";
19 compatible = "fsl,imx8dxl"; 19 compatible = "fsl,imx8dxl";
20 interrupt-parent = <&gic>; 20 interrupt-parent = <&gic>;
21 #address-cells = <2>; 21 #address-cells = <2>;
22 #size-cells = <2>; 22 #size-cells = <2>;
23 23
24 aliases { 24 aliases {
25 ethernet0 = &fec1; 25 ethernet0 = &fec1;
26 ethernet1 = &eqos; 26 ethernet1 = &eqos;
27 serial0 = &lpuart0; 27 serial0 = &lpuart0;
28 serial1 = &lpuart1; 28 serial1 = &lpuart1;
29 serial2 = &lpuart2; 29 serial2 = &lpuart2;
30 serial3 = &lpuart3; 30 serial3 = &lpuart3;
31 gpio0 = &gpio0; 31 gpio0 = &gpio0;
32 gpio1 = &gpio1; 32 gpio1 = &gpio1;
33 gpio2 = &gpio2; 33 gpio2 = &gpio2;
34 gpio3 = &gpio3; 34 gpio3 = &gpio3;
35 gpio4 = &gpio4; 35 gpio4 = &gpio4;
36 gpio5 = &gpio5; 36 gpio5 = &gpio5;
37 gpio6 = &gpio6; 37 gpio6 = &gpio6;
38 gpio7 = &gpio7; 38 gpio7 = &gpio7;
39 mmc0 = &usdhc1; 39 mmc0 = &usdhc1;
40 mmc1 = &usdhc2; 40 mmc1 = &usdhc2;
41 mmc2 = &usdhc3; 41 mmc2 = &usdhc3;
42 can0 = &flexcan1; 42 can0 = &flexcan1;
43 can1 = &flexcan2; 43 can1 = &flexcan2;
44 can2 = &flexcan3; 44 can2 = &flexcan3;
45 i2c0 = &i2c0; 45 i2c0 = &i2c0;
46 i2c1 = &i2c1; 46 i2c1 = &i2c1;
47 i2c2 = &i2c2; 47 i2c2 = &i2c2;
48 i2c3 = &i2c3; 48 i2c3 = &i2c3;
49 spi0 = &flexspi0; 49 spi0 = &flexspi0;
50 usb0 = &usbotg1; 50 usb0 = &usbotg1;
51 usbphy0 = &usbphy1; 51 usbphy0 = &usbphy1;
52 usb1 = &usbotg2; 52 usb1 = &usbotg2;
53 usbphy1 = &usbphy2; 53 usbphy1 = &usbphy2;
54 pci0 = &pcieb; 54 pci0 = &pcieb;
55 }; 55 };
56 56
57 cpus { 57 cpus {
58 idle-states { 58 idle-states {
59 entry-method = "psci"; 59 entry-method = "psci";
60 60
61 CPU_SLEEP: cpu-sleep { 61 CPU_SLEEP: cpu-sleep {
62 compatible = "arm,idle-state"; 62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x10000>; 63 arm,psci-suspend-param = <0x10000>;
64 local-timer-stop; 64 local-timer-stop;
65 entry-latency-us = <500>; 65 entry-latency-us = <500>;
66 exit-latency-us = <500>; 66 exit-latency-us = <500>;
67 min-residency-us = <5000>; 67 min-residency-us = <5000>;
68 }; 68 };
69 69
70 CLUSTER_SLEEP: cluster-sleep { 70 CLUSTER_SLEEP: cluster-sleep {
71 compatible = "arm,idle-state"; 71 compatible = "arm,idle-state";
72 arm,psci-suspend-param = <0x10033>; 72 arm,psci-suspend-param = <0x10033>;
73 local-timer-stop; 73 local-timer-stop;
74 entry-latency-us = <500>; 74 entry-latency-us = <500>;
75 exit-latency-us = <2300>; 75 exit-latency-us = <2300>;
76 min-residency-us = <14000>; 76 min-residency-us = <14000>;
77 }; 77 };
78 }; 78 };
79 }; 79 };
80 80
81 memory@80000000 { 81 memory@80000000 {
82 device_type = "memory"; 82 device_type = "memory";
83 reg = <0x00000000 0x80000000 0 0x40000000>; 83 reg = <0x00000000 0x80000000 0 0x40000000>;
84 /* DRAM space - 1, size : 1 GB DRAM */ 84 /* DRAM space - 1, size : 1 GB DRAM */
85 }; 85 };
86 86
87 reserved-memory { 87 reserved-memory {
88 #address-cells = <2>; 88 #address-cells = <2>;
89 #size-cells = <2>; 89 #size-cells = <2>;
90 ranges; 90 ranges;
91 91
92 /* 92 /*
93 * reserved-memory layout 93 * reserved-memory layout
94 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 94 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
95 * Shouldn't be used at A core and Linux side. 95 * Shouldn't be used at A core and Linux side.
96 * 96 *
97 */ 97 */
98 rpmsg_reserved: rpmsg@0x90000000 { 98 rpmsg_reserved: rpmsg@0x90000000 {
99 no-map; 99 no-map;
100 reg = <0 0x90000000 0 0x400000>; 100 reg = <0 0x90000000 0 0x400000>;
101 }; 101 };
102 rpmsg_dma_reserved:rpmsg_dma@0x90400000 { 102 rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
103 compatible = "shared-dma-pool"; 103 compatible = "shared-dma-pool";
104 no-map; 104 no-map;
105 reg = <0 0x90400000 0 0x1C00000>; 105 reg = <0 0x90400000 0 0x1C00000>;
106 }; 106 };
107 /* global autoconfigured region for contiguous allocations */ 107 /* global autoconfigured region for contiguous allocations */
108 linux,cma { 108 linux,cma {
109 compatible = "shared-dma-pool"; 109 compatible = "shared-dma-pool";
110 reusable; 110 reusable;
111 size = <0 0x3c000000>; 111 size = <0 0x3c000000>;
112 alloc-ranges = <0 0x96000000 0 0x3c000000>; 112 alloc-ranges = <0 0x96000000 0 0x3c000000>;
113 linux,cma-default; 113 linux,cma-default;
114 }; 114 };
115 }; 115 };
116 116
117 gic: interrupt-controller@51a00000 { 117 gic: interrupt-controller@51a00000 {
118 compatible = "arm,gic-v3"; 118 compatible = "arm,gic-v3";
119 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 119 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
120 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ 120 <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
121 #interrupt-cells = <3>; 121 #interrupt-cells = <3>;
122 interrupt-controller; 122 interrupt-controller;
123 interrupts = <GIC_PPI 9 123 interrupts = <GIC_PPI 9
124 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 124 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
125 interrupt-parent = <&gic>; 125 interrupt-parent = <&gic>;
126 }; 126 };
127 127
128 mu8: mu@5d230000 { 128 mu8: mu@5d230000 {
129 compatible = "fsl,imx-m4-mu"; 129 compatible = "fsl,imx-m4-mu";
130 reg = <0x0 0x5d230000 0x0 0x10000>; 130 reg = <0x0 0x5d230000 0x0 0x10000>;
131 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 131 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
132 power-domains = <&pd_lsio_mu8a>; 132 power-domains = <&pd_lsio_mu8a>;
133 status = "okay"; 133 status = "okay";
134 }; 134 };
135 135
136 mu: mu@5d1c0000 { 136 mu: mu@5d1c0000 {
137 compatible = "fsl,imx8-mu"; 137 compatible = "fsl,imx8-mu";
138 reg = <0x0 0x5d1c0000 0x0 0x10000>; 138 reg = <0x0 0x5d1c0000 0x0 0x10000>;
139 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 139 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
140 interrupt-parent = <&gic>; 140 interrupt-parent = <&gic>;
141 status = "okay"; 141 status = "okay";
142 142
143 clk: clk { 143 clk: clk {
144 compatible = "fsl,imx8qxp-clk"; 144 compatible = "fsl,imx8qxp-clk";
145 #clock-cells = <1>; 145 #clock-cells = <1>;
146 }; 146 };
147 147
148 iomuxc: iomuxc { 148 iomuxc: iomuxc {
149 compatible = "fsl,imx8qxp-iomuxc"; 149 compatible = "fsl,imx8qxp-iomuxc";
150 }; 150 };
151 }; 151 };
152 152
153 mu13: mu13@5d280000 { 153 mu13: mu13@5d280000 {
154 compatible = "fsl,imx8-mu-dsp"; 154 compatible = "fsl,imx8-mu-dsp";
155 reg = <0x0 0x5d280000 0x0 0x10000>; 155 reg = <0x0 0x5d280000 0x0 0x10000>;
156 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 156 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
157 fsl,dsp_ap_mu_id = <13>; 157 fsl,dsp_ap_mu_id = <13>;
158 status = "okay"; 158 status = "okay";
159 }; 159 };
160 160
161 rtc: rtc { 161 rtc: rtc {
162 compatible = "fsl,imx-sc-rtc"; 162 compatible = "fsl,imx-sc-rtc";
163 }; 163 };
164 164
165 timer { 165 timer {
166 compatible = "arm,armv8-timer"; 166 compatible = "arm,armv8-timer";
167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 167 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 168 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 169 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 170 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
171 clock-frequency = <8000000>; 171 clock-frequency = <8000000>;
172 interrupt-parent = <&gic>; 172 interrupt-parent = <&gic>;
173 }; 173 };
174 174
175 imx8dxl-pm { 175 imx8dxl-pm {
176 compatible = "simple-bus"; 176 compatible = "simple-bus";
177 #address-cells = <1>; 177 #address-cells = <1>;
178 #size-cells = <0>; 178 #size-cells = <0>;
179 179
180 pd_lsio: PD_LSIO { 180 pd_lsio: PD_LSIO {
181 compatible = "nxp,imx8-pd"; 181 compatible = "nxp,imx8-pd";
182 reg = <SC_R_NONE>; 182 reg = <SC_R_NONE>;
183 #power-domain-cells = <0>; 183 #power-domain-cells = <0>;
184 #address-cells = <1>; 184 #address-cells = <1>;
185 #size-cells = <0>; 185 #size-cells = <0>;
186 186
187 pd_lsio_pwm0: PD_LSIO_PWM_0 { 187 pd_lsio_pwm0: PD_LSIO_PWM_0 {
188 reg = <SC_R_PWM_0>; 188 reg = <SC_R_PWM_0>;
189 #power-domain-cells = <0>; 189 #power-domain-cells = <0>;
190 power-domains = <&pd_lsio>; 190 power-domains = <&pd_lsio>;
191 }; 191 };
192 pd_lsio_pwm1: PD_LSIO_PWM_1 { 192 pd_lsio_pwm1: PD_LSIO_PWM_1 {
193 reg = <SC_R_PWM_1>; 193 reg = <SC_R_PWM_1>;
194 #power-domain-cells = <0>; 194 #power-domain-cells = <0>;
195 power-domains = <&pd_lsio>; 195 power-domains = <&pd_lsio>;
196 }; 196 };
197 pd_lsio_pwm2: PD_LSIO_PWM_2 { 197 pd_lsio_pwm2: PD_LSIO_PWM_2 {
198 reg = <SC_R_PWM_2>; 198 reg = <SC_R_PWM_2>;
199 #power-domain-cells = <0>; 199 #power-domain-cells = <0>;
200 power-domains = <&pd_lsio>; 200 power-domains = <&pd_lsio>;
201 }; 201 };
202 pd_lsio_pwm3: PD_LSIO_PWM_3 { 202 pd_lsio_pwm3: PD_LSIO_PWM_3 {
203 reg = <SC_R_PWM_3>; 203 reg = <SC_R_PWM_3>;
204 #power-domain-cells = <0>; 204 #power-domain-cells = <0>;
205 power-domains = <&pd_lsio>; 205 power-domains = <&pd_lsio>;
206 }; 206 };
207 pd_lsio_pwm4: PD_LSIO_PWM_4 { 207 pd_lsio_pwm4: PD_LSIO_PWM_4 {
208 reg = <SC_R_PWM_4>; 208 reg = <SC_R_PWM_4>;
209 #power-domain-cells = <0>; 209 #power-domain-cells = <0>;
210 power-domains = <&pd_lsio>; 210 power-domains = <&pd_lsio>;
211 }; 211 };
212 pd_lsio_pwm5: PD_LSIO_PWM_5 { 212 pd_lsio_pwm5: PD_LSIO_PWM_5 {
213 reg = <SC_R_PWM_5>; 213 reg = <SC_R_PWM_5>;
214 #power-domain-cells = <0>; 214 #power-domain-cells = <0>;
215 power-domains = <&pd_lsio>; 215 power-domains = <&pd_lsio>;
216 }; 216 };
217 pd_lsio_pwm6: PD_LSIO_PWM_6 { 217 pd_lsio_pwm6: PD_LSIO_PWM_6 {
218 reg = <SC_R_PWM_6>; 218 reg = <SC_R_PWM_6>;
219 #power-domain-cells = <0>; 219 #power-domain-cells = <0>;
220 power-domains = <&pd_lsio>; 220 power-domains = <&pd_lsio>;
221 }; 221 };
222 pd_lsio_pwm7: PD_LSIO_PWM_7 { 222 pd_lsio_pwm7: PD_LSIO_PWM_7 {
223 reg = <SC_R_PWM_7>; 223 reg = <SC_R_PWM_7>;
224 #power-domain-cells = <0>; 224 #power-domain-cells = <0>;
225 power-domains = <&pd_lsio>; 225 power-domains = <&pd_lsio>;
226 }; 226 };
227 pd_lsio_kpp: PD_LSIO_KPP { 227 pd_lsio_kpp: PD_LSIO_KPP {
228 reg = <SC_R_KPP>; 228 reg = <SC_R_KPP>;
229 #power-domain-cells = <0>; 229 #power-domain-cells = <0>;
230 power-domains = <&pd_lsio>; 230 power-domains = <&pd_lsio>;
231 }; 231 };
232 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 232 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
233 reg = <SC_R_GPIO_0>; 233 reg = <SC_R_GPIO_0>;
234 #power-domain-cells = <0>; 234 #power-domain-cells = <0>;
235 power-domains = <&pd_lsio>; 235 power-domains = <&pd_lsio>;
236 }; 236 };
237 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 237 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
238 reg = <SC_R_GPIO_1>; 238 reg = <SC_R_GPIO_1>;
239 #power-domain-cells = <0>; 239 #power-domain-cells = <0>;
240 power-domains = <&pd_lsio>; 240 power-domains = <&pd_lsio>;
241 }; 241 };
242 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 242 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
243 reg = <SC_R_GPIO_2>; 243 reg = <SC_R_GPIO_2>;
244 #power-domain-cells = <0>; 244 #power-domain-cells = <0>;
245 power-domains = <&pd_lsio>; 245 power-domains = <&pd_lsio>;
246 }; 246 };
247 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 247 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
248 reg = <SC_R_GPIO_3>; 248 reg = <SC_R_GPIO_3>;
249 #power-domain-cells = <0>; 249 #power-domain-cells = <0>;
250 power-domains = <&pd_lsio>; 250 power-domains = <&pd_lsio>;
251 }; 251 };
252 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 252 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
253 reg = <SC_R_GPIO_4>; 253 reg = <SC_R_GPIO_4>;
254 #power-domain-cells = <0>; 254 #power-domain-cells = <0>;
255 power-domains = <&pd_lsio>; 255 power-domains = <&pd_lsio>;
256 }; 256 };
257 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 257 pd_lsio_gpio5: PD_LSIO_GPIO_5{
258 reg = <SC_R_GPIO_5>; 258 reg = <SC_R_GPIO_5>;
259 #power-domain-cells = <0>; 259 #power-domain-cells = <0>;
260 power-domains = <&pd_lsio>; 260 power-domains = <&pd_lsio>;
261 }; 261 };
262 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 262 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
263 reg = <SC_R_GPIO_6>; 263 reg = <SC_R_GPIO_6>;
264 #power-domain-cells = <0>; 264 #power-domain-cells = <0>;
265 power-domains = <&pd_lsio>; 265 power-domains = <&pd_lsio>;
266 }; 266 };
267 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 267 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
268 reg = <SC_R_GPIO_7>; 268 reg = <SC_R_GPIO_7>;
269 #power-domain-cells = <0>; 269 #power-domain-cells = <0>;
270 power-domains = <&pd_lsio>; 270 power-domains = <&pd_lsio>;
271 }; 271 };
272 pd_lsio_gpt0: PD_LSIO_GPT_0 { 272 pd_lsio_gpt0: PD_LSIO_GPT_0 {
273 reg = <SC_R_GPT_0>; 273 reg = <SC_R_GPT_0>;
274 #power-domain-cells = <0>; 274 #power-domain-cells = <0>;
275 power-domains = <&pd_lsio>; 275 power-domains = <&pd_lsio>;
276 }; 276 };
277 pd_lsio_gpt1: PD_LSIO_GPT_1 { 277 pd_lsio_gpt1: PD_LSIO_GPT_1 {
278 reg = <SC_R_GPT_1>; 278 reg = <SC_R_GPT_1>;
279 #power-domain-cells = <0>; 279 #power-domain-cells = <0>;
280 power-domains = <&pd_lsio>; 280 power-domains = <&pd_lsio>;
281 }; 281 };
282 pd_lsio_gpt2: PD_LSIO_GPT_2 { 282 pd_lsio_gpt2: PD_LSIO_GPT_2 {
283 reg = <SC_R_GPT_2>; 283 reg = <SC_R_GPT_2>;
284 #power-domain-cells = <0>; 284 #power-domain-cells = <0>;
285 power-domains = <&pd_lsio>; 285 power-domains = <&pd_lsio>;
286 }; 286 };
287 pd_lsio_gpt3: PD_LSIO_GPT_3 { 287 pd_lsio_gpt3: PD_LSIO_GPT_3 {
288 reg = <SC_R_GPT_3>; 288 reg = <SC_R_GPT_3>;
289 #power-domain-cells = <0>; 289 #power-domain-cells = <0>;
290 power-domains = <&pd_lsio>; 290 power-domains = <&pd_lsio>;
291 }; 291 };
292 pd_lsio_gpt4: PD_LSIO_GPT_4 { 292 pd_lsio_gpt4: PD_LSIO_GPT_4 {
293 reg = <SC_R_GPT_4>; 293 reg = <SC_R_GPT_4>;
294 #power-domain-cells = <0>; 294 #power-domain-cells = <0>;
295 power-domains = <&pd_lsio>; 295 power-domains = <&pd_lsio>;
296 }; 296 };
297 pd_lsio_flexspi0: PD_LSIO_FSPI_0 { 297 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
298 reg = <SC_R_FSPI_0>; 298 reg = <SC_R_FSPI_0>;
299 #power-domain-cells = <0>; 299 #power-domain-cells = <0>;
300 power-domains = <&pd_lsio>; 300 power-domains = <&pd_lsio>;
301 }; 301 };
302 pd_lsio_flexspi1: PD_LSIO_FSPI_1{ 302 pd_lsio_flexspi1: PD_LSIO_FSPI_1{
303 reg = <SC_R_FSPI_1>; 303 reg = <SC_R_FSPI_1>;
304 #power-domain-cells = <0>; 304 #power-domain-cells = <0>;
305 power-domains = <&pd_lsio>; 305 power-domains = <&pd_lsio>;
306 }; 306 };
307 pd_lsio_mu5a: PD_LSIO_MU5A { 307 pd_lsio_mu5a: PD_LSIO_MU5A {
308 reg = <SC_R_MU_5A>; 308 reg = <SC_R_MU_5A>;
309 #power-domain-cells = <0>; 309 #power-domain-cells = <0>;
310 power-domains = <&pd_lsio>; 310 power-domains = <&pd_lsio>;
311 }; 311 };
312 pd_lsio_mu8a: PD_LSIO_MU8A { 312 pd_lsio_mu8a: PD_LSIO_MU8A {
313 reg = <SC_R_MU_8A>; 313 reg = <SC_R_MU_8A>;
314 #power-domain-cells = <0>; 314 #power-domain-cells = <0>;
315 power-domains = <&pd_lsio>; 315 power-domains = <&pd_lsio>;
316 }; 316 };
317 }; 317 };
318 318
319 pd_conn: PD_CONN { 319 pd_conn: PD_CONN {
320 compatible = "nxp,imx8-pd"; 320 compatible = "nxp,imx8-pd";
321 reg = <SC_R_NONE>; 321 reg = <SC_R_NONE>;
322 #power-domain-cells = <0>; 322 #power-domain-cells = <0>;
323 #address-cells = <1>; 323 #address-cells = <1>;
324 #size-cells = <0>; 324 #size-cells = <0>;
325 325
326 pd_conn_usbotg0: PD_CONN_USB_0 { 326 pd_conn_usbotg0: PD_CONN_USB_0 {
327 reg = <SC_R_USB_0>; 327 reg = <SC_R_USB_0>;
328 #power-domain-cells = <0>; 328 #power-domain-cells = <0>;
329 power-domains = <&pd_conn>; 329 power-domains = <&pd_conn>;
330 #address-cells = <1>; 330 #address-cells = <1>;
331 #size-cells = <0>; 331 #size-cells = <0>;
332 wakeup-irq = <169>; 332 wakeup-irq = <169>;
333 333
334 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { 334 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
335 reg = <SC_R_USB_0_PHY>; 335 reg = <SC_R_USB_0_PHY>;
336 #power-domain-cells = <0>; 336 #power-domain-cells = <0>;
337 power-domains = <&pd_conn_usbotg0>; 337 power-domains = <&pd_conn_usbotg0>;
338 wakeup-irq = <169>; 338 wakeup-irq = <169>;
339 }; 339 };
340 340
341 }; 341 };
342 pd_conn_usbotg1: PD_CONN_USB_1 { 342 pd_conn_usbotg1: PD_CONN_USB_1 {
343 reg = <SC_R_USB_1>; 343 reg = <SC_R_USB_1>;
344 #power-domain-cells = <0>; 344 #power-domain-cells = <0>;
345 power-domains = <&pd_conn>; 345 power-domains = <&pd_conn>;
346 #address-cells = <1>; 346 #address-cells = <1>;
347 #size-cells = <0>; 347 #size-cells = <0>;
348 wakeup-irq = <166>; 348 wakeup-irq = <166>;
349 349
350 pd_conn_usbotg1_phy: PD_CONN_USB_1_PHY { 350 pd_conn_usbotg1_phy: PD_CONN_USB_1_PHY {
351 reg = <SC_R_USB_1_PHY>; 351 reg = <SC_R_USB_1_PHY>;
352 #power-domain-cells = <0>; 352 #power-domain-cells = <0>;
353 power-domains = <&pd_conn_usbotg1>; 353 power-domains = <&pd_conn_usbotg1>;
354 wakeup-irq = <166>; 354 wakeup-irq = <166>;
355 }; 355 };
356 }; 356 };
357 pd_conn_sdch0: PD_CONN_SDHC_0 { 357 pd_conn_sdch0: PD_CONN_SDHC_0 {
358 reg = <SC_R_SDHC_0>; 358 reg = <SC_R_SDHC_0>;
359 #power-domain-cells = <0>; 359 #power-domain-cells = <0>;
360 power-domains = <&pd_conn>; 360 power-domains = <&pd_conn>;
361 }; 361 };
362 pd_conn_sdch1: PD_CONN_SDHC_1 { 362 pd_conn_sdch1: PD_CONN_SDHC_1 {
363 reg = <SC_R_SDHC_1>; 363 reg = <SC_R_SDHC_1>;
364 #power-domain-cells = <0>; 364 #power-domain-cells = <0>;
365 power-domains = <&pd_conn>; 365 power-domains = <&pd_conn>;
366 }; 366 };
367 pd_conn_sdch2: PD_CONN_SDHC_2 { 367 pd_conn_sdch2: PD_CONN_SDHC_2 {
368 reg = <SC_R_SDHC_2>; 368 reg = <SC_R_SDHC_2>;
369 #power-domain-cells = <0>; 369 #power-domain-cells = <0>;
370 power-domains = <&pd_conn>; 370 power-domains = <&pd_conn>;
371 }; 371 };
372 pd_conn_enet0: PD_CONN_ENET_0 { 372 pd_conn_enet0: PD_CONN_ENET_0 {
373 reg = <SC_R_ENET_0>; 373 reg = <SC_R_ENET_0>;
374 #power-domain-cells = <0>; 374 #power-domain-cells = <0>;
375 power-domains = <&pd_conn>; 375 power-domains = <&pd_conn>;
376 wakeup-irq = <258>; 376 wakeup-irq = <258>;
377 }; 377 };
378 pd_conn_enet1: PD_CONN_ENET_1 { 378 pd_conn_enet1: PD_CONN_ENET_1 {
379 reg = <SC_R_ENET_1>; 379 reg = <SC_R_ENET_1>;
380 #power-domain-cells = <0>; 380 #power-domain-cells = <0>;
381 power-domains = <&pd_conn>; 381 power-domains = <&pd_conn>;
382 fsl,wakeup_irq = <262>; 382 fsl,wakeup_irq = <262>;
383 }; 383 };
384 pd_conn_nand: PD_CONN_NAND { 384 pd_conn_nand: PD_CONN_NAND {
385 reg = <SC_R_NAND>; 385 reg = <SC_R_NAND>;
386 #power-domain-cells = <0>; 386 #power-domain-cells = <0>;
387 power-domains = <&pd_conn>; 387 power-domains = <&pd_conn>;
388 }; 388 };
389 }; 389 };
390 390
391 pd_audio: PD_AUDIO { 391 pd_audio: PD_AUDIO {
392 compatible = "nxp,imx8-pd"; 392 compatible = "nxp,imx8-pd";
393 reg = <SC_R_NONE>; 393 reg = <SC_R_NONE>;
394 #power-domain-cells = <0>; 394 #power-domain-cells = <0>;
395 #address-cells = <1>; 395 #address-cells = <1>;
396 #size-cells = <0>; 396 #size-cells = <0>;
397 397
398 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { 398 pd_audio_pll0: PD_AUD_AUDIO_PLL_0 {
399 reg = <SC_R_AUDIO_PLL_0>; 399 reg = <SC_R_AUDIO_PLL_0>;
400 power-domains =<&pd_audio>; 400 power-domains =<&pd_audio>;
401 #power-domain-cells = <0>; 401 #power-domain-cells = <0>;
402 #address-cells = <1>; 402 #address-cells = <1>;
403 #size-cells = <0>; 403 #size-cells = <0>;
404 404
405 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { 405 pd_audio_pll1: PD_AUD_AUDIO_PLL_1 {
406 reg = <SC_R_AUDIO_PLL_1>; 406 reg = <SC_R_AUDIO_PLL_1>;
407 power-domains =<&pd_audio_pll0>; 407 power-domains =<&pd_audio_pll0>;
408 #power-domain-cells = <0>; 408 #power-domain-cells = <0>;
409 #address-cells = <1>; 409 #address-cells = <1>;
410 #size-cells = <0>; 410 #size-cells = <0>;
411 411
412 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { 412 pd_audio_clk0: PD_AUD_AUDIO_CLK_0 {
413 reg = <SC_R_AUDIO_CLK_0>; 413 reg = <SC_R_AUDIO_CLK_0>;
414 power-domains =<&pd_audio_pll1>; 414 power-domains =<&pd_audio_pll1>;
415 #power-domain-cells = <0>; 415 #power-domain-cells = <0>;
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <0>; 417 #size-cells = <0>;
418 418
419 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { 419 pd_audio_clk1: PD_AUD_AUDIO_CLK_1 {
420 reg = <SC_R_AUDIO_CLK_1>; 420 reg = <SC_R_AUDIO_CLK_1>;
421 #power-domain-cells = <0>; 421 #power-domain-cells = <0>;
422 power-domains =<&pd_audio_clk0>; 422 power-domains =<&pd_audio_clk0>;
423 #address-cells = <1>; 423 #address-cells = <1>;
424 #size-cells = <0>; 424 #size-cells = <0>;
425 425
426 pd_dma0_chan0: PD_ASRC_0_RXA { 426 pd_dma0_chan0: PD_ASRC_0_RXA {
427 reg = <SC_R_DMA_0_CH0>; 427 reg = <SC_R_DMA_0_CH0>;
428 power-domains =<&pd_audio_clk1>; 428 power-domains =<&pd_audio_clk1>;
429 #power-domain-cells = <0>; 429 #power-domain-cells = <0>;
430 #address-cells = <1>; 430 #address-cells = <1>;
431 #size-cells = <0>; 431 #size-cells = <0>;
432 432
433 pd_dma0_chan1: PD_ASRC_0_RXB { 433 pd_dma0_chan1: PD_ASRC_0_RXB {
434 reg = <SC_R_DMA_0_CH1>; 434 reg = <SC_R_DMA_0_CH1>;
435 power-domains =<&pd_dma0_chan0>; 435 power-domains =<&pd_dma0_chan0>;
436 #power-domain-cells = <0>; 436 #power-domain-cells = <0>;
437 #address-cells = <1>; 437 #address-cells = <1>;
438 #size-cells = <0>; 438 #size-cells = <0>;
439 439
440 pd_dma0_chan2: PD_ASRC_0_RXC { 440 pd_dma0_chan2: PD_ASRC_0_RXC {
441 reg = <SC_R_DMA_0_CH2>; 441 reg = <SC_R_DMA_0_CH2>;
442 power-domains =<&pd_dma0_chan1>; 442 power-domains =<&pd_dma0_chan1>;
443 #power-domain-cells = <0>; 443 #power-domain-cells = <0>;
444 #address-cells = <1>; 444 #address-cells = <1>;
445 #size-cells = <0>; 445 #size-cells = <0>;
446 446
447 pd_dma0_chan3: PD_ASRC_0_TXA { 447 pd_dma0_chan3: PD_ASRC_0_TXA {
448 reg = <SC_R_DMA_0_CH3>; 448 reg = <SC_R_DMA_0_CH3>;
449 power-domains =<&pd_dma0_chan2>; 449 power-domains =<&pd_dma0_chan2>;
450 #power-domain-cells = <0>; 450 #power-domain-cells = <0>;
451 #address-cells = <1>; 451 #address-cells = <1>;
452 #size-cells = <0>; 452 #size-cells = <0>;
453 453
454 pd_dma0_chan4: PD_ASRC_0_TXB { 454 pd_dma0_chan4: PD_ASRC_0_TXB {
455 reg = <SC_R_DMA_0_CH4>; 455 reg = <SC_R_DMA_0_CH4>;
456 power-domains =<&pd_dma0_chan3>; 456 power-domains =<&pd_dma0_chan3>;
457 #power-domain-cells = <0>; 457 #power-domain-cells = <0>;
458 #address-cells = <1>; 458 #address-cells = <1>;
459 #size-cells = <0>; 459 #size-cells = <0>;
460 460
461 pd_dma0_chan5: PD_ASRC_0_TXC { 461 pd_dma0_chan5: PD_ASRC_0_TXC {
462 reg = <SC_R_DMA_0_CH5>; 462 reg = <SC_R_DMA_0_CH5>;
463 power-domains =<&pd_dma0_chan4>; 463 power-domains =<&pd_dma0_chan4>;
464 #power-domain-cells = <0>; 464 #power-domain-cells = <0>;
465 #address-cells = <1>; 465 #address-cells = <1>;
466 #size-cells = <0>; 466 #size-cells = <0>;
467 467
468 pd_asrc0:PD_AUD_ASRC_0 { 468 pd_asrc0:PD_AUD_ASRC_0 {
469 reg = <SC_R_ASRC_0>; 469 reg = <SC_R_ASRC_0>;
470 #power-domain-cells = <0>; 470 #power-domain-cells = <0>;
471 power-domains =<&pd_dma0_chan5>; 471 power-domains =<&pd_dma0_chan5>;
472 }; 472 };
473 }; 473 };
474 }; 474 };
475 }; 475 };
476 }; 476 };
477 }; 477 };
478 }; 478 };
479 479
480 pd_dma0_chan8: PD_SPDIF_0_RX { 480 pd_dma0_chan8: PD_SPDIF_0_RX {
481 reg = <SC_R_DMA_0_CH8>; 481 reg = <SC_R_DMA_0_CH8>;
482 power-domains =<&pd_audio_clk1>; 482 power-domains =<&pd_audio_clk1>;
483 #power-domain-cells = <0>; 483 #power-domain-cells = <0>;
484 #address-cells = <1>; 484 #address-cells = <1>;
485 #size-cells = <0>; 485 #size-cells = <0>;
486 486
487 pd_dma0_chan9: PD_SPDIF_0_TX { 487 pd_dma0_chan9: PD_SPDIF_0_TX {
488 reg = <SC_R_DMA_0_CH9>; 488 reg = <SC_R_DMA_0_CH9>;
489 power-domains =<&pd_dma0_chan8>; 489 power-domains =<&pd_dma0_chan8>;
490 #power-domain-cells = <0>; 490 #power-domain-cells = <0>;
491 #address-cells = <1>; 491 #address-cells = <1>;
492 #size-cells = <0>; 492 #size-cells = <0>;
493 493
494 pd_spdif0: PD_AUD_SPDIF_0 { 494 pd_spdif0: PD_AUD_SPDIF_0 {
495 reg = <SC_R_SPDIF_0>; 495 reg = <SC_R_SPDIF_0>;
496 #power-domain-cells = <0>; 496 #power-domain-cells = <0>;
497 power-domains =<&pd_dma0_chan9>; 497 power-domains =<&pd_dma0_chan9>;
498 498
499 }; 499 };
500 }; 500 };
501 }; 501 };
502 pd_dma0_chan12: PD_SAI_0_RX { 502 pd_dma0_chan12: PD_SAI_0_RX {
503 reg = <SC_R_DMA_0_CH12>; 503 reg = <SC_R_DMA_0_CH12>;
504 power-domains =<&pd_audio_clk1>; 504 power-domains =<&pd_audio_clk1>;
505 #power-domain-cells = <0>; 505 #power-domain-cells = <0>;
506 #address-cells = <1>; 506 #address-cells = <1>;
507 #size-cells = <0>; 507 #size-cells = <0>;
508 508
509 pd_dma0_chan13: PD_SAI_0_TX { 509 pd_dma0_chan13: PD_SAI_0_TX {
510 reg = <SC_R_DMA_0_CH13>; 510 reg = <SC_R_DMA_0_CH13>;
511 power-domains =<&pd_dma0_chan12>; 511 power-domains =<&pd_dma0_chan12>;
512 #power-domain-cells = <0>; 512 #power-domain-cells = <0>;
513 #address-cells = <1>; 513 #address-cells = <1>;
514 #size-cells = <0>; 514 #size-cells = <0>;
515 515
516 pd_sai0:PD_AUD_SAI_0 { 516 pd_sai0:PD_AUD_SAI_0 {
517 reg = <SC_R_SAI_0>; 517 reg = <SC_R_SAI_0>;
518 #power-domain-cells = <0>; 518 #power-domain-cells = <0>;
519 power-domains =<&pd_dma0_chan13>; 519 power-domains =<&pd_dma0_chan13>;
520 }; 520 };
521 }; 521 };
522 522
523 }; 523 };
524 pd_dma0_chan14: PD_SAI_1_RX { 524 pd_dma0_chan14: PD_SAI_1_RX {
525 reg = <SC_R_DMA_0_CH14>; 525 reg = <SC_R_DMA_0_CH14>;
526 power-domains =<&pd_audio_clk1>; 526 power-domains =<&pd_audio_clk1>;
527 #power-domain-cells = <0>; 527 #power-domain-cells = <0>;
528 #address-cells = <1>; 528 #address-cells = <1>;
529 #size-cells = <0>; 529 #size-cells = <0>;
530 530
531 pd_dma0_chan15: PD_SAI_1_TX { 531 pd_dma0_chan15: PD_SAI_1_TX {
532 reg = <SC_R_DMA_0_CH15>; 532 reg = <SC_R_DMA_0_CH15>;
533 power-domains =<&pd_dma0_chan14>; 533 power-domains =<&pd_dma0_chan14>;
534 #power-domain-cells = <0>; 534 #power-domain-cells = <0>;
535 #address-cells = <1>; 535 #address-cells = <1>;
536 #size-cells = <0>; 536 #size-cells = <0>;
537 537
538 pd_sai1: PD_AUD_SAI_1 { 538 pd_sai1: PD_AUD_SAI_1 {
539 reg = <SC_R_SAI_1>; 539 reg = <SC_R_SAI_1>;
540 #power-domain-cells = <0>; 540 #power-domain-cells = <0>;
541 power-domains =<&pd_dma0_chan15>; 541 power-domains =<&pd_dma0_chan15>;
542 }; 542 };
543 }; 543 };
544 }; 544 };
545 pd_dma0_chan16: PD_SAI_2_RX { 545 pd_dma0_chan16: PD_SAI_2_RX {
546 reg = <SC_R_DMA_0_CH16>; 546 reg = <SC_R_DMA_0_CH16>;
547 power-domains =<&pd_audio_clk1>; 547 power-domains =<&pd_audio_clk1>;
548 #power-domain-cells = <0>; 548 #power-domain-cells = <0>;
549 #address-cells = <1>; 549 #address-cells = <1>;
550 #size-cells = <0>; 550 #size-cells = <0>;
551 pd_sai2: PD_AUD_SAI_2 { 551 pd_sai2: PD_AUD_SAI_2 {
552 reg = <SC_R_SAI_2>; 552 reg = <SC_R_SAI_2>;
553 #power-domain-cells = <0>; 553 #power-domain-cells = <0>;
554 power-domains =<&pd_dma0_chan16>; 554 power-domains =<&pd_dma0_chan16>;
555 }; 555 };
556 }; 556 };
557 pd_dma0_chan17: PD_SAI_3_RX { 557 pd_dma0_chan17: PD_SAI_3_RX {
558 reg = <SC_R_DMA_0_CH17>; 558 reg = <SC_R_DMA_0_CH17>;
559 power-domains =<&pd_audio_clk1>; 559 power-domains =<&pd_audio_clk1>;
560 #power-domain-cells = <0>; 560 #power-domain-cells = <0>;
561 #address-cells = <1>; 561 #address-cells = <1>;
562 #size-cells = <0>; 562 #size-cells = <0>;
563 563
564 pd_sai3: PD_AUD_SAI_3 { 564 pd_sai3: PD_AUD_SAI_3 {
565 reg = <SC_R_SAI_3>; 565 reg = <SC_R_SAI_3>;
566 #power-domain-cells = <0>; 566 #power-domain-cells = <0>;
567 power-domains =<&pd_dma0_chan17>; 567 power-domains =<&pd_dma0_chan17>;
568 }; 568 };
569 }; 569 };
570 pd_gpt5: PD_AUD_GPT_5 { 570 pd_gpt5: PD_AUD_GPT_5 {
571 reg = <SC_R_GPT_5>; 571 reg = <SC_R_GPT_5>;
572 #power-domain-cells = <0>; 572 #power-domain-cells = <0>;
573 power-domains =<&pd_audio_clk1>; 573 power-domains =<&pd_audio_clk1>;
574 }; 574 };
575 pd_gpt6: PD_AUD_GPT_6 { 575 pd_gpt6: PD_AUD_GPT_6 {
576 reg = <SC_R_GPT_6>; 576 reg = <SC_R_GPT_6>;
577 #power-domain-cells = <0>; 577 #power-domain-cells = <0>;
578 power-domains =<&pd_audio_clk1>; 578 power-domains =<&pd_audio_clk1>;
579 }; 579 };
580 pd_gpt7: PD_AUD_GPT_7 { 580 pd_gpt7: PD_AUD_GPT_7 {
581 reg = <SC_R_GPT_7>; 581 reg = <SC_R_GPT_7>;
582 #power-domain-cells = <0>; 582 #power-domain-cells = <0>;
583 power-domains =<&pd_audio_clk1>; 583 power-domains =<&pd_audio_clk1>;
584 }; 584 };
585 pd_gpt8: PD_AUD_GPT_8 { 585 pd_gpt8: PD_AUD_GPT_8 {
586 reg = <SC_R_GPT_8>; 586 reg = <SC_R_GPT_8>;
587 #power-domain-cells = <0>; 587 #power-domain-cells = <0>;
588 power-domains =<&pd_audio_clk1>; 588 power-domains =<&pd_audio_clk1>;
589 }; 589 };
590 pd_mqs0: PD_AUD_MQS_0 { 590 pd_mqs0: PD_AUD_MQS_0 {
591 reg = <SC_R_MQS_0>; 591 reg = <SC_R_MQS_0>;
592 #power-domain-cells = <0>; 592 #power-domain-cells = <0>;
593 power-domains =<&pd_audio_clk1>; 593 power-domains =<&pd_audio_clk1>;
594 }; 594 };
595 pd_mclk_out0: PD_AUD_MCLK_OUT_0 { 595 pd_mclk_out0: PD_AUD_MCLK_OUT_0 {
596 reg = <SC_R_MCLK_OUT_0>; 596 reg = <SC_R_MCLK_OUT_0>;
597 #power-domain-cells = <0>; 597 #power-domain-cells = <0>;
598 power-domains =<&pd_audio_clk1>; 598 power-domains =<&pd_audio_clk1>;
599 }; 599 };
600 pd_mclk_out1: PD_AUD_MCLK_OUT_1 { 600 pd_mclk_out1: PD_AUD_MCLK_OUT_1 {
601 reg = <SC_R_MCLK_OUT_1>; 601 reg = <SC_R_MCLK_OUT_1>;
602 #power-domain-cells = <0>; 602 #power-domain-cells = <0>;
603 power-domains =<&pd_audio_clk1>; 603 power-domains =<&pd_audio_clk1>;
604 }; 604 };
605 }; 605 };
606 }; 606 };
607 }; 607 };
608 }; 608 };
609 }; 609 };
610 610
611 pd_dma: PD_DMA { 611 pd_dma: PD_DMA {
612 compatible = "nxp,imx8-pd"; 612 compatible = "nxp,imx8-pd";
613 reg = <SC_R_NONE>; 613 reg = <SC_R_NONE>;
614 #power-domain-cells = <0>; 614 #power-domain-cells = <0>;
615 #address-cells = <1>; 615 #address-cells = <1>;
616 #size-cells = <0>; 616 #size-cells = <0>;
617 617
618 pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { 618 pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
619 reg = <SC_R_ELCDIF_PLL>; 619 reg = <SC_R_ELCDIF_PLL>;
620 #power-domain-cells = <0>; 620 #power-domain-cells = <0>;
621 power-domains = <&pd_dma>; 621 power-domains = <&pd_dma>;
622 #address-cells = <1>; 622 #address-cells = <1>;
623 #size-cells = <0>; 623 #size-cells = <0>;
624 624
625 pd_dma_lcd0: PD_DMA_LCD_0 { 625 pd_dma_lcd0: PD_DMA_LCD_0 {
626 reg = <SC_R_LCD_0>; 626 reg = <SC_R_LCD_0>;
627 #power-domain-cells = <0>; 627 #power-domain-cells = <0>;
628 power-domains = <&pd_dma_elcdif_pll>; 628 power-domains = <&pd_dma_elcdif_pll>;
629 }; 629 };
630 }; 630 };
631 pd_dma_flexcan0: PD_DMA_CAN_0 { 631 pd_dma_flexcan0: PD_DMA_CAN_0 {
632 reg = <SC_R_CAN_0>; 632 reg = <SC_R_CAN_0>;
633 #power-domain-cells = <0>; 633 #power-domain-cells = <0>;
634 power-domains = <&pd_dma>; 634 power-domains = <&pd_dma>;
635 wakeup-irq = <235>; 635 wakeup-irq = <235>;
636 #address-cells = <1>; 636 #address-cells = <1>;
637 #size-cells = <0>; 637 #size-cells = <0>;
638 638
639 pd_dma_flexcan1: PD_DMA_CAN_1 { 639 pd_dma_flexcan1: PD_DMA_CAN_1 {
640 reg = <SC_R_CAN_1>; 640 reg = <SC_R_CAN_1>;
641 #power-domain-cells = <0>; 641 #power-domain-cells = <0>;
642 power-domains = <&pd_dma_flexcan0>; 642 power-domains = <&pd_dma_flexcan0>;
643 wakeup-irq = <236>; 643 wakeup-irq = <236>;
644 }; 644 };
645 645
646 pd_dma_flexcan2: PD_DMA_CAN_2 { 646 pd_dma_flexcan2: PD_DMA_CAN_2 {
647 reg = <SC_R_CAN_2>; 647 reg = <SC_R_CAN_2>;
648 #power-domain-cells = <0>; 648 #power-domain-cells = <0>;
649 power-domains = <&pd_dma_flexcan0>; 649 power-domains = <&pd_dma_flexcan0>;
650 wakeup-irq = <237>; 650 wakeup-irq = <237>;
651 }; 651 };
652 }; 652 };
653 653
654 pd_dma_ftm0: PD_DMA_FTM_0 { 654 pd_dma_ftm0: PD_DMA_FTM_0 {
655 reg = <SC_R_FTM_0>; 655 reg = <SC_R_FTM_0>;
656 #power-domain-cells = <0>; 656 #power-domain-cells = <0>;
657 power-domains = <&pd_dma>; 657 power-domains = <&pd_dma>;
658 }; 658 };
659 pd_dma_ftm1: PD_DMA_FTM_1 { 659 pd_dma_ftm1: PD_DMA_FTM_1 {
660 reg = <SC_R_FTM_1>; 660 reg = <SC_R_FTM_1>;
661 #power-domain-cells = <0>; 661 #power-domain-cells = <0>;
662 power-domains = <&pd_dma>; 662 power-domains = <&pd_dma>;
663 }; 663 };
664 pd_dma_adc0: PD_DMA_ADC_0 { 664 pd_dma_adc0: PD_DMA_ADC_0 {
665 reg = <SC_R_ADC_0>; 665 reg = <SC_R_ADC_0>;
666 #power-domain-cells = <0>; 666 #power-domain-cells = <0>;
667 power-domains = <&pd_dma>; 667 power-domains = <&pd_dma>;
668 }; 668 };
669 pd_dma_lpi2c0: PD_DMA_I2C_0 { 669 pd_dma_lpi2c0: PD_DMA_I2C_0 {
670 reg = <SC_R_I2C_0>; 670 reg = <SC_R_I2C_0>;
671 #power-domain-cells = <0>; 671 #power-domain-cells = <0>;
672 power-domains = <&pd_dma>; 672 power-domains = <&pd_dma>;
673 }; 673 };
674 pd_dma_lpi2c1: PD_DMA_I2C_1 { 674 pd_dma_lpi2c1: PD_DMA_I2C_1 {
675 reg = <SC_R_I2C_1>; 675 reg = <SC_R_I2C_1>;
676 #power-domain-cells = <0>; 676 #power-domain-cells = <0>;
677 power-domains = <&pd_dma>; 677 power-domains = <&pd_dma>;
678 }; 678 };
679 pd_dma_lpi2c2:PD_DMA_I2C_2 { 679 pd_dma_lpi2c2:PD_DMA_I2C_2 {
680 reg = <SC_R_I2C_2>; 680 reg = <SC_R_I2C_2>;
681 #power-domain-cells = <0>; 681 #power-domain-cells = <0>;
682 power-domains = <&pd_dma>; 682 power-domains = <&pd_dma>;
683 }; 683 };
684 pd_dma_lpi2c3: PD_DMA_I2C_3 { 684 pd_dma_lpi2c3: PD_DMA_I2C_3 {
685 reg = <SC_R_I2C_3>; 685 reg = <SC_R_I2C_3>;
686 #power-domain-cells = <0>; 686 #power-domain-cells = <0>;
687 power-domains = <&pd_dma>; 687 power-domains = <&pd_dma>;
688 }; 688 };
689 pd_dma_lpuart0: PD_DMA_UART0 { 689 pd_dma_lpuart0: PD_DMA_UART0 {
690 reg = <SC_R_UART_0>; 690 reg = <SC_R_UART_0>;
691 #power-domain-cells = <0>; 691 #power-domain-cells = <0>;
692 power-domains = <&pd_dma>; 692 power-domains = <&pd_dma>;
693 wakeup-irq = <345>; 693 wakeup-irq = <345>;
694 }; 694 };
695 pd_dma_lpuart1: PD_DMA_UART1 { 695 pd_dma_lpuart1: PD_DMA_UART1 {
696 reg = <SC_R_UART_1>; 696 reg = <SC_R_UART_1>;
697 #power-domain-cells = <0>; 697 #power-domain-cells = <0>;
698 power-domains = <&pd_dma>; 698 power-domains = <&pd_dma>;
699 #address-cells = <1>; 699 #address-cells = <1>;
700 #size-cells = <0>; 700 #size-cells = <0>;
701 wakeup-irq = <346>; 701 wakeup-irq = <346>;
702 702
703 pd_dma2_chan10: PD_UART1_RX { 703 pd_dma2_chan10: PD_UART1_RX {
704 reg = <SC_R_DMA_2_CH10>; 704 reg = <SC_R_DMA_2_CH10>;
705 power-domains =<&pd_dma_lpuart1>; 705 power-domains =<&pd_dma_lpuart1>;
706 #power-domain-cells = <0>; 706 #power-domain-cells = <0>;
707 #address-cells = <1>; 707 #address-cells = <1>;
708 #size-cells = <0>; 708 #size-cells = <0>;
709 709
710 pd_dma2_chan11: PD_UART1_TX { 710 pd_dma2_chan11: PD_UART1_TX {
711 reg = <SC_R_DMA_2_CH11>; 711 reg = <SC_R_DMA_2_CH11>;
712 power-domains =<&pd_dma2_chan10>; 712 power-domains =<&pd_dma2_chan10>;
713 #power-domain-cells = <0>; 713 #power-domain-cells = <0>;
714 #address-cells = <1>; 714 #address-cells = <1>;
715 #size-cells = <0>; 715 #size-cells = <0>;
716 }; 716 };
717 }; 717 };
718 }; 718 };
719 pd_dma_lpuart2: PD_DMA_UART2 { 719 pd_dma_lpuart2: PD_DMA_UART2 {
720 reg = <SC_R_UART_2>; 720 reg = <SC_R_UART_2>;
721 #power-domain-cells = <0>; 721 #power-domain-cells = <0>;
722 power-domains = <&pd_dma>; 722 power-domains = <&pd_dma>;
723 #address-cells = <1>; 723 #address-cells = <1>;
724 #size-cells = <0>; 724 #size-cells = <0>;
725 wakeup-irq = <347>; 725 wakeup-irq = <347>;
726 726
727 pd_dma2_chan12: PD_UART2_RX { 727 pd_dma2_chan12: PD_UART2_RX {
728 reg = <SC_R_DMA_2_CH12>; 728 reg = <SC_R_DMA_2_CH12>;
729 power-domains =<&pd_dma_lpuart2>; 729 power-domains =<&pd_dma_lpuart2>;
730 #power-domain-cells = <0>; 730 #power-domain-cells = <0>;
731 #address-cells = <1>; 731 #address-cells = <1>;
732 #size-cells = <0>; 732 #size-cells = <0>;
733 733
734 pd_dma2_chan13: PD_UART2_TX { 734 pd_dma2_chan13: PD_UART2_TX {
735 reg = <SC_R_DMA_2_CH13>; 735 reg = <SC_R_DMA_2_CH13>;
736 power-domains =<&pd_dma2_chan12>; 736 power-domains =<&pd_dma2_chan12>;
737 #power-domain-cells = <0>; 737 #power-domain-cells = <0>;
738 #address-cells = <1>; 738 #address-cells = <1>;
739 #size-cells = <0>; 739 #size-cells = <0>;
740 }; 740 };
741 }; 741 };
742 }; 742 };
743 pd_dma_lpuart3: PD_DMA_UART3 { 743 pd_dma_lpuart3: PD_DMA_UART3 {
744 reg = <SC_R_UART_3>; 744 reg = <SC_R_UART_3>;
745 #power-domain-cells = <0>; 745 #power-domain-cells = <0>;
746 power-domains = <&pd_dma>; 746 power-domains = <&pd_dma>;
747 #address-cells = <1>; 747 #address-cells = <1>;
748 #size-cells = <0>; 748 #size-cells = <0>;
749 wakeup-irq = <348>; 749 wakeup-irq = <348>;
750 750
751 pd_dma3_chan14: PD_UART3_RX { 751 pd_dma3_chan14: PD_UART3_RX {
752 reg = <SC_R_DMA_2_CH14>; 752 reg = <SC_R_DMA_2_CH14>;
753 power-domains =<&pd_dma_lpuart3>; 753 power-domains =<&pd_dma_lpuart3>;
754 #power-domain-cells = <0>; 754 #power-domain-cells = <0>;
755 #address-cells = <1>; 755 #address-cells = <1>;
756 #size-cells = <0>; 756 #size-cells = <0>;
757 757
758 pd_dma3_chan15: PD_UART3_TX { 758 pd_dma3_chan15: PD_UART3_TX {
759 reg = <SC_R_DMA_2_CH15>; 759 reg = <SC_R_DMA_2_CH15>;
760 power-domains =<&pd_dma3_chan14>; 760 power-domains =<&pd_dma3_chan14>;
761 #power-domain-cells = <0>; 761 #power-domain-cells = <0>;
762 #address-cells = <1>; 762 #address-cells = <1>;
763 #size-cells = <0>; 763 #size-cells = <0>;
764 }; 764 };
765 }; 765 };
766 }; 766 };
767 pd_dma_lpspi0: PD_DMA_SPI_0 { 767 pd_dma_lpspi0: PD_DMA_SPI_0 {
768 reg = <SC_R_SPI_0>; 768 reg = <SC_R_SPI_0>;
769 #power-domain-cells = <0>; 769 #power-domain-cells = <0>;
770 power-domains = <&pd_dma>; 770 power-domains = <&pd_dma>;
771 }; 771 };
772 pd_dma_lpspi1: PD_DMA_SPI_1 { 772 pd_dma_lpspi1: PD_DMA_SPI_1 {
773 reg = <SC_R_SPI_1>; 773 reg = <SC_R_SPI_1>;
774 #power-domain-cells = <0>; 774 #power-domain-cells = <0>;
775 power-domains = <&pd_dma>; 775 power-domains = <&pd_dma>;
776 }; 776 };
777 pd_dma_lpspi2: PD_DMA_SPI_2 { 777 pd_dma_lpspi2: PD_DMA_SPI_2 {
778 reg = <SC_R_SPI_2>; 778 reg = <SC_R_SPI_2>;
779 #power-domain-cells = <0>; 779 #power-domain-cells = <0>;
780 power-domains = <&pd_dma>; 780 power-domains = <&pd_dma>;
781 }; 781 };
782 pd_dma_lpspi3: PD_DMA_SPI_3 { 782 pd_dma_lpspi3: PD_DMA_SPI_3 {
783 reg = <SC_R_SPI_3>; 783 reg = <SC_R_SPI_3>;
784 #power-domain-cells = <0>; 784 #power-domain-cells = <0>;
785 power-domains = <&pd_dma>; 785 power-domains = <&pd_dma>;
786 }; 786 };
787 pd_dma_pwm0: PD_DMA_PWM_0 { 787 pd_dma_pwm0: PD_DMA_PWM_0 {
788 reg = <SC_R_LCD_0_PWM_0>; 788 reg = <SC_R_LCD_0_PWM_0>;
789 #power-domain-cells = <0>; 789 #power-domain-cells = <0>;
790 power-domains = <&pd_dma>; 790 power-domains = <&pd_dma>;
791 }; 791 };
792 }; 792 };
793 793
794 pd_hsio: hsio-power-domain { 794 pd_hsio: hsio-power-domain {
795 compatible = "nxp,imx8-pd"; 795 compatible = "nxp,imx8-pd";
796 reg = <SC_R_NONE>; 796 reg = <SC_R_NONE>;
797 #power-domain-cells = <0>; 797 #power-domain-cells = <0>;
798 #address-cells = <1>; 798 #address-cells = <1>;
799 #size-cells = <0>; 799 #size-cells = <0>;
800 800
801 pd_hsio_gpio: PD_HSIO_GPIO { 801 pd_hsio_gpio: PD_HSIO_GPIO {
802 reg = <SC_R_HSIO_GPIO>; 802 reg = <SC_R_HSIO_GPIO>;
803 #power-domain-cells = <0>; 803 #power-domain-cells = <0>;
804 power-domains =<&pd_hsio>; 804 power-domains =<&pd_hsio>;
805 #address-cells = <1>; 805 #address-cells = <1>;
806 #size-cells = <0>; 806 #size-cells = <0>;
807 807
808 pd_serdes1: PD_HSIO_SERDES_1 { 808 pd_serdes1: PD_HSIO_SERDES_1 {
809 reg = <SC_R_SERDES_1>; 809 reg = <SC_R_SERDES_1>;
810 #power-domain-cells = <0>; 810 #power-domain-cells = <0>;
811 power-domains =<&pd_hsio_gpio>; 811 power-domains =<&pd_hsio_gpio>;
812 #address-cells = <1>; 812 #address-cells = <1>;
813 #size-cells = <0>; 813 #size-cells = <0>;
814 814
815 pd_pcie: PD_HSIO_PCIE_B { 815 pd_pcie: PD_HSIO_PCIE_B {
816 reg = <SC_R_PCIE_B>; 816 reg = <SC_R_PCIE_B>;
817 #power-domain-cells = <0>; 817 #power-domain-cells = <0>;
818 power-domains =<&pd_serdes1>; 818 power-domains =<&pd_serdes1>;
819 }; 819 };
820 }; 820 };
821 }; 821 };
822 }; 822 };
823 823
824 pd_cm40: PD_CM40 { 824 pd_cm40: PD_CM40 {
825 compatible = "nxp,imx8-pd"; 825 compatible = "nxp,imx8-pd";
826 reg = <SC_R_NONE>; 826 reg = <SC_R_NONE>;
827 #power-domain-cells = <0>; 827 #power-domain-cells = <0>;
828 #address-cells = <1>; 828 #address-cells = <1>;
829 #size-cells = <0>; 829 #size-cells = <0>;
830 830
831 pd_cm40_i2c: PD_CM40_I2C { 831 pd_cm40_i2c: PD_CM40_I2C {
832 reg = <SC_R_M4_0_I2C>; 832 reg = <SC_R_M4_0_I2C>;
833 #power-domain-cells = <0>; 833 #power-domain-cells = <0>;
834 power-domains =<&pd_cm40>; 834 power-domains =<&pd_cm40>;
835 }; 835 };
836 836
837 pd_cm40_intmux: PD_CM40_INTMUX { 837 pd_cm40_intmux: PD_CM40_INTMUX {
838 reg = <SC_R_M4_0_INTMUX>; 838 reg = <SC_R_M4_0_INTMUX>;
839 #power-domain-cells = <0>; 839 #power-domain-cells = <0>;
840 power-domains =<&pd_cm40>; 840 power-domains =<&pd_cm40>;
841 }; 841 };
842 }; 842 };
843 843
844 pd_caam: PD_CAAM { 844 pd_caam: PD_CAAM {
845 compatible = "nxp,imx8-pd"; 845 compatible = "nxp,imx8-pd";
846 reg = <SC_R_NONE>; 846 reg = <SC_R_NONE>;
847 #power-domain-cells = <0>; 847 #power-domain-cells = <0>;
848 #address-cells = <1>; 848 #address-cells = <1>;
849 #size-cells = <0>; 849 #size-cells = <0>;
850 850
851 pd_caam_jr1: PD_CAAM_JR1 { 851 pd_caam_jr1: PD_CAAM_JR1 {
852 reg = <SC_R_CAAM_JR1>; 852 reg = <SC_R_CAAM_JR1>;
853 #power-domain-cells = <0>; 853 #power-domain-cells = <0>;
854 power-domains = <&pd_caam>; 854 power-domains = <&pd_caam>;
855 }; 855 };
856 pd_caam_jr2: PD_CAAM_JR2 { 856 pd_caam_jr2: PD_CAAM_JR2 {
857 reg = <SC_R_CAAM_JR2>; 857 reg = <SC_R_CAAM_JR2>;
858 #power-domain-cells = <0>; 858 #power-domain-cells = <0>;
859 power-domains = <&pd_caam>; 859 power-domains = <&pd_caam>;
860 }; 860 };
861 pd_caam_jr3: PD_CAAM_JR3 { 861 pd_caam_jr3: PD_CAAM_JR3 {
862 reg = <SC_R_CAAM_JR3>; 862 reg = <SC_R_CAAM_JR3>;
863 #power-domain-cells = <0>; 863 #power-domain-cells = <0>;
864 power-domains = <&pd_caam>; 864 power-domains = <&pd_caam>;
865 }; 865 };
866 }; 866 };
867 }; 867 };
868 868
869 tsens: thermal-sensor { 869 tsens: thermal-sensor {
870 compatible = "nxp,imx8qxp-sc-tsens"; 870 compatible = "nxp,imx8qxp-sc-tsens";
871 u-boot,dm-pre-reloc; 871 u-boot,dm-pre-reloc;
872 /* number of the temp sensor on the chip */ 872 /* number of the temp sensor on the chip */
873 tsens-num = <2>; 873 tsens-num = <2>;
874 #thermal-sensor-cells = <1>; 874 #thermal-sensor-cells = <1>;
875 }; 875 };
876 876
877 thermal_zones: thermal-zones { 877 thermal_zones: thermal-zones {
878 /* cpu thermal */ 878 /* cpu thermal */
879 cpu-thermal0 { 879 cpu-thermal0 {
880 polling-delay-passive = <250>; 880 polling-delay-passive = <250>;
881 polling-delay = <2000>; 881 polling-delay = <2000>;
882 /*the slope and offset of the temp sensor */ 882 /*the slope and offset of the temp sensor */
883 thermal-sensors = <&tsens 0>; 883 thermal-sensors = <&tsens 0>;
884 trips { 884 trips {
885 cpu_alert0: trip0 { 885 cpu_alert0: trip0 {
886 temperature = <107000>; 886 temperature = <107000>;
887 hysteresis = <2000>; 887 hysteresis = <2000>;
888 type = "passive"; 888 type = "passive";
889 }; 889 };
890 cpu_crit0: trip1 { 890 cpu_crit0: trip1 {
891 temperature = <127000>; 891 temperature = <127000>;
892 hysteresis = <2000>; 892 hysteresis = <2000>;
893 type = "critical"; 893 type = "critical";
894 }; 894 };
895 }; 895 };
896 cooling-maps { 896 cooling-maps {
897 map0 { 897 map0 {
898 trip = <&cpu_alert0>; 898 trip = <&cpu_alert0>;
899 cooling-device = 899 cooling-device =
900 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 900 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
901 }; 901 };
902 }; 902 };
903 }; 903 };
904 904
905 drc-thermal0 { 905 drc-thermal0 {
906 polling-delay-passive = <250>; 906 polling-delay-passive = <250>;
907 polling-delay = <2000>; 907 polling-delay = <2000>;
908 thermal-sensors = <&tsens 1>; 908 thermal-sensors = <&tsens 1>;
909 status = "disabled"; 909 status = "disabled";
910 trips { 910 trips {
911 drc_alert0: trip0 { 911 drc_alert0: trip0 {
912 temperature = <107000>; 912 temperature = <107000>;
913 hysteresis = <2000>; 913 hysteresis = <2000>;
914 type = "passive"; 914 type = "passive";
915 }; 915 };
916 drc_crit0: trip1 { 916 drc_crit0: trip1 {
917 temperature = <127000>; 917 temperature = <127000>;
918 hysteresis = <2000>; 918 hysteresis = <2000>;
919 type = "critical"; 919 type = "critical";
920 }; 920 };
921 }; 921 };
922 }; 922 };
923 }; 923 };
924 924
925 intmux_cm40: intmux@37400000 { 925 intmux_cm40: intmux@37400000 {
926 compatible = "nxp,imx-intmux"; 926 compatible = "nxp,imx-intmux";
927 reg = <0x0 0x37400000 0x0 0x1000>; 927 reg = <0x0 0x37400000 0x0 0x1000>;
928 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 928 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 935 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
936 interrupt-controller; 936 interrupt-controller;
937 interrupt-parent = <&gic>; 937 interrupt-parent = <&gic>;
938 #interrupt-cells = <2>; 938 #interrupt-cells = <2>;
939 clocks = <&clk IMX8QXP_CM40_IPG_CLK>; 939 clocks = <&clk IMX8QXP_CM40_IPG_CLK>;
940 clock-names = "ipg"; 940 clock-names = "ipg";
941 power-domains = <&pd_cm40_intmux>; 941 power-domains = <&pd_cm40_intmux>;
942 status = "disabled"; 942 status = "disabled";
943 }; 943 };
944 944
945 i2c0_cm40: i2c@37230000 { 945 i2c0_cm40: i2c@37230000 {
946 compatible = "fsl,imx8qm-lpi2c"; 946 compatible = "fsl,imx8qm-lpi2c";
947 reg = <0x0 0x37230000 0x0 0x1000>; 947 reg = <0x0 0x37230000 0x0 0x1000>;
948 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 948 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
949 interrupt-parent = <&intmux_cm40>; 949 interrupt-parent = <&intmux_cm40>;
950 clocks = <&clk IMX8QXP_CM40_I2C_CLK>, 950 clocks = <&clk IMX8QXP_CM40_I2C_CLK>,
951 <&clk IMX8QXP_CM40_I2C_IPG_CLK>; 951 <&clk IMX8QXP_CM40_I2C_IPG_CLK>;
952 clock-names = "per", "ipg"; 952 clock-names = "per", "ipg";
953 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; 953 assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>;
954 assigned-clock-rates = <24000000>; 954 assigned-clock-rates = <24000000>;
955 power-domains = <&pd_cm40_i2c>; 955 power-domains = <&pd_cm40_i2c>;
956 #address-cells = <1>; 956 #address-cells = <1>;
957 #size-cells = <0>; 957 #size-cells = <0>;
958 status = "disabled"; 958 status = "disabled";
959 }; 959 };
960 960
961 adma_lcdif: lcdif@5a180000 { 961 adma_lcdif: lcdif@5a180000 {
962 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; 962 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
963 reg = <0x0 0x5a180000 0x0 0x10000>; 963 reg = <0x0 0x5a180000 0x0 0x10000>;
964 clocks = <&clk IMX8QXP_LCD_CLK>, 964 clocks = <&clk IMX8QXP_LCD_CLK>,
965 <&clk IMX8QXP_LCD_PXL_CLK>, 965 <&clk IMX8QXP_LCD_PXL_CLK>,
966 <&clk IMX8QXP_LCD_IPG_CLK>; 966 <&clk IMX8QXP_LCD_IPG_CLK>;
967 clock-names = "pix", "disp_axi", "axi"; 967 clock-names = "pix", "disp_axi", "axi";
968 assigned-clocks = <&clk IMX8QXP_LCD_SEL>, 968 assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
969 <&clk IMX8QXP_LCD_PXL_SEL>, 969 <&clk IMX8QXP_LCD_PXL_SEL>,
970 <&clk IMX8QXP_ELCDIF_PLL_DIV>; 970 <&clk IMX8QXP_ELCDIF_PLL_DIV>;
971 assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, 971 assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>,
972 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; 972 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
973 assigned-clock-rates = <0>, <24000000>, <804000000>; 973 assigned-clock-rates = <0>, <24000000>, <804000000>;
974 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 974 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
975 power-domains = <&pd_dma_lcd0>; 975 power-domains = <&pd_dma_lcd0>;
976 status = "disabled"; 976 status = "disabled";
977 }; 977 };
978 978
979 pwm_adma_lcdif: pwm@5a190000 { 979 pwm_adma_lcdif: pwm@5a190000 {
980 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; 980 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
981 reg = <0x0 0x5a190000 0 0x1000>; 981 reg = <0x0 0x5a190000 0 0x1000>;
982 clocks = <&clk IMX8QXP_PWM_IPG_CLK>, 982 clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
983 <&clk IMX8QXP_PWM_CLK>; 983 <&clk IMX8QXP_PWM_CLK>;
984 clock-names = "ipg", "per"; 984 clock-names = "ipg", "per";
985 assigned-clocks = <&clk IMX8QXP_PWM_CLK>; 985 assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
986 assigned-clock-rates = <24000000>; 986 assigned-clock-rates = <24000000>;
987 #pwm-cells = <2>; 987 #pwm-cells = <2>;
988 power-domains = <&pd_dma_pwm0>; 988 power-domains = <&pd_dma_pwm0>;
989 status = "disabled"; 989 status = "disabled";
990 }; 990 };
991 991
992 i2c_rpbus_1: i2c-rpbus-1 { 992 i2c_rpbus_1: i2c-rpbus-1 {
993 compatible = "fsl,i2c-rpbus"; 993 compatible = "fsl,i2c-rpbus";
994 status = "disabled"; 994 status = "disabled";
995 }; 995 };
996 996
997 i2c_rpbus_5: i2c-rpbus-5 { 997 i2c_rpbus_5: i2c-rpbus-5 {
998 compatible = "fsl,i2c-rpbus"; 998 compatible = "fsl,i2c-rpbus";
999 status = "disabled"; 999 status = "disabled";
1000 }; 1000 };
1001 1001
1002 i2c_rpbus_12: i2c-rpbus-12 { 1002 i2c_rpbus_12: i2c-rpbus-12 {
1003 compatible = "fsl,i2c-rpbus"; 1003 compatible = "fsl,i2c-rpbus";
1004 status = "disabled"; 1004 status = "disabled";
1005 }; 1005 };
1006 1006
1007 i2c_rpbus_13: i2c-rpbus-13 { 1007 i2c_rpbus_13: i2c-rpbus-13 {
1008 compatible = "fsl,i2c-rpbus"; 1008 compatible = "fsl,i2c-rpbus";
1009 status = "disabled"; 1009 status = "disabled";
1010 }; 1010 };
1011 1011
1012 i2c_rpbus_14: i2c-rpbus-14 { 1012 i2c_rpbus_14: i2c-rpbus-14 {
1013 compatible = "fsl,i2c-rpbus"; 1013 compatible = "fsl,i2c-rpbus";
1014 status = "disabled"; 1014 status = "disabled";
1015 }; 1015 };
1016 1016
1017 i2c_rpbus_15: i2c-rpbus-15 { 1017 i2c_rpbus_15: i2c-rpbus-15 {
1018 compatible = "fsl,i2c-rpbus"; 1018 compatible = "fsl,i2c-rpbus";
1019 status = "disabled"; 1019 status = "disabled";
1020 }; 1020 };
1021 1021
1022 adc0: adc@5a880000 { 1022 adc0: adc@5a880000 {
1023 compatible = "fsl,imx8qxp-adc"; 1023 compatible = "fsl,imx8qxp-adc";
1024 reg = <0x0 0x5a880000 0x0 0x10000>; 1024 reg = <0x0 0x5a880000 0x0 0x10000>;
1025 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1025 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1026 interrupt-parent = <&gic>; 1026 interrupt-parent = <&gic>;
1027 clocks = <&clk IMX8QXP_ADC0_CLK>, 1027 clocks = <&clk IMX8QXP_ADC0_CLK>,
1028 <&clk IMX8QXP_ADC0_IPG_CLK>; 1028 <&clk IMX8QXP_ADC0_IPG_CLK>;
1029 clock-names = "per", "ipg"; 1029 clock-names = "per", "ipg";
1030 assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; 1030 assigned-clocks = <&clk IMX8QXP_ADC0_CLK>;
1031 assigned-clock-rates = <24000000>; 1031 assigned-clock-rates = <24000000>;
1032 power-domains = <&pd_dma_adc0>; 1032 power-domains = <&pd_dma_adc0>;
1033 status = "disabled"; 1033 status = "disabled";
1034 }; 1034 };
1035 1035
1036 i2c0: i2c@5a800000 { 1036 i2c0: i2c@5a800000 {
1037 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1037 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1038 reg = <0x0 0x5a800000 0x0 0x4000>; 1038 reg = <0x0 0x5a800000 0x0 0x4000>;
1039 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1039 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1040 interrupt-parent = <&gic>; 1040 interrupt-parent = <&gic>;
1041 clocks = <&clk IMX8QXP_I2C0_CLK>, 1041 clocks = <&clk IMX8QXP_I2C0_CLK>,
1042 <&clk IMX8QXP_I2C0_IPG_CLK>; 1042 <&clk IMX8QXP_I2C0_IPG_CLK>;
1043 clock-names = "per", "ipg"; 1043 clock-names = "per", "ipg";
1044 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; 1044 assigned-clocks = <&clk IMX8QXP_I2C0_CLK>;
1045 assigned-clock-rates = <24000000>; 1045 assigned-clock-rates = <24000000>;
1046 power-domains = <&pd_dma_lpi2c0>; 1046 power-domains = <&pd_dma_lpi2c0>;
1047 #address-cells = <1>; 1047 #address-cells = <1>;
1048 #size-cells = <0>; 1048 #size-cells = <0>;
1049 status = "disabled"; 1049 status = "disabled";
1050 }; 1050 };
1051 1051
1052 i2c1: i2c@5a810000 { 1052 i2c1: i2c@5a810000 {
1053 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1053 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1054 reg = <0x0 0x5a810000 0x0 0x4000>; 1054 reg = <0x0 0x5a810000 0x0 0x4000>;
1055 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1055 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1056 interrupt-parent = <&gic>; 1056 interrupt-parent = <&gic>;
1057 clocks = <&clk IMX8QXP_I2C1_CLK>, 1057 clocks = <&clk IMX8QXP_I2C1_CLK>,
1058 <&clk IMX8QXP_I2C1_IPG_CLK>; 1058 <&clk IMX8QXP_I2C1_IPG_CLK>;
1059 clock-names = "per", "ipg"; 1059 clock-names = "per", "ipg";
1060 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; 1060 assigned-clocks = <&clk IMX8QXP_I2C1_CLK>;
1061 assigned-clock-rates = <24000000>; 1061 assigned-clock-rates = <24000000>;
1062 power-domains = <&pd_dma_lpi2c1>; 1062 power-domains = <&pd_dma_lpi2c1>;
1063 #address-cells = <1>; 1063 #address-cells = <1>;
1064 #size-cells = <0>; 1064 #size-cells = <0>;
1065 status = "disabled"; 1065 status = "disabled";
1066 }; 1066 };
1067 1067
1068 i2c2: i2c@5a820000 { 1068 i2c2: i2c@5a820000 {
1069 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1069 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1070 reg = <0x0 0x5a820000 0x0 0x4000>; 1070 reg = <0x0 0x5a820000 0x0 0x4000>;
1071 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1071 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1072 interrupt-parent = <&gic>; 1072 interrupt-parent = <&gic>;
1073 clocks = <&clk IMX8QXP_I2C2_CLK>, 1073 clocks = <&clk IMX8QXP_I2C2_CLK>,
1074 <&clk IMX8QXP_I2C2_IPG_CLK>; 1074 <&clk IMX8QXP_I2C2_IPG_CLK>;
1075 clock-names = "per", "ipg"; 1075 clock-names = "per", "ipg";
1076 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; 1076 assigned-clocks = <&clk IMX8QXP_I2C2_CLK>;
1077 assigned-clock-rates = <24000000>; 1077 assigned-clock-rates = <24000000>;
1078 power-domains = <&pd_dma_lpi2c2>; 1078 power-domains = <&pd_dma_lpi2c2>;
1079 #address-cells = <1>; 1079 #address-cells = <1>;
1080 #size-cells = <0>; 1080 #size-cells = <0>;
1081 status = "disabled"; 1081 status = "disabled";
1082 }; 1082 };
1083 1083
1084 i2c3: i2c@5a830000 { 1084 i2c3: i2c@5a830000 {
1085 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1085 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1086 reg = <0x0 0x5a830000 0x0 0x4000>; 1086 reg = <0x0 0x5a830000 0x0 0x4000>;
1087 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1087 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1088 interrupt-parent = <&gic>; 1088 interrupt-parent = <&gic>;
1089 clocks = <&clk IMX8QXP_I2C3_CLK>, 1089 clocks = <&clk IMX8QXP_I2C3_CLK>,
1090 <&clk IMX8QXP_I2C3_IPG_CLK>; 1090 <&clk IMX8QXP_I2C3_IPG_CLK>;
1091 clock-names = "per", "ipg"; 1091 clock-names = "per", "ipg";
1092 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; 1092 assigned-clocks = <&clk IMX8QXP_I2C3_CLK>;
1093 assigned-clock-rates = <24000000>; 1093 assigned-clock-rates = <24000000>;
1094 power-domains = <&pd_dma_lpi2c3>; 1094 power-domains = <&pd_dma_lpi2c3>;
1095 #address-cells = <1>; 1095 #address-cells = <1>;
1096 #size-cells = <0>; 1096 #size-cells = <0>;
1097 status = "disabled"; 1097 status = "disabled";
1098 }; 1098 };
1099 1099
1100 usbphy1: usbphy@0x5b100000 { 1100 usbphy1: usbphy@0x5b100000 {
1101 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 1101 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
1102 reg = <0x0 0x5b100000 0x0 0x1000>; 1102 reg = <0x0 0x5b100000 0x0 0x1000>;
1103 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; 1103 clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>;
1104 power-domains = <&pd_conn_usbotg0_phy>; 1104 power-domains = <&pd_conn_usbotg0_phy>;
1105 }; 1105 };
1106 1106
1107 usbphy2: usbphy@0x5b110000 { 1107 usbphy2: usbphy@0x5b110000 {
1108 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 1108 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
1109 reg = <0x0 0x5b110000 0x0 0x1000>; 1109 reg = <0x0 0x5b110000 0x0 0x1000>;
1110 clocks = <&clk IMX8DXL_USB2_PHY2_IPG_CLK>; 1110 clocks = <&clk IMX8DXL_USB2_PHY2_IPG_CLK>;
1111 power-domains = <&pd_conn_usbotg1_phy>; 1111 power-domains = <&pd_conn_usbotg1_phy>;
1112 }; 1112 };
1113 1113
1114 usbotg1: usb@5b0d0000 { 1114 usbotg1: usb@5b0d0000 {
1115 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; 1115 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
1116 reg = <0x0 0x5b0d0000 0x0 0x200>; 1116 reg = <0x0 0x5b0d0000 0x0 0x200>;
1117 interrupt-parent = <&wu>; 1117 interrupt-parent = <&wu>;
1118 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1118 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
1119 fsl,usbphy = <&usbphy1>; 1119 fsl,usbphy = <&usbphy1>;
1120 clocks = <&clk IMX8QXP_CLK_DUMMY>; 1120 clocks = <&clk IMX8QXP_CLK_DUMMY>;
1121 ahb-burst-config = <0x0>; 1121 ahb-burst-config = <0x0>;
1122 tx-burst-size-dword = <0x10>; 1122 tx-burst-size-dword = <0x10>;
1123 rx-burst-size-dword = <0x10>; 1123 rx-burst-size-dword = <0x10>;
1124 #stream-id-cells = <1>; 1124 #stream-id-cells = <1>;
1125 power-domains = <&pd_conn_usbotg0>; 1125 power-domains = <&pd_conn_usbotg0>;
1126 status = "disabled"; 1126 status = "disabled";
1127 }; 1127 };
1128 1128
1129 usbotg2: usb@5b0e0000 { 1129 usbotg2: usb@5b0e0000 {
1130 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; 1130 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
1131 reg = <0x0 0x5b0e0000 0x0 0x200>; 1131 reg = <0x0 0x5b0e0000 0x0 0x200>;
1132 interrupt-parent = <&wu>; 1132 interrupt-parent = <&wu>;
1133 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1133 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1134 fsl,usbphy = <&usbphy2>; 1134 fsl,usbphy = <&usbphy2>;
1135 clocks = <&clk IMX8QXP_CLK_DUMMY>; 1135 clocks = <&clk IMX8QXP_CLK_DUMMY>;
1136 ahb-burst-config = <0x0>; 1136 ahb-burst-config = <0x0>;
1137 tx-burst-size-dword = <0x10>; 1137 tx-burst-size-dword = <0x10>;
1138 rx-burst-size-dword = <0x10>; 1138 rx-burst-size-dword = <0x10>;
1139 #stream-id-cells = <1>; 1139 #stream-id-cells = <1>;
1140 power-domains = <&pd_conn_usbotg1>; 1140 power-domains = <&pd_conn_usbotg1>;
1141 status = "disabled"; 1141 status = "disabled";
1142 }; 1142 };
1143 1143
1144 flexcan1: can@5a8d0000 { 1144 flexcan1: can@5a8d0000 {
1145 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1145 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1146 reg = <0x0 0x5a8d0000 0x0 0x10000>; 1146 reg = <0x0 0x5a8d0000 0x0 0x10000>;
1147 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1148 interrupt-parent = <&wu>; 1148 interrupt-parent = <&wu>;
1149 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1149 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1150 <&clk IMX8QXP_CAN0_CLK>; 1150 <&clk IMX8QXP_CAN0_CLK>;
1151 clock-names = "ipg", "per"; 1151 clock-names = "ipg", "per";
1152 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1152 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1153 assigned-clock-rates = <40000000>; 1153 assigned-clock-rates = <40000000>;
1154 power-domains = <&pd_dma_flexcan0>; 1154 power-domains = <&pd_dma_flexcan0>;
1155 /* SLSlice[4] */ 1155 /* SLSlice[4] */
1156 clk-src = <0>; 1156 clk-src = <0>;
1157 status = "disabled"; 1157 status = "disabled";
1158 }; 1158 };
1159 1159
1160 flexcan2: can@5a8e0000 { 1160 flexcan2: can@5a8e0000 {
1161 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1161 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1162 reg = <0x0 0x5a8e0000 0x0 0x10000>; 1162 reg = <0x0 0x5a8e0000 0x0 0x10000>;
1163 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1163 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-parent = <&wu>; 1164 interrupt-parent = <&wu>;
1165 /* CAN0 clock and PD is shared among all CAN instances */ 1165 /* CAN0 clock and PD is shared among all CAN instances */
1166 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1166 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1167 <&clk IMX8QXP_CAN0_CLK>; 1167 <&clk IMX8QXP_CAN0_CLK>;
1168 clock-names = "ipg", "per"; 1168 clock-names = "ipg", "per";
1169 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1169 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1170 assigned-clock-rates = <40000000>; 1170 assigned-clock-rates = <40000000>;
1171 power-domains = <&pd_dma_flexcan1>; 1171 power-domains = <&pd_dma_flexcan1>;
1172 /* SLSlice[4] */ 1172 /* SLSlice[4] */
1173 clk-src = <0>; 1173 clk-src = <0>;
1174 status = "disabled"; 1174 status = "disabled";
1175 }; 1175 };
1176 1176
1177 flexcan3: can@5a8f0000 { 1177 flexcan3: can@5a8f0000 {
1178 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; 1178 compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan";
1179 reg = <0x0 0x5a8f0000 0x0 0x10000>; 1179 reg = <0x0 0x5a8f0000 0x0 0x10000>;
1180 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1180 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-parent = <&wu>; 1181 interrupt-parent = <&wu>;
1182 /* CAN0 clock and PD is shared among all CAN instances */ 1182 /* CAN0 clock and PD is shared among all CAN instances */
1183 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, 1183 clocks = <&clk IMX8QXP_CAN0_IPG_CLK>,
1184 <&clk IMX8QXP_CAN0_CLK>; 1184 <&clk IMX8QXP_CAN0_CLK>;
1185 clock-names = "ipg", "per"; 1185 clock-names = "ipg", "per";
1186 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; 1186 assigned-clocks = <&clk IMX8QXP_CAN0_CLK>;
1187 assigned-clock-rates = <40000000>; 1187 assigned-clock-rates = <40000000>;
1188 power-domains = <&pd_dma_flexcan2>; 1188 power-domains = <&pd_dma_flexcan2>;
1189 /* SLSlice[4] */ 1189 /* SLSlice[4] */
1190 clk-src = <0>; 1190 clk-src = <0>;
1191 status = "disabled"; 1191 status = "disabled";
1192 }; 1192 };
1193 1193
1194 dma_apbh: dma-apbh@5b810000 { 1194 dma_apbh: dma-apbh@5b810000 {
1195 compatible = "fsl,imx28-dma-apbh"; 1195 compatible = "fsl,imx28-dma-apbh";
1196 reg = <0x0 0x5b810000 0x0 0x2000>; 1196 reg = <0x0 0x5b810000 0x0 0x2000>;
1197 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1197 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 1200 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
1201 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1201 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1202 #dma-cells = <1>; 1202 #dma-cells = <1>;
1203 dma-channels = <4>; 1203 dma-channels = <4>;
1204 clocks = <&clk IMX8QXP_APBHDMA_CLK>; 1204 clocks = <&clk IMX8QXP_APBHDMA_CLK>;
1205 power-domains = <&pd_conn_nand>; 1205 power-domains = <&pd_conn_nand>;
1206 }; 1206 };
1207 1207
1208 gpmi: gpmi-nand@5b812000{ 1208 gpmi: gpmi-nand@5b812000{
1209 compatible = "fsl,imx8qxp-gpmi-nand"; 1209 compatible = "fsl,imx8qxp-gpmi-nand";
1210 #address-cells = <1>; 1210 #address-cells = <1>;
1211 #size-cells = <1>; 1211 #size-cells = <1>;
1212 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; 1212 reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>;
1213 reg-names = "gpmi-nand", "bch"; 1213 reg-names = "gpmi-nand", "bch";
1214 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1214 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1215 interrupt-names = "bch"; 1215 interrupt-names = "bch";
1216 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, 1216 clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>,
1217 <&clk IMX8QXP_GPMI_APB_CLK>, 1217 <&clk IMX8QXP_GPMI_APB_CLK>,
1218 <&clk IMX8QXP_GPMI_BCH_CLK>, 1218 <&clk IMX8QXP_GPMI_BCH_CLK>,
1219 <&clk IMX8QXP_GPMI_APB_BCH_CLK>, 1219 <&clk IMX8QXP_GPMI_APB_BCH_CLK>,
1220 <&clk IMX8QXP_APBHDMA_CLK>; 1220 <&clk IMX8QXP_APBHDMA_CLK>;
1221 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma"; 1221 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma";
1222 dmas = <&dma_apbh 0>; 1222 dmas = <&dma_apbh 0>;
1223 dma-names = "rx-tx"; 1223 dma-names = "rx-tx";
1224 power-domains = <&pd_conn_nand>; 1224 power-domains = <&pd_conn_nand>;
1225 assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; 1225 assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>;
1226 assigned-clock-rates = <50000000>; 1226 assigned-clock-rates = <50000000>;
1227 status = "disabled"; 1227 status = "disabled";
1228 }; 1228 };
1229 1229
1230 wu: wu { 1230 wu: wu {
1231 compatible = "fsl,imx8-wu"; 1231 compatible = "fsl,imx8-wu";
1232 interrupt-controller; 1232 interrupt-controller;
1233 #interrupt-cells = <3>; 1233 #interrupt-cells = <3>;
1234 interrupt-parent = <&gic>; 1234 interrupt-parent = <&gic>;
1235 }; 1235 };
1236 1236
1237 gpio0: gpio@5d080000 { 1237 gpio0: gpio@5d080000 {
1238 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1238 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1239 reg = <0x0 0x5d080000 0x0 0x10000>; 1239 reg = <0x0 0x5d080000 0x0 0x10000>;
1240 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1240 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1241 gpio-controller; 1241 gpio-controller;
1242 #gpio-cells = <2>; 1242 #gpio-cells = <2>;
1243 power-domains = <&pd_lsio_gpio0>; 1243 power-domains = <&pd_lsio_gpio0>;
1244 interrupt-controller; 1244 interrupt-controller;
1245 #interrupt-cells = <2>; 1245 #interrupt-cells = <2>;
1246 }; 1246 };
1247 1247
1248 gpio1: gpio@5d090000 { 1248 gpio1: gpio@5d090000 {
1249 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1249 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1250 reg = <0x0 0x5d090000 0x0 0x10000>; 1250 reg = <0x0 0x5d090000 0x0 0x10000>;
1251 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1251 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1252 gpio-controller; 1252 gpio-controller;
1253 #gpio-cells = <2>; 1253 #gpio-cells = <2>;
1254 power-domains = <&pd_lsio_gpio1>; 1254 power-domains = <&pd_lsio_gpio1>;
1255 interrupt-controller; 1255 interrupt-controller;
1256 #interrupt-cells = <2>; 1256 #interrupt-cells = <2>;
1257 }; 1257 };
1258 1258
1259 gpio2: gpio@5d0a0000 { 1259 gpio2: gpio@5d0a0000 {
1260 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1260 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1261 reg = <0x0 0x5d0a0000 0x0 0x10000>; 1261 reg = <0x0 0x5d0a0000 0x0 0x10000>;
1262 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1262 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1263 gpio-controller; 1263 gpio-controller;
1264 #gpio-cells = <2>; 1264 #gpio-cells = <2>;
1265 power-domains = <&pd_lsio_gpio2>; 1265 power-domains = <&pd_lsio_gpio2>;
1266 interrupt-controller; 1266 interrupt-controller;
1267 #interrupt-cells = <2>; 1267 #interrupt-cells = <2>;
1268 }; 1268 };
1269 1269
1270 gpio3: gpio@5d0b0000 { 1270 gpio3: gpio@5d0b0000 {
1271 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1271 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1272 reg = <0x0 0x5d0b0000 0x0 0x10000>; 1272 reg = <0x0 0x5d0b0000 0x0 0x10000>;
1273 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1273 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1274 gpio-controller; 1274 gpio-controller;
1275 #gpio-cells = <2>; 1275 #gpio-cells = <2>;
1276 power-domains = <&pd_lsio_gpio3>; 1276 power-domains = <&pd_lsio_gpio3>;
1277 interrupt-controller; 1277 interrupt-controller;
1278 #interrupt-cells = <2>; 1278 #interrupt-cells = <2>;
1279 }; 1279 };
1280 1280
1281 gpio4: gpio@5d0c0000 { 1281 gpio4: gpio@5d0c0000 {
1282 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1282 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1283 reg = <0x0 0x5d0c0000 0x0 0x10000>; 1283 reg = <0x0 0x5d0c0000 0x0 0x10000>;
1284 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1284 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1285 gpio-controller; 1285 gpio-controller;
1286 #gpio-cells = <2>; 1286 #gpio-cells = <2>;
1287 power-domains = <&pd_lsio_gpio4>; 1287 power-domains = <&pd_lsio_gpio4>;
1288 interrupt-controller; 1288 interrupt-controller;
1289 #interrupt-cells = <2>; 1289 #interrupt-cells = <2>;
1290 }; 1290 };
1291 1291
1292 gpio5: gpio@5d0d0000 { 1292 gpio5: gpio@5d0d0000 {
1293 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1293 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1294 reg = <0x0 0x5d0d0000 0x0 0x10000>; 1294 reg = <0x0 0x5d0d0000 0x0 0x10000>;
1295 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1296 gpio-controller; 1296 gpio-controller;
1297 #gpio-cells = <2>; 1297 #gpio-cells = <2>;
1298 power-domains = <&pd_lsio_gpio5>; 1298 power-domains = <&pd_lsio_gpio5>;
1299 interrupt-controller; 1299 interrupt-controller;
1300 #interrupt-cells = <2>; 1300 #interrupt-cells = <2>;
1301 }; 1301 };
1302 1302
1303 gpio6: gpio@5d0e0000 { 1303 gpio6: gpio@5d0e0000 {
1304 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1304 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1305 reg = <0x0 0x5d0e0000 0x0 0x10000>; 1305 reg = <0x0 0x5d0e0000 0x0 0x10000>;
1306 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1306 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1307 gpio-controller; 1307 gpio-controller;
1308 #gpio-cells = <2>; 1308 #gpio-cells = <2>;
1309 power-domains = <&pd_lsio_gpio6>; 1309 power-domains = <&pd_lsio_gpio6>;
1310 interrupt-controller; 1310 interrupt-controller;
1311 #interrupt-cells = <2>; 1311 #interrupt-cells = <2>;
1312 }; 1312 };
1313 1313
1314 gpio7: gpio@5d0f0000 { 1314 gpio7: gpio@5d0f0000 {
1315 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1315 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1316 reg = <0x0 0x5d0f0000 0x0 0x10000>; 1316 reg = <0x0 0x5d0f0000 0x0 0x10000>;
1317 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1317 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1318 gpio-controller; 1318 gpio-controller;
1319 #gpio-cells = <2>; 1319 #gpio-cells = <2>;
1320 power-domains = <&pd_lsio_gpio7>; 1320 power-domains = <&pd_lsio_gpio7>;
1321 interrupt-controller; 1321 interrupt-controller;
1322 #interrupt-cells = <2>; 1322 #interrupt-cells = <2>;
1323 }; 1323 };
1324 1324
1325 ddr_pmu0: ddr_pmu@5c020000 { 1325 ddr_pmu0: ddr_pmu@5c020000 {
1326 compatible = "fsl,imx8-ddr-pmu"; 1326 compatible = "fsl,imx8-ddr-pmu";
1327 reg = <0x0 0x5c020000 0x0 0x10000>; 1327 reg = <0x0 0x5c020000 0x0 0x10000>;
1328 interrupt-parent = <&gic>; 1328 interrupt-parent = <&gic>;
1329 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1330 }; 1330 };
1331 1331
1332 lpspi0: lpspi@5a000000 { 1332 lpspi0: lpspi@5a000000 {
1333 compatible = "fsl,imx7ulp-spi"; 1333 compatible = "fsl,imx7ulp-spi";
1334 reg = <0x0 0x5a000000 0x0 0x10000>; 1334 reg = <0x0 0x5a000000 0x0 0x10000>;
1335 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1335 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1336 interrupt-parent = <&gic>; 1336 interrupt-parent = <&gic>;
1337 clocks = <&clk IMX8QXP_SPI0_CLK>, 1337 clocks = <&clk IMX8QXP_SPI0_CLK>,
1338 <&clk IMX8QXP_SPI0_IPG_CLK>; 1338 <&clk IMX8QXP_SPI0_IPG_CLK>;
1339 clock-names = "per", "ipg"; 1339 clock-names = "per", "ipg";
1340 assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; 1340 assigned-clocks = <&clk IMX8QXP_SPI0_CLK>;
1341 assigned-clock-rates = <20000000>; 1341 assigned-clock-rates = <20000000>;
1342 power-domains = <&pd_dma_lpspi0>; 1342 power-domains = <&pd_dma_lpspi0>;
1343 status = "disabled"; 1343 status = "disabled";
1344 }; 1344 };
1345 1345
1346 lpspi2: lpspi@5a020000 { 1346 lpspi2: lpspi@5a020000 {
1347 compatible = "fsl,imx7ulp-spi"; 1347 compatible = "fsl,imx7ulp-spi";
1348 reg = <0x0 0x5a020000 0x0 0x10000>; 1348 reg = <0x0 0x5a020000 0x0 0x10000>;
1349 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1349 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1350 interrupt-parent = <&gic>; 1350 interrupt-parent = <&gic>;
1351 clocks = <&clk IMX8QXP_SPI2_CLK>, 1351 clocks = <&clk IMX8QXP_SPI2_CLK>,
1352 <&clk IMX8QXP_SPI2_IPG_CLK>; 1352 <&clk IMX8QXP_SPI2_IPG_CLK>;
1353 clock-names = "per", "ipg"; 1353 clock-names = "per", "ipg";
1354 assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; 1354 assigned-clocks = <&clk IMX8QXP_SPI2_CLK>;
1355 assigned-clock-rates = <20000000>; 1355 assigned-clock-rates = <20000000>;
1356 power-domains = <&pd_dma_lpspi2>; 1356 power-domains = <&pd_dma_lpspi2>;
1357 status = "disabled"; 1357 status = "disabled";
1358 }; 1358 };
1359 1359
1360 lpuart0: serial@5a060000 { 1360 lpuart0: serial@5a060000 {
1361 compatible = "fsl,imx8qm-lpuart"; 1361 compatible = "fsl,imx8qm-lpuart";
1362 reg = <0x0 0x5a060000 0x0 0x1000>; 1362 reg = <0x0 0x5a060000 0x0 0x1000>;
1363 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1363 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-parent = <&wu>; 1364 interrupt-parent = <&wu>;
1365 clocks = <&clk IMX8QXP_UART0_CLK>, 1365 clocks = <&clk IMX8QXP_UART0_CLK>,
1366 <&clk IMX8QXP_UART0_IPG_CLK>; 1366 <&clk IMX8QXP_UART0_IPG_CLK>;
1367 clock-names = "per", "ipg"; 1367 clock-names = "per", "ipg";
1368 assigned-clocks = <&clk IMX8QXP_UART0_CLK>; 1368 assigned-clocks = <&clk IMX8QXP_UART0_CLK>;
1369 assigned-clock-rates = <80000000>; 1369 assigned-clock-rates = <80000000>;
1370 power-domains = <&pd_dma_lpuart0>; 1370 power-domains = <&pd_dma_lpuart0>;
1371 status = "disabled"; 1371 status = "disabled";
1372 }; 1372 };
1373 1373
1374 lpuart1: serial@5a070000 { 1374 lpuart1: serial@5a070000 {
1375 compatible = "fsl,imx8qm-lpuart"; 1375 compatible = "fsl,imx8qm-lpuart";
1376 reg = <0x0 0x5a070000 0x0 0x1000>; 1376 reg = <0x0 0x5a070000 0x0 0x1000>;
1377 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1377 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-parent = <&wu>; 1378 interrupt-parent = <&wu>;
1379 clocks = <&clk IMX8QXP_UART1_CLK>, 1379 clocks = <&clk IMX8QXP_UART1_CLK>,
1380 <&clk IMX8QXP_UART1_IPG_CLK>; 1380 <&clk IMX8QXP_UART1_IPG_CLK>;
1381 clock-names = "per", "ipg"; 1381 clock-names = "per", "ipg";
1382 assigned-clocks = <&clk IMX8QXP_UART1_CLK>; 1382 assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
1383 assigned-clock-rates = <80000000>; 1383 assigned-clock-rates = <80000000>;
1384 power-domains = <&pd_dma2_chan11>; 1384 power-domains = <&pd_dma2_chan11>;
1385 dma-names = "tx","rx"; 1385 dma-names = "tx","rx";
1386 dmas = <&edma2 11 0 0>, 1386 dmas = <&edma2 11 0 0>,
1387 <&edma2 10 0 1>; 1387 <&edma2 10 0 1>;
1388 status = "disabled"; 1388 status = "disabled";
1389 }; 1389 };
1390 1390
1391 lpuart2: serial@5a080000 { 1391 lpuart2: serial@5a080000 {
1392 compatible = "fsl,imx8qm-lpuart"; 1392 compatible = "fsl,imx8qm-lpuart";
1393 reg = <0x0 0x5a080000 0x0 0x1000>; 1393 reg = <0x0 0x5a080000 0x0 0x1000>;
1394 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1394 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1395 interrupt-parent = <&wu>; 1395 interrupt-parent = <&wu>;
1396 clocks = <&clk IMX8QXP_UART2_CLK>, 1396 clocks = <&clk IMX8QXP_UART2_CLK>,
1397 <&clk IMX8QXP_UART2_IPG_CLK>; 1397 <&clk IMX8QXP_UART2_IPG_CLK>;
1398 clock-names = "per", "ipg"; 1398 clock-names = "per", "ipg";
1399 assigned-clocks = <&clk IMX8QXP_UART2_CLK>; 1399 assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
1400 assigned-clock-rates = <80000000>; 1400 assigned-clock-rates = <80000000>;
1401 power-domains = <&pd_dma2_chan13>; 1401 power-domains = <&pd_dma2_chan13>;
1402 dma-names = "tx","rx"; 1402 dma-names = "tx","rx";
1403 dmas = <&edma2 13 0 0>, 1403 dmas = <&edma2 13 0 0>,
1404 <&edma2 12 0 1>; 1404 <&edma2 12 0 1>;
1405 status = "disabled"; 1405 status = "disabled";
1406 }; 1406 };
1407 1407
1408 lpuart3: serial@5a090000 { 1408 lpuart3: serial@5a090000 {
1409 compatible = "fsl,imx8qm-lpuart"; 1409 compatible = "fsl,imx8qm-lpuart";
1410 reg = <0x0 0x5a090000 0x0 0x1000>; 1410 reg = <0x0 0x5a090000 0x0 0x1000>;
1411 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1411 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1412 interrupt-parent = <&wu>; 1412 interrupt-parent = <&wu>;
1413 clocks = <&clk IMX8QXP_UART3_CLK>, 1413 clocks = <&clk IMX8QXP_UART3_CLK>,
1414 <&clk IMX8QXP_UART3_IPG_CLK>; 1414 <&clk IMX8QXP_UART3_IPG_CLK>;
1415 clock-names = "per", "ipg"; 1415 clock-names = "per", "ipg";
1416 assigned-clocks = <&clk IMX8QXP_UART3_CLK>; 1416 assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
1417 assigned-clock-rates = <80000000>; 1417 assigned-clock-rates = <80000000>;
1418 power-domains = <&pd_dma3_chan15>; 1418 power-domains = <&pd_dma3_chan15>;
1419 dma-names = "tx","rx"; 1419 dma-names = "tx","rx";
1420 dmas = <&edma2 15 0 0>, 1420 dmas = <&edma2 15 0 0>,
1421 <&edma2 14 0 1>; 1421 <&edma2 14 0 1>;
1422 status = "disabled"; 1422 status = "disabled";
1423 }; 1423 };
1424 1424
1425 edma2: dma-controller@5a1f0000 { 1425 edma2: dma-controller@5a1f0000 {
1426 compatible = "fsl,imx8qm-edma"; 1426 compatible = "fsl,imx8qm-edma";
1427 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ 1427 reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */
1428 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ 1428 <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */
1429 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ 1429 <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */
1430 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ 1430 <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */
1431 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ 1431 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */
1432 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ 1432 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */
1433 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ 1433 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */
1434 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ 1434 <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */
1435 #dma-cells = <3>; 1435 #dma-cells = <3>;
1436 dma-channels = <8>; 1436 dma-channels = <8>;
1437 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1437 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
1438 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
1439 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1444 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", 1445 interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
1446 "edma2-chan10-rx", "edma2-chan11-tx", 1446 "edma2-chan10-rx", "edma2-chan11-tx",
1447 "edma2-chan12-rx", "edma2-chan13-tx", 1447 "edma2-chan12-rx", "edma2-chan13-tx",
1448 "edma2-chan14-rx", "edma2-chan15-tx"; 1448 "edma2-chan14-rx", "edma2-chan15-tx";
1449 status = "okay"; 1449 status = "okay";
1450 }; 1450 };
1451 1451
1452 edma0: dma-controller@591F0000 { 1452 edma0: dma-controller@591F0000 {
1453 compatible = "fsl,imx8qm-edma"; 1453 compatible = "fsl,imx8qm-edma";
1454 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ 1454 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
1455 <0x0 0x59210000 0x0 0x10000>, 1455 <0x0 0x59210000 0x0 0x10000>,
1456 <0x0 0x59220000 0x0 0x10000>, 1456 <0x0 0x59220000 0x0 0x10000>,
1457 <0x0 0x59230000 0x0 0x10000>, 1457 <0x0 0x59230000 0x0 0x10000>,
1458 <0x0 0x59240000 0x0 0x10000>, 1458 <0x0 0x59240000 0x0 0x10000>,
1459 <0x0 0x59250000 0x0 0x10000>, 1459 <0x0 0x59250000 0x0 0x10000>,
1460 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ 1460 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
1461 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ 1461 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
1462 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ 1462 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
1463 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ 1463 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
1464 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ 1464 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
1465 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ 1465 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
1466 <0x0 0x59350000 0x0 0x10000>, 1466 <0x0 0x59350000 0x0 0x10000>,
1467 <0x0 0x59370000 0x0 0x10000>; 1467 <0x0 0x59370000 0x0 0x10000>;
1468 #dma-cells = <3>; 1468 #dma-cells = <3>;
1469 shared-interrupt; 1469 shared-interrupt;
1470 dma-channels = <16>; 1470 dma-channels = <16>;
1471 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ 1471 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
1472 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 1477 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
1478 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 1479 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
1480 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 1481 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
1482 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 1484 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
1485 interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ 1485 interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
1486 "edma0-chan2-rx", "edma0-chan3-tx", 1486 "edma0-chan2-rx", "edma0-chan3-tx",
1487 "edma0-chan4-tx", "edma0-chan5-tx", 1487 "edma0-chan4-tx", "edma0-chan5-tx",
1488 "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ 1488 "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
1489 "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ 1489 "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
1490 "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ 1490 "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
1491 "edma0-chan21-tx", /* gpt0 */ 1491 "edma0-chan21-tx", /* gpt0 */
1492 "edma0-chan23-rx"; /* gpt2 */ 1492 "edma0-chan23-rx"; /* gpt2 */
1493 status = "okay"; 1493 status = "okay";
1494 }; 1494 };
1495 acm: acm@59e00000 { 1495 acm: acm@59e00000 {
1496 compatible = "nxp,imx8qm-acm"; 1496 compatible = "nxp,imx8qm-acm";
1497 reg = <0x0 0x59e00000 0x0 0x1D0000>; 1497 reg = <0x0 0x59e00000 0x0 0x1D0000>;
1498 status = "disabled"; 1498 status = "disabled";
1499 }; 1499 };
1500 1500
1501 sai0: sai@59040000 { 1501 sai0: sai@59040000 {
1502 compatible = "fsl,imx8qm-sai"; 1502 compatible = "fsl,imx8qm-sai";
1503 reg = <0x0 0x59040000 0x0 0x10000>; 1503 reg = <0x0 0x59040000 0x0 0x10000>;
1504 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1504 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, 1505 clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>,
1506 <&clk IMX8QXP_CLK_DUMMY>, 1506 <&clk IMX8QXP_CLK_DUMMY>,
1507 <&clk IMX8QXP_AUD_SAI_0_MCLK>, 1507 <&clk IMX8QXP_AUD_SAI_0_MCLK>,
1508 <&clk IMX8QXP_CLK_DUMMY>, 1508 <&clk IMX8QXP_CLK_DUMMY>,
1509 <&clk IMX8QXP_CLK_DUMMY>; 1509 <&clk IMX8QXP_CLK_DUMMY>;
1510 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1510 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1511 dma-names = "rx", "tx"; 1511 dma-names = "rx", "tx";
1512 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; 1512 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
1513 status = "disabled"; 1513 status = "disabled";
1514 power-domains = <&pd_sai0>; 1514 power-domains = <&pd_sai0>;
1515 }; 1515 };
1516 1516
1517 sai1: sai@59050000 { 1517 sai1: sai@59050000 {
1518 compatible = "fsl,imx8qm-sai"; 1518 compatible = "fsl,imx8qm-sai";
1519 reg = <0x0 0x59050000 0x0 0x10000>; 1519 reg = <0x0 0x59050000 0x0 0x10000>;
1520 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1520 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1521 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, 1521 clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>,
1522 <&clk IMX8QXP_CLK_DUMMY>, 1522 <&clk IMX8QXP_CLK_DUMMY>,
1523 <&clk IMX8QXP_AUD_SAI_1_MCLK>, 1523 <&clk IMX8QXP_AUD_SAI_1_MCLK>,
1524 <&clk IMX8QXP_CLK_DUMMY>, 1524 <&clk IMX8QXP_CLK_DUMMY>,
1525 <&clk IMX8QXP_CLK_DUMMY>; 1525 <&clk IMX8QXP_CLK_DUMMY>;
1526 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1526 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1527 dma-names = "rx", "tx"; 1527 dma-names = "rx", "tx";
1528 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; 1528 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
1529 status = "disabled"; 1529 status = "disabled";
1530 power-domains = <&pd_sai1>; 1530 power-domains = <&pd_sai1>;
1531 }; 1531 };
1532 1532
1533 sai2: sai@59060000 { 1533 sai2: sai@59060000 {
1534 compatible = "fsl,imx8qm-sai"; 1534 compatible = "fsl,imx8qm-sai";
1535 reg = <0x0 0x59060000 0x0 0x10000>; 1535 reg = <0x0 0x59060000 0x0 0x10000>;
1536 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1536 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1537 clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, 1537 clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>,
1538 <&clk IMX8QXP_CLK_DUMMY>, 1538 <&clk IMX8QXP_CLK_DUMMY>,
1539 <&clk IMX8QXP_AUD_SAI_2_MCLK>, 1539 <&clk IMX8QXP_AUD_SAI_2_MCLK>,
1540 <&clk IMX8QXP_CLK_DUMMY>, 1540 <&clk IMX8QXP_CLK_DUMMY>,
1541 <&clk IMX8QXP_CLK_DUMMY>; 1541 <&clk IMX8QXP_CLK_DUMMY>;
1542 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1542 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1543 dma-names = "rx"; 1543 dma-names = "rx";
1544 dmas = <&edma0 16 0 1>; 1544 dmas = <&edma0 16 0 1>;
1545 status = "disabled"; 1545 status = "disabled";
1546 power-domains = <&pd_sai2>; 1546 power-domains = <&pd_sai2>;
1547 }; 1547 };
1548 1548
1549 sai3: sai@59070000 { 1549 sai3: sai@59070000 {
1550 compatible = "fsl,imx8qm-sai"; 1550 compatible = "fsl,imx8qm-sai";
1551 reg = <0x0 0x59070000 0x0 0x10000>; 1551 reg = <0x0 0x59070000 0x0 0x10000>;
1552 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 1552 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
1553 clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, 1553 clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>,
1554 <&clk IMX8QXP_CLK_DUMMY>, 1554 <&clk IMX8QXP_CLK_DUMMY>,
1555 <&clk IMX8QXP_AUD_SAI_3_MCLK>, 1555 <&clk IMX8QXP_AUD_SAI_3_MCLK>,
1556 <&clk IMX8QXP_CLK_DUMMY>, 1556 <&clk IMX8QXP_CLK_DUMMY>,
1557 <&clk IMX8QXP_CLK_DUMMY>; 1557 <&clk IMX8QXP_CLK_DUMMY>;
1558 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1558 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1559 dma-names = "rx"; 1559 dma-names = "rx";
1560 dmas = <&edma0 17 0 1>; 1560 dmas = <&edma0 17 0 1>;
1561 status = "disabled"; 1561 status = "disabled";
1562 power-domains = <&pd_sai3>; 1562 power-domains = <&pd_sai3>;
1563 }; 1563 };
1564 1564
1565 asrc0: asrc@59000000 { 1565 asrc0: asrc@59000000 {
1566 compatible = "fsl,imx8qm-asrc0"; 1566 compatible = "fsl,imx8qm-asrc0";
1567 reg = <0x0 0x59000000 0x0 0x10000>; 1567 reg = <0x0 0x59000000 0x0 0x10000>;
1568 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1568 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1569 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
1570 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, 1570 clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>,
1571 <&clk IMX8QXP_CLK_DUMMY>, 1571 <&clk IMX8QXP_CLK_DUMMY>,
1572 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, 1572 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
1573 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, 1573 <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
1574 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, 1574 <&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
1575 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, 1575 <&clk IMX8QXP_ACM_AUD_CLK1_SEL>,
1576 <&clk IMX8QXP_CLK_DUMMY>, 1576 <&clk IMX8QXP_CLK_DUMMY>,
1577 <&clk IMX8QXP_CLK_DUMMY>, 1577 <&clk IMX8QXP_CLK_DUMMY>,
1578 <&clk IMX8QXP_CLK_DUMMY>, 1578 <&clk IMX8QXP_CLK_DUMMY>,
1579 <&clk IMX8QXP_CLK_DUMMY>, 1579 <&clk IMX8QXP_CLK_DUMMY>,
1580 <&clk IMX8QXP_CLK_DUMMY>, 1580 <&clk IMX8QXP_CLK_DUMMY>,
1581 <&clk IMX8QXP_CLK_DUMMY>, 1581 <&clk IMX8QXP_CLK_DUMMY>,
1582 <&clk IMX8QXP_CLK_DUMMY>, 1582 <&clk IMX8QXP_CLK_DUMMY>,
1583 <&clk IMX8QXP_CLK_DUMMY>, 1583 <&clk IMX8QXP_CLK_DUMMY>,
1584 <&clk IMX8QXP_CLK_DUMMY>, 1584 <&clk IMX8QXP_CLK_DUMMY>,
1585 <&clk IMX8QXP_CLK_DUMMY>, 1585 <&clk IMX8QXP_CLK_DUMMY>,
1586 <&clk IMX8QXP_CLK_DUMMY>, 1586 <&clk IMX8QXP_CLK_DUMMY>,
1587 <&clk IMX8QXP_CLK_DUMMY>, 1587 <&clk IMX8QXP_CLK_DUMMY>,
1588 <&clk IMX8QXP_CLK_DUMMY>; 1588 <&clk IMX8QXP_CLK_DUMMY>;
1589 clock-names = "ipg", "mem", 1589 clock-names = "ipg", "mem",
1590 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 1590 "asrck_0", "asrck_1", "asrck_2", "asrck_3",
1591 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 1591 "asrck_4", "asrck_5", "asrck_6", "asrck_7",
1592 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 1592 "asrck_8", "asrck_9", "asrck_a", "asrck_b",
1593 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 1593 "asrck_c", "asrck_d", "asrck_e", "asrck_f",
1594 "spba"; 1594 "spba";
1595 dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, 1595 dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
1596 <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; 1596 <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
1597 dma-names = "rxa", "rxb", "rxc", 1597 dma-names = "rxa", "rxb", "rxc",
1598 "txa", "txb", "txc"; 1598 "txa", "txb", "txc";
1599 fsl,asrc-rate = <8000>; 1599 fsl,asrc-rate = <8000>;
1600 fsl,asrc-width = <16>; 1600 fsl,asrc-width = <16>;
1601 power-domains = <&pd_asrc0>; 1601 power-domains = <&pd_asrc0>;
1602 status = "disabled"; 1602 status = "disabled";
1603 }; 1603 };
1604 1604
1605 mqs: mqs@59850000 { 1605 mqs: mqs@59850000 {
1606 compatible = "fsl,imx8qm-mqs"; 1606 compatible = "fsl,imx8qm-mqs";
1607 reg = <0x0 0x59850000 0x0 0x10000>; 1607 reg = <0x0 0x59850000 0x0 0x10000>;
1608 clocks = <&clk IMX8QXP_AUD_MQS_IPG>, 1608 clocks = <&clk IMX8QXP_AUD_MQS_IPG>,
1609 <&clk IMX8QXP_AUD_MQS_HMCLK>; 1609 <&clk IMX8QXP_AUD_MQS_HMCLK>;
1610 clock-names = "core", "mclk"; 1610 clock-names = "core", "mclk";
1611 power-domains = <&pd_mqs0>; 1611 power-domains = <&pd_mqs0>;
1612 status = "disabled"; 1612 status = "disabled";
1613 }; 1613 };
1614 1614
1615 usdhc1: usdhc@5b010000 { 1615 usdhc1: usdhc@5b010000 {
1616 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1616 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1617 interrupt-parent = <&gic>; 1617 interrupt-parent = <&gic>;
1618 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1618 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1619 reg = <0x0 0x5b010000 0x0 0x10000>; 1619 reg = <0x0 0x5b010000 0x0 0x10000>;
1620 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, 1620 clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
1621 <&clk IMX8QXP_SDHC0_CLK>, 1621 <&clk IMX8QXP_SDHC0_CLK>,
1622 <&clk IMX8QXP_SDHC0_AHB_CLK>; 1622 <&clk IMX8QXP_SDHC0_AHB_CLK>;
1623 clock-names = "ipg", "per", "ahb"; 1623 clock-names = "ipg", "per", "ahb";
1624 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; 1624 assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
1625 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 1625 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
1626 assigned-clock-rates = <0>, <400000000>; 1626 assigned-clock-rates = <0>, <400000000>;
1627 power-domains = <&pd_conn_sdch0>; 1627 power-domains = <&pd_conn_sdch0>;
1628 fsl,tuning-start-tap = <20>; 1628 fsl,tuning-start-tap = <20>;
1629 fsl,tuning-step= <2>; 1629 fsl,tuning-step= <2>;
1630 status = "disabled"; 1630 status = "disabled";
1631 }; 1631 };
1632 1632
1633 usdhc2: usdhc@5b020000 { 1633 usdhc2: usdhc@5b020000 {
1634 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1634 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1635 interrupt-parent = <&gic>; 1635 interrupt-parent = <&gic>;
1636 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1636 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1637 reg = <0x0 0x5b020000 0x0 0x10000>; 1637 reg = <0x0 0x5b020000 0x0 0x10000>;
1638 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, 1638 clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>,
1639 <&clk IMX8QXP_SDHC1_CLK>, 1639 <&clk IMX8QXP_SDHC1_CLK>,
1640 <&clk IMX8QXP_SDHC1_AHB_CLK>; 1640 <&clk IMX8QXP_SDHC1_AHB_CLK>;
1641 clock-names = "ipg", "per", "ahb"; 1641 clock-names = "ipg", "per", "ahb";
1642 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; 1642 assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>;
1643 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 1643 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
1644 assigned-clock-rates = <0>, <200000000>; 1644 assigned-clock-rates = <0>, <200000000>;
1645 power-domains = <&pd_conn_sdch1>; 1645 power-domains = <&pd_conn_sdch1>;
1646 fsl,tuning-start-tap = <20>; 1646 fsl,tuning-start-tap = <20>;
1647 fsl,tuning-step= <2>; 1647 fsl,tuning-step= <2>;
1648 status = "disabled"; 1648 status = "disabled";
1649 }; 1649 };
1650 1650
1651 usdhc3: usdhc@5b030000 { 1651 usdhc3: usdhc@5b030000 {
1652 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1652 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1653 interrupt-parent = <&gic>; 1653 interrupt-parent = <&gic>;
1654 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1655 reg = <0x0 0x5b030000 0x0 0x10000>; 1655 reg = <0x0 0x5b030000 0x0 0x10000>;
1656 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, 1656 clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>,
1657 <&clk IMX8QXP_SDHC2_CLK>, 1657 <&clk IMX8QXP_SDHC2_CLK>,
1658 <&clk IMX8QXP_SDHC2_AHB_CLK>; 1658 <&clk IMX8QXP_SDHC2_AHB_CLK>;
1659 clock-names = "ipg", "per", "ahb"; 1659 clock-names = "ipg", "per", "ahb";
1660 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; 1660 assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>;
1661 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; 1661 assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>;
1662 assigned-clock-rates = <0>, <200000000>; 1662 assigned-clock-rates = <0>, <200000000>;
1663 power-domains = <&pd_conn_sdch2>; 1663 power-domains = <&pd_conn_sdch2>;
1664 status = "disabled"; 1664 status = "disabled";
1665 }; 1665 };
1666 1666
1667 fec1: ethernet@5b040000 { 1667 fec1: ethernet@5b040000 {
1668 compatible = "fsl,imx8qm-fec"; 1668 compatible = "fsl,imx8qm-fec";
1669 reg = <0x0 0x5b040000 0x0 0x10000>; 1669 reg = <0x0 0x5b040000 0x0 0x10000>;
1670 interrupt-parent = <&wu>; 1670 interrupt-parent = <&wu>;
1671 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1671 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1672 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1672 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1673 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1673 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1674 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1674 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
1675 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, 1675 clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>,
1676 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; 1676 <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>;
1677 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 1677 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
1678 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, 1678 assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>,
1679 <&clk IMX8QXP_ENET0_REF_DIV>; 1679 <&clk IMX8QXP_ENET0_REF_DIV>;
1680 assigned-clock-rates = <250000000>, <125000000>; 1680 assigned-clock-rates = <250000000>, <125000000>;
1681 fsl,num-tx-queues=<3>; 1681 fsl,num-tx-queues=<3>;
1682 fsl,num-rx-queues=<3>; 1682 fsl,num-rx-queues=<3>;
1683 fsl,wakeup_irq = <0>; 1683 fsl,wakeup_irq = <0>;
1684 power-domains = <&pd_conn_enet0>; 1684 power-domains = <&pd_conn_enet0>;
1685 status = "disabled"; 1685 status = "disabled";
1686 }; 1686 };
1687 1687
1688 eqos: ethernet@5b050000 { 1688 eqos: ethernet@5b050000 {
1689 compatible = "fsl,imx-eqos"; 1689 compatible = "fsl,imx-eqos";
1690 reg = <0x0 0x5b050000 0x0 0x10000>; 1690 reg = <0x0 0x5b050000 0x0 0x10000>;
1691 interrupt-parent = <&wu>; 1691 interrupt-parent = <&wu>;
1692 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1692 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1693 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1693 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
1694 clocks = <&clk IMX8DXL_EQOS_ACLK>, <&clk IMX8DXL_EQOS_CSR_CLK>, <&clk IMX8DXL_EQOS_CLK>, 1694 clocks = <&clk IMX8DXL_EQOS_ACLK>, <&clk IMX8DXL_EQOS_CSR_CLK>, <&clk IMX8DXL_EQOS_CLK>,
1695 <&clk IMX8DXL_EQOS_PTP_CLK>; 1695 <&clk IMX8DXL_EQOS_PTP_CLK>;
1696 clock-names = "aclk", "csr", "tx_clk", "ptp"; 1696 clock-names = "aclk", "csr", "tx_clk", "ptp";
1697 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>; 1697 assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>;
1698 assigned-clock-rates = <125000000>; 1698 assigned-clock-rates = <125000000>;
1699 power-domains = <&pd_conn_enet1>; 1699 power-domains = <&pd_conn_enet1>;
1700 status = "disabled"; 1700 status = "disabled";
1701 }; 1701 };
1702 1702
1703 gpt0: gpt0@5d140000 { 1703 gpt0: gpt0@5d140000 {
1704 compatible = "fsl,imx8qxp-gpt"; 1704 compatible = "fsl,imx8qxp-gpt";
1705 reg = <0x0 0x5d140000 0x0 0x4000>; 1705 reg = <0x0 0x5d140000 0x0 0x4000>;
1706 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1706 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
1707 clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>; 1707 clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>;
1708 clock-names = "ipg", "per"; 1708 clock-names = "ipg", "per";
1709 power-domains = <&pd_lsio_gpt0>; 1709 power-domains = <&pd_lsio_gpt0>;
1710 }; 1710 };
1711 1711
1712 spdif0: spdif@59020000 { 1712 spdif0: spdif@59020000 {
1713 compatible = "fsl,imx8qm-spdif"; 1713 compatible = "fsl,imx8qm-spdif";
1714 reg = <0x0 0x59020000 0x0 0x10000>; 1714 reg = <0x0 0x59020000 0x0 0x10000>;
1715 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 1715 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */
1716 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 1716 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */
1717 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ 1717 clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */
1718 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ 1718 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */
1719 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ 1719 <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */
1720 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ 1720 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */
1721 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ 1721 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */
1722 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ 1722 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */
1723 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ 1723 <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */
1724 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ 1724 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */
1725 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ 1725 <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */
1726 <&clk IMX8QXP_CLK_DUMMY>; /* spba */ 1726 <&clk IMX8QXP_CLK_DUMMY>; /* spba */
1727 clock-names = "core", "rxtx0", 1727 clock-names = "core", "rxtx0",
1728 "rxtx1", "rxtx2", 1728 "rxtx1", "rxtx2",
1729 "rxtx3", "rxtx4", 1729 "rxtx3", "rxtx4",
1730 "rxtx5", "rxtx6", 1730 "rxtx5", "rxtx6",
1731 "rxtx7", "spba"; 1731 "rxtx7", "spba";
1732 dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; 1732 dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
1733 dma-names = "rx", "tx"; 1733 dma-names = "rx", "tx";
1734 power-domains = <&pd_spdif0>; 1734 power-domains = <&pd_spdif0>;
1735 status = "disabled"; 1735 status = "disabled";
1736 }; 1736 };
1737 1737
1738 flexspi0: flexspi@05d120000 { 1738 flexspi0: flexspi@05d120000 {
1739 #address-cells = <1>; 1739 #address-cells = <1>;
1740 #size-cells = <0>; 1740 #size-cells = <0>;
1741 compatible = "fsl,imx8qxp-flexspi"; 1741 compatible = "fsl,imx8qxp-flexspi";
1742 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; 1742 reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>;
1743 reg-names = "FlexSPI", "FlexSPI-memory"; 1743 reg-names = "FlexSPI", "FlexSPI-memory";
1744 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1744 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1745 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>; 1745 clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>;
1746 assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>; 1746 assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>;
1747 assigned-clock-rates = <29000000>; 1747 assigned-clock-rates = <29000000>;
1748 clock-names = "fspi"; 1748 clock-names = "fspi";
1749 power-domains = <&pd_lsio_flexspi0>; 1749 power-domains = <&pd_lsio_flexspi0>;
1750 status = "disabled"; 1750 status = "disabled";
1751 }; 1751 };
1752 1752
1753 dma_cap: dma_cap { 1753 dma_cap: dma_cap {
1754 compatible = "dma-capability"; 1754 compatible = "dma-capability";
1755 only-dma-mask32 = <1>; 1755 only-dma-mask32 = <1>;
1756 }; 1756 };
1757 1757
1758 hsio: hsio@5f080000 { 1758 hsio: hsio@5f080000 {
1759 compatible = "fsl,imx8qm-hsio", "syscon"; 1759 compatible = "fsl,imx8qm-hsio", "syscon";
1760 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ 1760 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
1761 }; 1761 };
1762 1762
1763 ocotp: ocotp { 1763 ocotp: ocotp {
1764 #address-cells = <1>; 1764 #address-cells = <1>;
1765 #size-cells = <1>; 1765 #size-cells = <1>;
1766 compatible = "fsl,imx8qxp-ocotp", "syscon"; 1766 compatible = "fsl,imx8qxp-ocotp", "syscon";
1767 }; 1767 };
1768 1768
1769 pcieb: pcie@0x5f010000 { 1769 pcieb: pcie@0x5f010000 {
1770 /* 1770 /*
1771 * pcieb phyx1 lane1 in default, adjust it refer to the 1771 * pcieb phyx1 lane1 in default, adjust it refer to the
1772 * exact hw design. 1772 * exact hw design.
1773 */ 1773 */
1774 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; 1774 compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
1775 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ 1775 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
1776 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ 1776 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
1777 reg-names = "dbi", "config"; 1777 reg-names = "dbi", "config";
1778 reserved-region = <&rpmsg_reserved>; 1778 reserved-region = <&rpmsg_reserved>;
1779 #address-cells = <3>; 1779 #address-cells = <3>;
1780 #size-cells = <2>; 1780 #size-cells = <2>;
1781 device_type = "pci"; 1781 device_type = "pci";
1782 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 1782 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
1783 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ 1783 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
1784 num-lanes = <1>; 1784 num-lanes = <1>;
1785 1785
1786 #interrupt-cells = <1>; 1786 #interrupt-cells = <1>;
1787 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1787 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 1788 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
1789 interrupt-names = "msi"; 1789 interrupt-names = "msi";
1790 1790
1791 /* 1791 /*
1792 * Set these clocks in default, then clocks should be 1792 * Set these clocks in default, then clocks should be
1793 * refined for exact hw design of imx8 pcie. 1793 * refined for exact hw design of imx8 pcie.
1794 */ 1794 */
1795 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, 1795 clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
1796 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, 1796 <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
1797 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, 1797 <&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
1798 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, 1798 <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>,
1799 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>; 1799 <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>,
1800 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; 1800 <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>,
1801 1801 <&clk IMX8QXP_HSIO_MISC_PER_CLK>;
1802 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
1803 "phy_per", "misc_per";
1802 interrupt-map-mask = <0 0 0 0x7>; 1804 interrupt-map-mask = <0 0 0 0x7>;
1803 interrupt-map = <0 0 0 1 &gic 0 105 4>, 1805 interrupt-map = <0 0 0 1 &gic 0 105 4>,
1804 <0 0 0 2 &gic 0 106 4>, 1806 <0 0 0 2 &gic 0 106 4>,
1805 <0 0 0 3 &gic 0 107 4>, 1807 <0 0 0 3 &gic 0 107 4>,
1806 <0 0 0 4 &gic 0 108 4>; 1808 <0 0 0 4 &gic 0 108 4>;
1807 power-domains = <&pd_pcie>; 1809 power-domains = <&pd_pcie>;
1808 fsl,max-link-speed = <3>; 1810 fsl,max-link-speed = <3>;
1809 hsio-cfg = <PCIEAX2PCIEBX1>; 1811 hsio-cfg = <PCIEAX2PCIEBX1>;
1810 hsio = <&hsio>; 1812 hsio = <&hsio>;
1811 ctrl-id = <1>; /* pcieb */ 1813 ctrl-id = <1>; /* pcieb */
1812 cpu-base-addr = <0x80000000>; 1814 cpu-base-addr = <0x80000000>;
1813 status = "disabled"; 1815 status = "disabled";
1814 }; 1816 };
1815 1817
1816 imx_ion { 1818 imx_ion {
1817 compatible = "fsl,mxc-ion"; 1819 compatible = "fsl,mxc-ion";
1818 fsl,heap-id = <0>; 1820 fsl,heap-id = <0>;
1819 }; 1821 };
1820 1822
1821 imx_rpmsg: imx_rpmsg { 1823 imx_rpmsg: imx_rpmsg {
1822 compatible = "fsl,rpmsg-bus", "simple-bus"; 1824 compatible = "fsl,rpmsg-bus", "simple-bus";
1823 #address-cells = <2>; 1825 #address-cells = <2>;
1824 #size-cells = <2>; 1826 #size-cells = <2>;
1825 ranges; 1827 ranges;
1826 1828
1827 mu_rpmsg: mu_rpmsg@5d200000 { 1829 mu_rpmsg: mu_rpmsg@5d200000 {
1828 compatible = "fsl,imx6sx-mu"; 1830 compatible = "fsl,imx6sx-mu";
1829 reg = <0x0 0x5d200000 0x0 0x10000>; 1831 reg = <0x0 0x5d200000 0x0 0x10000>;
1830 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1832 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1831 clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; 1833 clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>;
1832 clock-names = "ipg"; 1834 clock-names = "ipg";
1833 power-domains = <&pd_lsio_mu5a>; 1835 power-domains = <&pd_lsio_mu5a>;
1834 }; 1836 };
1835 1837
1836 rpmsg: rpmsg{ 1838 rpmsg: rpmsg{
1837 compatible = "fsl,imx8qxp-rpmsg"; 1839 compatible = "fsl,imx8qxp-rpmsg";
1838 status = "disabled"; 1840 status = "disabled";
1839 mub-partition = <3>; 1841 mub-partition = <3>;
1840 power-domains = <&pd_lsio_mu5a>; 1842 power-domains = <&pd_lsio_mu5a>;
1841 memory-region = <&rpmsg_dma_reserved>; 1843 memory-region = <&rpmsg_dma_reserved>;
1842 }; 1844 };
1843 }; 1845 };
1844 1846
1845 crypto: caam@0x31400000 { 1847 crypto: caam@0x31400000 {
1846 compatible = "fsl,sec-v4.0"; 1848 compatible = "fsl,sec-v4.0";
1847 reg = <0 0x31400000 0 0x400000>; 1849 reg = <0 0x31400000 0 0x400000>;
1848 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1850 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1849 #address-cells = <1>; 1851 #address-cells = <1>;
1850 #size-cells = <1>; 1852 #size-cells = <1>;
1851 ranges = <0 0 0x31400000 0x400000>; 1853 ranges = <0 0 0x31400000 0x400000>;
1852 fsl,first-jr-index = <2>; 1854 fsl,first-jr-index = <2>;
1853 fsl,sec-era = <9>; 1855 fsl,sec-era = <9>;
1854 1856
1855 sec_jr1: jr1@0x20000 { 1857 sec_jr1: jr1@0x20000 {
1856 compatible = "fsl,sec-v4.0-job-ring"; 1858 compatible = "fsl,sec-v4.0-job-ring";
1857 reg = <0x20000 0x1000>; 1859 reg = <0x20000 0x1000>;
1858 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
1859 power-domains = <&pd_caam_jr1>; 1861 power-domains = <&pd_caam_jr1>;
1860 status = "disabled"; 1862 status = "disabled";
1861 }; 1863 };
1862 1864
1863 sec_jr2: jr2@30000 { 1865 sec_jr2: jr2@30000 {
1864 compatible = "fsl,sec-v4.0-job-ring"; 1866 compatible = "fsl,sec-v4.0-job-ring";
1865 reg = <0x30000 0x1000>; 1867 reg = <0x30000 0x1000>;
1866 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 1868 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
1867 power-domains = <&pd_caam_jr2>; 1869 power-domains = <&pd_caam_jr2>;
1868 status = "okay"; 1870 status = "okay";
1869 }; 1871 };
1870 1872
1871 sec_jr3: jr3@40000 { 1873 sec_jr3: jr3@40000 {
1872 compatible = "fsl,sec-v4.0-job-ring"; 1874 compatible = "fsl,sec-v4.0-job-ring";
1873 reg = <0x40000 0x1000>; 1875 reg = <0x40000 0x1000>;
1874 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
1875 power-domains = <&pd_caam_jr3>; 1877 power-domains = <&pd_caam_jr3>;
1876 status = "okay"; 1878 status = "okay";
1877 }; 1879 };
1878 }; 1880 };
1879 1881
1880 caam_sm: caam-sm@31800000 { 1882 caam_sm: caam-sm@31800000 {
1881 compatible = "fsl,imx6q-caam-sm"; 1883 compatible = "fsl,imx6q-caam-sm";
1882 reg = <0 0x31800000 0 0x10000>; 1884 reg = <0 0x31800000 0 0x10000>;
1883 }; 1885 };
1884 1886
1885 sc_pwrkey: sc-powerkey { 1887 sc_pwrkey: sc-powerkey {
1886 compatible = "fsl,imx8-pwrkey"; 1888 compatible = "fsl,imx8-pwrkey";
1887 linux,keycode = <KEY_POWER>; 1889 linux,keycode = <KEY_POWER>;
1888 wakeup-source; 1890 wakeup-source;
1889 }; 1891 };
1890 1892
1891 wdog: wdog { 1893 wdog: wdog {
1892 compatible = "fsl,imx8-wdt"; 1894 compatible = "fsl,imx8-wdt";
1893 }; 1895 };
1894 }; 1896 };
1895 1897
1896 &A35_0 { 1898 &A35_0 {
1897 operating-points = < 1899 operating-points = <
1898 /* kHz uV*/ 1900 /* kHz uV*/
1899 /* voltage is maintained by SCFW, so no need here */ 1901 /* voltage is maintained by SCFW, so no need here */
1900 1200000 0 1902 1200000 0
1901 900000 0 1903 900000 0
1902 >; 1904 >;
1903 clocks = <&clk IMX8QXP_A35_DIV>; 1905 clocks = <&clk IMX8QXP_A35_DIV>;
1904 clock-latency = <61036>; 1906 clock-latency = <61036>;
1905 #cooling-cells = <2>; 1907 #cooling-cells = <2>;
1906 }; 1908 };
1907 1909
arch/arm/dts/fsl-imx8qm-device.dtsi
Diff comments   View file @ 11ea97f
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 imx8qm-pm { 6 imx8qm-pm {
7 compatible = "simple-bus"; 7 compatible = "simple-bus";
8 #address-cells = <1>; 8 #address-cells = <1>;
9 #size-cells = <0>; 9 #size-cells = <0>;
10 10
11 pd_dc0: PD_DC_0 { 11 pd_dc0: PD_DC_0 {
12 compatible = "nxp,imx8-pd"; 12 compatible = "nxp,imx8-pd";
13 reg = <SC_R_DC_0>; 13 reg = <SC_R_DC_0>;
14 #power-domain-cells = <0>; 14 #power-domain-cells = <0>;
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <0>; 16 #size-cells = <0>;
17 17
18 pd_dc0_pll0: PD_DC_0_PLL_0{ 18 pd_dc0_pll0: PD_DC_0_PLL_0{
19 reg = <SC_R_DC_0_PLL_0>; 19 reg = <SC_R_DC_0_PLL_0>;
20 #power-domain-cells = <0>; 20 #power-domain-cells = <0>;
21 power-domains =<&pd_dc0>; 21 power-domains =<&pd_dc0>;
22 #address-cells = <1>; 22 #address-cells = <1>;
23 #size-cells = <0>; 23 #size-cells = <0>;
24 24
25 pd_dc0_pll1: PD_DC_0_PLL_1{ 25 pd_dc0_pll1: PD_DC_0_PLL_1{
26 reg = <SC_R_DC_0_PLL_1>; 26 reg = <SC_R_DC_0_PLL_1>;
27 #power-domain-cells = <0>; 27 #power-domain-cells = <0>;
28 power-domains =<&pd_dc0_pll0>; 28 power-domains =<&pd_dc0_pll0>;
29 }; 29 };
30 }; 30 };
31 31
32 pd_mipi0: PD_MIPI_0_DSI { 32 pd_mipi0: PD_MIPI_0_DSI {
33 reg = <SC_R_MIPI_0>; 33 reg = <SC_R_MIPI_0>;
34 #power-domain-cells = <0>; 34 #power-domain-cells = <0>;
35 power-domains =<&pd_dc0>; 35 power-domains =<&pd_dc0>;
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 38
39 pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 { 39 pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 {
40 reg = <SC_R_MIPI_0_I2C_0>; 40 reg = <SC_R_MIPI_0_I2C_0>;
41 #power-domain-cells = <0>; 41 #power-domain-cells = <0>;
42 power-domains =<&pd_mipi0>; 42 power-domains =<&pd_mipi0>;
43 }; 43 };
44 44
45 pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 { 45 pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 {
46 reg = <SC_R_MIPI_0_I2C_1>; 46 reg = <SC_R_MIPI_0_I2C_1>;
47 #power-domain-cells = <0>; 47 #power-domain-cells = <0>;
48 power-domains =<&pd_mipi0>; 48 power-domains =<&pd_mipi0>;
49 }; 49 };
50 50
51 pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 { 51 pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 {
52 reg = <SC_R_MIPI_0_PWM_0>; 52 reg = <SC_R_MIPI_0_PWM_0>;
53 #power-domain-cells = <0>; 53 #power-domain-cells = <0>;
54 power-domains =<&pd_mipi0>; 54 power-domains =<&pd_mipi0>;
55 }; 55 };
56 }; 56 };
57 57
58 pd_lvds0: PD_LVDS0 { 58 pd_lvds0: PD_LVDS0 {
59 reg = <SC_R_LVDS_0>; 59 reg = <SC_R_LVDS_0>;
60 #power-domain-cells = <0>; 60 #power-domain-cells = <0>;
61 power-domains =<&pd_dc0>; 61 power-domains =<&pd_dc0>;
62 #address-cells = <1>; 62 #address-cells = <1>;
63 #size-cells = <0>; 63 #size-cells = <0>;
64 64
65 pd_lvds0_i2c0: PD_LVDS0_I2C0 { 65 pd_lvds0_i2c0: PD_LVDS0_I2C0 {
66 reg = <SC_R_LVDS_0_I2C_0>; 66 reg = <SC_R_LVDS_0_I2C_0>;
67 #power-domain-cells = <0>; 67 #power-domain-cells = <0>;
68 power-domains =<&pd_lvds0>; 68 power-domains =<&pd_lvds0>;
69 }; 69 };
70 70
71 pd_lvds0_pwm: PD_LVDS0_PWM { 71 pd_lvds0_pwm: PD_LVDS0_PWM {
72 reg = <SC_R_LVDS_0_PWM_0>; 72 reg = <SC_R_LVDS_0_PWM_0>;
73 #power-domain-cells = <0>; 73 #power-domain-cells = <0>;
74 power-domains =<&pd_lvds0>; 74 power-domains =<&pd_lvds0>;
75 }; 75 };
76 }; 76 };
77 77
78 pd_hdmi: PD_HDMI { 78 pd_hdmi: PD_HDMI {
79 reg = <SC_R_HDMI>; 79 reg = <SC_R_HDMI>;
80 #power-domain-cells = <0>; 80 #power-domain-cells = <0>;
81 power-domains =<&pd_dc0>; 81 power-domains =<&pd_dc0>;
82 #address-cells = <1>; 82 #address-cells = <1>;
83 #size-cells = <0>; 83 #size-cells = <0>;
84 84
85 pd_hdmi_pll0: PD_HDMI_PLL_0{ 85 pd_hdmi_pll0: PD_HDMI_PLL_0{
86 reg = <SC_R_HDMI_PLL_0>; 86 reg = <SC_R_HDMI_PLL_0>;
87 #power-domain-cells = <0>; 87 #power-domain-cells = <0>;
88 power-domains =<&pd_hdmi>; 88 power-domains =<&pd_hdmi>;
89 #address-cells = <1>; 89 #address-cells = <1>;
90 #size-cells = <0>; 90 #size-cells = <0>;
91 91
92 pd_hdmi_pll1: PD_HDMI_PLL_1{ 92 pd_hdmi_pll1: PD_HDMI_PLL_1{
93 reg = <SC_R_HDMI_PLL_1>; 93 reg = <SC_R_HDMI_PLL_1>;
94 #power-domain-cells = <0>; 94 #power-domain-cells = <0>;
95 power-domains =<&pd_hdmi_pll0>; 95 power-domains =<&pd_hdmi_pll0>;
96 #address-cells = <1>; 96 #address-cells = <1>;
97 #size-cells = <0>; 97 #size-cells = <0>;
98 98
99 pd_hdmi_i2c0: PD_HDMI_I2C_0 { 99 pd_hdmi_i2c0: PD_HDMI_I2C_0 {
100 reg = <SC_R_HDMI_I2C_0>; 100 reg = <SC_R_HDMI_I2C_0>;
101 #power-domain-cells = <0>; 101 #power-domain-cells = <0>;
102 power-domains =<&pd_hdmi_pll1>; 102 power-domains =<&pd_hdmi_pll1>;
103 }; 103 };
104 104
105 pd_hdmi_i2s: PD_HDMI_I2S { 105 pd_hdmi_i2s: PD_HDMI_I2S {
106 reg = <SC_R_HDMI_I2S>; 106 reg = <SC_R_HDMI_I2S>;
107 #power-domain-cells = <0>; 107 #power-domain-cells = <0>;
108 power-domains =<&pd_hdmi_pll1>; 108 power-domains =<&pd_hdmi_pll1>;
109 }; 109 };
110 }; 110 };
111 }; 111 };
112 112
113 }; 113 };
114 114
115 }; 115 };
116 116
117 pd_dc1: PD_DC_1 { 117 pd_dc1: PD_DC_1 {
118 compatible = "nxp,imx8-pd"; 118 compatible = "nxp,imx8-pd";
119 reg = <SC_R_DC_1>; 119 reg = <SC_R_DC_1>;
120 #power-domain-cells = <0>; 120 #power-domain-cells = <0>;
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <0>; 122 #size-cells = <0>;
123 123
124 pd_dc1_pll0: PD_DC_1_PLL_0{ 124 pd_dc1_pll0: PD_DC_1_PLL_0{
125 reg = <SC_R_DC_1_PLL_0>; 125 reg = <SC_R_DC_1_PLL_0>;
126 #power-domain-cells = <0>; 126 #power-domain-cells = <0>;
127 power-domains =<&pd_dc1>; 127 power-domains =<&pd_dc1>;
128 #address-cells = <1>; 128 #address-cells = <1>;
129 #size-cells = <0>; 129 #size-cells = <0>;
130 130
131 pd_dc1_pll1: PD_DC_1_PLL_1{ 131 pd_dc1_pll1: PD_DC_1_PLL_1{
132 reg = <SC_R_DC_1_PLL_1>; 132 reg = <SC_R_DC_1_PLL_1>;
133 #power-domain-cells = <0>; 133 #power-domain-cells = <0>;
134 power-domains =<&pd_dc1_pll0>; 134 power-domains =<&pd_dc1_pll0>;
135 }; 135 };
136 }; 136 };
137 137
138 pd_mipi1: PD_MIPI_1_DSI { 138 pd_mipi1: PD_MIPI_1_DSI {
139 reg = <SC_R_MIPI_1>; 139 reg = <SC_R_MIPI_1>;
140 #power-domain-cells = <0>; 140 #power-domain-cells = <0>;
141 power-domains =<&pd_dc1>; 141 power-domains =<&pd_dc1>;
142 #address-cells = <1>; 142 #address-cells = <1>;
143 #size-cells = <0>; 143 #size-cells = <0>;
144 144
145 pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 { 145 pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 {
146 reg = <SC_R_MIPI_1_I2C_0>; 146 reg = <SC_R_MIPI_1_I2C_0>;
147 #power-domain-cells = <0>; 147 #power-domain-cells = <0>;
148 power-domains =<&pd_mipi1>; 148 power-domains =<&pd_mipi1>;
149 }; 149 };
150 150
151 pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 { 151 pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 {
152 reg = <SC_R_MIPI_1_I2C_1>; 152 reg = <SC_R_MIPI_1_I2C_1>;
153 #power-domain-cells = <0>; 153 #power-domain-cells = <0>;
154 power-domains =<&pd_mipi1>; 154 power-domains =<&pd_mipi1>;
155 }; 155 };
156 156
157 pd_mipi1_pwm: PD_MIPI_1_DSI_PWM { 157 pd_mipi1_pwm: PD_MIPI_1_DSI_PWM {
158 reg = <SC_R_MIPI_1_PWM_0>; 158 reg = <SC_R_MIPI_1_PWM_0>;
159 #power-domain-cells = <0>; 159 #power-domain-cells = <0>;
160 power-domains =<&pd_mipi1>; 160 power-domains =<&pd_mipi1>;
161 }; 161 };
162 }; 162 };
163 163
164 pd_lvds1: PD_LVDS1 { 164 pd_lvds1: PD_LVDS1 {
165 reg = <SC_R_LVDS_1>; 165 reg = <SC_R_LVDS_1>;
166 #power-domain-cells = <0>; 166 #power-domain-cells = <0>;
167 power-domains =<&pd_dc1>; 167 power-domains =<&pd_dc1>;
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 170
171 pd_lvds1_i2c0: PD_LVDS1_I2C0 { 171 pd_lvds1_i2c0: PD_LVDS1_I2C0 {
172 reg = <SC_R_LVDS_1_I2C_0>; 172 reg = <SC_R_LVDS_1_I2C_0>;
173 #power-domain-cells = <0>; 173 #power-domain-cells = <0>;
174 power-domains =<&pd_lvds1>; 174 power-domains =<&pd_lvds1>;
175 }; 175 };
176 176
177 pd_lvds1_pwm: PD_LVDS1_PWM { 177 pd_lvds1_pwm: PD_LVDS1_PWM {
178 reg = <SC_R_LVDS_1_PWM_0>; 178 reg = <SC_R_LVDS_1_PWM_0>;
179 #power-domain-cells = <0>; 179 #power-domain-cells = <0>;
180 power-domains =<&pd_lvds1>; 180 power-domains =<&pd_lvds1>;
181 }; 181 };
182 }; 182 };
183 }; 183 };
184 184
185 pd_lsio: PD_LSIO { 185 pd_lsio: PD_LSIO {
186 compatible = "nxp,imx8-pd"; 186 compatible = "nxp,imx8-pd";
187 reg = <SC_R_NONE>; 187 reg = <SC_R_NONE>;
188 #power-domain-cells = <0>; 188 #power-domain-cells = <0>;
189 #address-cells = <1>; 189 #address-cells = <1>;
190 #size-cells = <0>; 190 #size-cells = <0>;
191 191
192 pd_lsio_gpio0: PD_LSIO_GPIO_0 { 192 pd_lsio_gpio0: PD_LSIO_GPIO_0 {
193 reg = <SC_R_GPIO_0>; 193 reg = <SC_R_GPIO_0>;
194 #power-domain-cells = <0>; 194 #power-domain-cells = <0>;
195 power-domains = <&pd_lsio>; 195 power-domains = <&pd_lsio>;
196 }; 196 };
197 pd_lsio_gpio1: PD_LSIO_GPIO_1 { 197 pd_lsio_gpio1: PD_LSIO_GPIO_1 {
198 reg = <SC_R_GPIO_1>; 198 reg = <SC_R_GPIO_1>;
199 #power-domain-cells = <0>; 199 #power-domain-cells = <0>;
200 power-domains = <&pd_lsio>; 200 power-domains = <&pd_lsio>;
201 }; 201 };
202 pd_lsio_gpio2: PD_LSIO_GPIO_2 { 202 pd_lsio_gpio2: PD_LSIO_GPIO_2 {
203 reg = <SC_R_GPIO_2>; 203 reg = <SC_R_GPIO_2>;
204 #power-domain-cells = <0>; 204 #power-domain-cells = <0>;
205 power-domains = <&pd_lsio>; 205 power-domains = <&pd_lsio>;
206 }; 206 };
207 pd_lsio_gpio3: PD_LSIO_GPIO_3 { 207 pd_lsio_gpio3: PD_LSIO_GPIO_3 {
208 reg = <SC_R_GPIO_3>; 208 reg = <SC_R_GPIO_3>;
209 #power-domain-cells = <0>; 209 #power-domain-cells = <0>;
210 power-domains = <&pd_lsio>; 210 power-domains = <&pd_lsio>;
211 }; 211 };
212 pd_lsio_gpio4: PD_LSIO_GPIO_4 { 212 pd_lsio_gpio4: PD_LSIO_GPIO_4 {
213 reg = <SC_R_GPIO_4>; 213 reg = <SC_R_GPIO_4>;
214 #power-domain-cells = <0>; 214 #power-domain-cells = <0>;
215 power-domains = <&pd_lsio>; 215 power-domains = <&pd_lsio>;
216 }; 216 };
217 pd_lsio_gpio5: PD_LSIO_GPIO_5{ 217 pd_lsio_gpio5: PD_LSIO_GPIO_5{
218 reg = <SC_R_GPIO_5>; 218 reg = <SC_R_GPIO_5>;
219 #power-domain-cells = <0>; 219 #power-domain-cells = <0>;
220 power-domains = <&pd_lsio>; 220 power-domains = <&pd_lsio>;
221 }; 221 };
222 pd_lsio_gpio6:PD_LSIO_GPIO_6 { 222 pd_lsio_gpio6:PD_LSIO_GPIO_6 {
223 reg = <SC_R_GPIO_6>; 223 reg = <SC_R_GPIO_6>;
224 #power-domain-cells = <0>; 224 #power-domain-cells = <0>;
225 power-domains = <&pd_lsio>; 225 power-domains = <&pd_lsio>;
226 }; 226 };
227 pd_lsio_gpio7: PD_LSIO_GPIO_7 { 227 pd_lsio_gpio7: PD_LSIO_GPIO_7 {
228 reg = <SC_R_GPIO_7>; 228 reg = <SC_R_GPIO_7>;
229 #power-domain-cells = <0>; 229 #power-domain-cells = <0>;
230 power-domains = <&pd_lsio>; 230 power-domains = <&pd_lsio>;
231 }; 231 };
232 pd_lsio_flexspi0: PD_LSIO_FSPI_0 { 232 pd_lsio_flexspi0: PD_LSIO_FSPI_0 {
233 reg = <SC_R_FSPI_0>; 233 reg = <SC_R_FSPI_0>;
234 #power-domain-cells = <0>; 234 #power-domain-cells = <0>;
235 power-domains = <&pd_lsio>; 235 power-domains = <&pd_lsio>;
236 }; 236 };
237 pd_lsio_flexspi1: PD_LSIO_FSPI_1{ 237 pd_lsio_flexspi1: PD_LSIO_FSPI_1{
238 reg = <SC_R_FSPI_1>; 238 reg = <SC_R_FSPI_1>;
239 #power-domain-cells = <0>; 239 #power-domain-cells = <0>;
240 power-domains = <&pd_lsio>; 240 power-domains = <&pd_lsio>;
241 }; 241 };
242 pd_lsio_mu5a: PD_LSIO_MU5A { 242 pd_lsio_mu5a: PD_LSIO_MU5A {
243 reg = <SC_R_MU_5A>; 243 reg = <SC_R_MU_5A>;
244 #power-domain-cells = <0>; 244 #power-domain-cells = <0>;
245 power-domains = <&pd_lsio>; 245 power-domains = <&pd_lsio>;
246 }; 246 };
247 pd_lsio_mu6a: PD_LSIO_MU6A { 247 pd_lsio_mu6a: PD_LSIO_MU6A {
248 reg = <SC_R_MU_6A>; 248 reg = <SC_R_MU_6A>;
249 #power-domain-cells = <0>; 249 #power-domain-cells = <0>;
250 power-domains = <&pd_lsio>; 250 power-domains = <&pd_lsio>;
251 }; 251 };
252 pd_lsio_mu8a: PD_LSIO_MU8A { 252 pd_lsio_mu8a: PD_LSIO_MU8A {
253 reg = <SC_R_MU_8A>; 253 reg = <SC_R_MU_8A>;
254 #power-domain-cells = <0>; 254 #power-domain-cells = <0>;
255 power-domains = <&pd_lsio>; 255 power-domains = <&pd_lsio>;
256 }; 256 };
257 pd_lsio_mu9a: PD_LSIO_MU9A { 257 pd_lsio_mu9a: PD_LSIO_MU9A {
258 reg = <SC_R_MU_9A>; 258 reg = <SC_R_MU_9A>;
259 #power-domain-cells = <0>; 259 #power-domain-cells = <0>;
260 power-domains = <&pd_lsio>; 260 power-domains = <&pd_lsio>;
261 }; 261 };
262 }; 262 };
263 263
264 pd_conn: PD_CONN { 264 pd_conn: PD_CONN {
265 compatible = "nxp,imx8-pd"; 265 compatible = "nxp,imx8-pd";
266 reg = <SC_R_NONE>; 266 reg = <SC_R_NONE>;
267 #power-domain-cells = <0>; 267 #power-domain-cells = <0>;
268 #address-cells = <1>; 268 #address-cells = <1>;
269 #size-cells = <0>; 269 #size-cells = <0>;
270 270
271 pd_conn_usbotg0: PD_CONN_USB_0 { 271 pd_conn_usbotg0: PD_CONN_USB_0 {
272 reg = <SC_R_USB_0>; 272 reg = <SC_R_USB_0>;
273 #power-domain-cells = <0>; 273 #power-domain-cells = <0>;
274 power-domains = <&pd_conn>; 274 power-domains = <&pd_conn>;
275 wakeup-irq = <267>; 275 wakeup-irq = <267>;
276 }; 276 };
277 277
278 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { 278 pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY {
279 reg = <SC_R_USB_0_PHY>; 279 reg = <SC_R_USB_0_PHY>;
280 #power-domain-cells = <0>; 280 #power-domain-cells = <0>;
281 power-domains = <&pd_conn>; 281 power-domains = <&pd_conn>;
282 wakeup-irq = <267>; 282 wakeup-irq = <267>;
283 }; 283 };
284 284
285 pd_conn_usbh1: PD_CONN_USB_1 { 285 pd_conn_usbh1: PD_CONN_USB_1 {
286 reg = <SC_R_USB_1>; 286 reg = <SC_R_USB_1>;
287 #power-domain-cells = <0>; 287 #power-domain-cells = <0>;
288 power-domains = <&pd_conn>; 288 power-domains = <&pd_conn>;
289 wakeup-irq = <268>; 289 wakeup-irq = <268>;
290 }; 290 };
291 291
292 pd_conn_usb2: PD_CONN_USB_2 { 292 pd_conn_usb2: PD_CONN_USB_2 {
293 reg = <SC_R_USB_2>; 293 reg = <SC_R_USB_2>;
294 #power-domain-cells = <0>; 294 #power-domain-cells = <0>;
295 #address-cells = <1>; 295 #address-cells = <1>;
296 #size-cells = <0>; 296 #size-cells = <0>;
297 power-domains = <&pd_conn>; 297 power-domains = <&pd_conn>;
298 wakeup-irq = <271>; 298 wakeup-irq = <271>;
299 299
300 pd_conn_usb2_phy: PD_CONN_USB_2_PHY { 300 pd_conn_usb2_phy: PD_CONN_USB_2_PHY {
301 reg = <SC_R_USB_2_PHY>; 301 reg = <SC_R_USB_2_PHY>;
302 #power-domain-cells = <0>; 302 #power-domain-cells = <0>;
303 power-domains = <&pd_conn_usb2>; 303 power-domains = <&pd_conn_usb2>;
304 wakeup-irq = <271>; 304 wakeup-irq = <271>;
305 }; 305 };
306 }; 306 };
307 pd_conn_sdch0: PD_CONN_SDHC_0 { 307 pd_conn_sdch0: PD_CONN_SDHC_0 {
308 reg = <SC_R_SDHC_0>; 308 reg = <SC_R_SDHC_0>;
309 #power-domain-cells = <0>; 309 #power-domain-cells = <0>;
310 power-domains = <&pd_conn>; 310 power-domains = <&pd_conn>;
311 }; 311 };
312 pd_conn_sdch1: PD_CONN_SDHC_1 { 312 pd_conn_sdch1: PD_CONN_SDHC_1 {
313 reg = <SC_R_SDHC_1>; 313 reg = <SC_R_SDHC_1>;
314 #power-domain-cells = <0>; 314 #power-domain-cells = <0>;
315 power-domains = <&pd_conn>; 315 power-domains = <&pd_conn>;
316 }; 316 };
317 pd_conn_sdch2: PD_CONN_SDHC_2 { 317 pd_conn_sdch2: PD_CONN_SDHC_2 {
318 reg = <SC_R_SDHC_2>; 318 reg = <SC_R_SDHC_2>;
319 #power-domain-cells = <0>; 319 #power-domain-cells = <0>;
320 power-domains = <&pd_conn>; 320 power-domains = <&pd_conn>;
321 }; 321 };
322 pd_conn_enet0: PD_CONN_ENET_0 { 322 pd_conn_enet0: PD_CONN_ENET_0 {
323 reg = <SC_R_ENET_0>; 323 reg = <SC_R_ENET_0>;
324 #power-domain-cells = <0>; 324 #power-domain-cells = <0>;
325 power-domains = <&pd_conn>; 325 power-domains = <&pd_conn>;
326 wakeup-irq = <258>; 326 wakeup-irq = <258>;
327 }; 327 };
328 pd_conn_enet1: PD_CONN_ENET_1 { 328 pd_conn_enet1: PD_CONN_ENET_1 {
329 reg = <SC_R_ENET_1>; 329 reg = <SC_R_ENET_1>;
330 #power-domain-cells = <0>; 330 #power-domain-cells = <0>;
331 power-domains = <&pd_conn>; 331 power-domains = <&pd_conn>;
332 fsl,wakeup_irq = <262>; 332 fsl,wakeup_irq = <262>;
333 }; 333 };
334 pd_conn_nand: PD_CONN_NAND { 334 pd_conn_nand: PD_CONN_NAND {
335 reg = <SC_R_NAND>; 335 reg = <SC_R_NAND>;
336 #power-domain-cells = <0>; 336 #power-domain-cells = <0>;
337 power-domains = <&pd_conn>; 337 power-domains = <&pd_conn>;
338 }; 338 };
339 pd_conn_mlb0: PD_CONN_MLB_0 { 339 pd_conn_mlb0: PD_CONN_MLB_0 {
340 reg = <SC_R_MLB_0>; 340 reg = <SC_R_MLB_0>;
341 #power-domain-cells = <0>; 341 #power-domain-cells = <0>;
342 power-domains = <&pd_conn>; 342 power-domains = <&pd_conn>;
343 }; 343 };
344 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { 344 pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 {
345 reg = <SC_R_DMA_4_CH0>; 345 reg = <SC_R_DMA_4_CH0>;
346 #power-domain-cells = <0>; 346 #power-domain-cells = <0>;
347 power-domains =<&pd_conn>; 347 power-domains =<&pd_conn>;
348 }; 348 };
349 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { 349 pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 {
350 reg = <SC_R_DMA_4_CH1>; 350 reg = <SC_R_DMA_4_CH1>;
351 #power-domain-cells = <0>; 351 #power-domain-cells = <0>;
352 power-domains =<&pd_conn>; 352 power-domains =<&pd_conn>;
353 }; 353 };
354 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { 354 pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 {
355 reg = <SC_R_DMA_4_CH2>; 355 reg = <SC_R_DMA_4_CH2>;
356 #power-domain-cells = <0>; 356 #power-domain-cells = <0>;
357 power-domains =<&pd_conn>; 357 power-domains =<&pd_conn>;
358 }; 358 };
359 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { 359 pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 {
360 reg = <SC_R_DMA_4_CH3>; 360 reg = <SC_R_DMA_4_CH3>;
361 #power-domain-cells = <0>; 361 #power-domain-cells = <0>;
362 power-domains =<&pd_conn>; 362 power-domains =<&pd_conn>;
363 }; 363 };
364 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { 364 pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 {
365 reg = <SC_R_DMA_4_CH4>; 365 reg = <SC_R_DMA_4_CH4>;
366 #power-domain-cells = <0>; 366 #power-domain-cells = <0>;
367 power-domains =<&pd_conn>; 367 power-domains =<&pd_conn>;
368 }; 368 };
369 }; 369 };
370 370
371 pd_hsio: PD_HSIO { 371 pd_hsio: PD_HSIO {
372 compatible = "nxp,imx8-pd"; 372 compatible = "nxp,imx8-pd";
373 reg = <SC_R_NONE>; 373 reg = <SC_R_NONE>;
374 #power-domain-cells = <0>; 374 #power-domain-cells = <0>;
375 #address-cells = <1>; 375 #address-cells = <1>;
376 #size-cells = <0>; 376 #size-cells = <0>;
377 377
378 pd_hsio_gpio: PD_HSIO_GPIO { 378 pd_hsio_gpio: PD_HSIO_GPIO {
379 reg = <SC_R_HSIO_GPIO>; 379 reg = <SC_R_HSIO_GPIO>;
380 #power-domain-cells = <0>; 380 #power-domain-cells = <0>;
381 power-domains =<&pd_hsio>; 381 power-domains =<&pd_hsio>;
382 #address-cells = <1>; 382 #address-cells = <1>;
383 #size-cells = <0>; 383 #size-cells = <0>;
384 384
385 pd_serdes0: PD_HSIO_SERDES_0 { 385 pd_serdes0: PD_HSIO_SERDES_0 {
386 reg = <SC_R_SERDES_0>; 386 reg = <SC_R_SERDES_0>;
387 #power-domain-cells = <0>; 387 #power-domain-cells = <0>;
388 power-domains =<&pd_hsio_gpio>; 388 power-domains =<&pd_hsio_gpio>;
389 #address-cells = <1>; 389 #address-cells = <1>;
390 #size-cells = <0>; 390 #size-cells = <0>;
391 391
392 pd_pcie0: PD_HSIO_PCIE_A { 392 pd_pcie0: PD_HSIO_PCIE_A {
393 reg = <SC_R_PCIE_A>; 393 reg = <SC_R_PCIE_A>;
394 #power-domain-cells = <0>; 394 #power-domain-cells = <0>;
395 power-domains =<&pd_serdes0>; 395 power-domains =<&pd_serdes0>;
396 #address-cells = <1>; 396 #address-cells = <1>;
397 #size-cells = <0>; 397 #size-cells = <0>;
398 398
399 pd_pcie1: PD_HSIO_PCIE_B { 399 pd_pcie1: PD_HSIO_PCIE_B {
400 reg = <SC_R_PCIE_B>; 400 reg = <SC_R_PCIE_B>;
401 #power-domain-cells = <0>; 401 #power-domain-cells = <0>;
402 power-domains =<&pd_pcie0>; 402 power-domains =<&pd_pcie0>;
403 #address-cells = <1>; 403 #address-cells = <1>;
404 #size-cells = <0>; 404 #size-cells = <0>;
405 405
406 pd_serdes1: PD_HSIO_SERDES_1 { 406 pd_serdes1: PD_HSIO_SERDES_1 {
407 reg = <SC_R_SERDES_1>; 407 reg = <SC_R_SERDES_1>;
408 #power-domain-cells = <0>; 408 #power-domain-cells = <0>;
409 power-domains =<&pd_pcie1>; 409 power-domains =<&pd_pcie1>;
410 #address-cells = <1>; 410 #address-cells = <1>;
411 #size-cells = <0>; 411 #size-cells = <0>;
412 412
413 pd_sata0: PD_HSIO_SATA_0 { 413 pd_sata0: PD_HSIO_SATA_0 {
414 reg = <SC_R_SATA_0>; 414 reg = <SC_R_SATA_0>;
415 #power-domain-cells = <0>; 415 #power-domain-cells = <0>;
416 power-domains =<&pd_serdes1>; 416 power-domains =<&pd_serdes1>;
417 }; 417 };
418 }; 418 };
419 }; 419 };
420 }; 420 };
421 }; 421 };
422 }; 422 };
423 }; 423 };
424 424
425 pd_dma: PD_DMA { 425 pd_dma: PD_DMA {
426 compatible = "nxp,imx8-pd"; 426 compatible = "nxp,imx8-pd";
427 reg = <SC_R_NONE>; 427 reg = <SC_R_NONE>;
428 #power-domain-cells = <0>; 428 #power-domain-cells = <0>;
429 #address-cells = <1>; 429 #address-cells = <1>;
430 #size-cells = <0>; 430 #size-cells = <0>;
431 431
432 pd_dma_lpi2c0: PD_DMA_I2C_0 { 432 pd_dma_lpi2c0: PD_DMA_I2C_0 {
433 reg = <SC_R_I2C_0>; 433 reg = <SC_R_I2C_0>;
434 #power-domain-cells = <0>; 434 #power-domain-cells = <0>;
435 power-domains = <&pd_dma>; 435 power-domains = <&pd_dma>;
436 }; 436 };
437 pd_dma_lpi2c1: PD_DMA_I2C_1 { 437 pd_dma_lpi2c1: PD_DMA_I2C_1 {
438 reg = <SC_R_I2C_1>; 438 reg = <SC_R_I2C_1>;
439 #power-domain-cells = <0>; 439 #power-domain-cells = <0>;
440 power-domains = <&pd_dma>; 440 power-domains = <&pd_dma>;
441 }; 441 };
442 pd_dma_lpi2c2:PD_DMA_I2C_2 { 442 pd_dma_lpi2c2:PD_DMA_I2C_2 {
443 reg = <SC_R_I2C_2>; 443 reg = <SC_R_I2C_2>;
444 #power-domain-cells = <0>; 444 #power-domain-cells = <0>;
445 power-domains = <&pd_dma>; 445 power-domains = <&pd_dma>;
446 }; 446 };
447 pd_dma_lpi2c3: PD_DMA_I2C_3 { 447 pd_dma_lpi2c3: PD_DMA_I2C_3 {
448 reg = <SC_R_I2C_3>; 448 reg = <SC_R_I2C_3>;
449 #power-domain-cells = <0>; 449 #power-domain-cells = <0>;
450 power-domains = <&pd_dma>; 450 power-domains = <&pd_dma>;
451 }; 451 };
452 pd_dma_lpi2c4: PD_DMA_I2C_4 { 452 pd_dma_lpi2c4: PD_DMA_I2C_4 {
453 reg = <SC_R_I2C_4>; 453 reg = <SC_R_I2C_4>;
454 #power-domain-cells = <0>; 454 #power-domain-cells = <0>;
455 power-domains = <&pd_dma>; 455 power-domains = <&pd_dma>;
456 }; 456 };
457 pd_dma_lpuart0: PD_DMA_UART0 { 457 pd_dma_lpuart0: PD_DMA_UART0 {
458 reg = <SC_R_UART_0>; 458 reg = <SC_R_UART_0>;
459 #power-domain-cells = <0>; 459 #power-domain-cells = <0>;
460 power-domains = <&pd_dma>; 460 power-domains = <&pd_dma>;
461 wakeup-irq = <345>; 461 wakeup-irq = <345>;
462 }; 462 };
463 pd_dma_lpuart1: PD_DMA_UART1 { 463 pd_dma_lpuart1: PD_DMA_UART1 {
464 reg = <SC_R_UART_1>; 464 reg = <SC_R_UART_1>;
465 #power-domain-cells = <0>; 465 #power-domain-cells = <0>;
466 power-domains = <&pd_dma>; 466 power-domains = <&pd_dma>;
467 #address-cells = <1>; 467 #address-cells = <1>;
468 #size-cells = <0>; 468 #size-cells = <0>;
469 wakeup-irq = <346>; 469 wakeup-irq = <346>;
470 470
471 pd_dma0_chan14: PD_UART1_RX { 471 pd_dma0_chan14: PD_UART1_RX {
472 reg = <SC_R_DMA_0_CH14>; 472 reg = <SC_R_DMA_0_CH14>;
473 power-domains =<&pd_dma_lpuart1>; 473 power-domains =<&pd_dma_lpuart1>;
474 #power-domain-cells = <0>; 474 #power-domain-cells = <0>;
475 #address-cells = <1>; 475 #address-cells = <1>;
476 #size-cells = <0>; 476 #size-cells = <0>;
477 477
478 pd_dma0_chan15: PD_UART1_TX { 478 pd_dma0_chan15: PD_UART1_TX {
479 reg = <SC_R_DMA_0_CH15>; 479 reg = <SC_R_DMA_0_CH15>;
480 power-domains =<&pd_dma0_chan14>; 480 power-domains =<&pd_dma0_chan14>;
481 #power-domain-cells = <0>; 481 #power-domain-cells = <0>;
482 #address-cells = <1>; 482 #address-cells = <1>;
483 #size-cells = <0>; 483 #size-cells = <0>;
484 }; 484 };
485 }; 485 };
486 }; 486 };
487 pd_dma_lpuart2: PD_DMA_UART2 { 487 pd_dma_lpuart2: PD_DMA_UART2 {
488 reg = <SC_R_UART_2>; 488 reg = <SC_R_UART_2>;
489 #power-domain-cells = <0>; 489 #power-domain-cells = <0>;
490 power-domains = <&pd_dma>; 490 power-domains = <&pd_dma>;
491 #address-cells = <1>; 491 #address-cells = <1>;
492 #size-cells = <0>; 492 #size-cells = <0>;
493 wakeup-irq = <347>; 493 wakeup-irq = <347>;
494 494
495 pd_dma0_chan16: PD_UART2_RX { 495 pd_dma0_chan16: PD_UART2_RX {
496 reg = <SC_R_DMA_0_CH16>; 496 reg = <SC_R_DMA_0_CH16>;
497 power-domains =<&pd_dma_lpuart2>; 497 power-domains =<&pd_dma_lpuart2>;
498 #power-domain-cells = <0>; 498 #power-domain-cells = <0>;
499 #address-cells = <1>; 499 #address-cells = <1>;
500 #size-cells = <0>; 500 #size-cells = <0>;
501 501
502 pd_dma0_chan17: PD_UART2_TX { 502 pd_dma0_chan17: PD_UART2_TX {
503 reg = <SC_R_DMA_0_CH17>; 503 reg = <SC_R_DMA_0_CH17>;
504 power-domains =<&pd_dma0_chan16>; 504 power-domains =<&pd_dma0_chan16>;
505 #power-domain-cells = <0>; 505 #power-domain-cells = <0>;
506 #address-cells = <1>; 506 #address-cells = <1>;
507 #size-cells = <0>; 507 #size-cells = <0>;
508 }; 508 };
509 }; 509 };
510 }; 510 };
511 pd_dma_lpuart3: PD_DMA_UART3 { 511 pd_dma_lpuart3: PD_DMA_UART3 {
512 reg = <SC_R_UART_3>; 512 reg = <SC_R_UART_3>;
513 #power-domain-cells = <0>; 513 #power-domain-cells = <0>;
514 power-domains = <&pd_dma>; 514 power-domains = <&pd_dma>;
515 #address-cells = <1>; 515 #address-cells = <1>;
516 #size-cells = <0>; 516 #size-cells = <0>;
517 wakeup-irq = <348>; 517 wakeup-irq = <348>;
518 518
519 pd_dma0_chan18: PD_UART3_RX { 519 pd_dma0_chan18: PD_UART3_RX {
520 reg = <SC_R_DMA_0_CH18>; 520 reg = <SC_R_DMA_0_CH18>;
521 power-domains =<&pd_dma_lpuart3>; 521 power-domains =<&pd_dma_lpuart3>;
522 #power-domain-cells = <0>; 522 #power-domain-cells = <0>;
523 #address-cells = <1>; 523 #address-cells = <1>;
524 #size-cells = <0>; 524 #size-cells = <0>;
525 525
526 pd_dma0_chan19: PD_UART3_TX { 526 pd_dma0_chan19: PD_UART3_TX {
527 reg = <SC_R_DMA_0_CH19>; 527 reg = <SC_R_DMA_0_CH19>;
528 power-domains =<&pd_dma0_chan18>; 528 power-domains =<&pd_dma0_chan18>;
529 #power-domain-cells = <0>; 529 #power-domain-cells = <0>;
530 #address-cells = <1>; 530 #address-cells = <1>;
531 #size-cells = <0>; 531 #size-cells = <0>;
532 }; 532 };
533 }; 533 };
534 }; 534 };
535 pd_dma_lpuart4: PD_DMA_UART4 { 535 pd_dma_lpuart4: PD_DMA_UART4 {
536 reg = <SC_R_UART_4>; 536 reg = <SC_R_UART_4>;
537 #power-domain-cells = <0>; 537 #power-domain-cells = <0>;
538 power-domains = <&pd_dma>; 538 power-domains = <&pd_dma>;
539 #address-cells = <1>; 539 #address-cells = <1>;
540 #size-cells = <0>; 540 #size-cells = <0>;
541 wakeup-irq = <349>; 541 wakeup-irq = <349>;
542 542
543 pd_dma0_chan20: PD_UART4_RX { 543 pd_dma0_chan20: PD_UART4_RX {
544 reg = <SC_R_DMA_0_CH20>; 544 reg = <SC_R_DMA_0_CH20>;
545 power-domains =<&pd_dma_lpuart4>; 545 power-domains =<&pd_dma_lpuart4>;
546 #power-domain-cells = <0>; 546 #power-domain-cells = <0>;
547 #address-cells = <1>; 547 #address-cells = <1>;
548 #size-cells = <0>; 548 #size-cells = <0>;
549 549
550 pd_dma0_chan21: PD_UART4_TX { 550 pd_dma0_chan21: PD_UART4_TX {
551 reg = <SC_R_DMA_0_CH21>; 551 reg = <SC_R_DMA_0_CH21>;
552 power-domains =<&pd_dma0_chan20>; 552 power-domains =<&pd_dma0_chan20>;
553 #power-domain-cells = <0>; 553 #power-domain-cells = <0>;
554 #address-cells = <1>; 554 #address-cells = <1>;
555 #size-cells = <0>; 555 #size-cells = <0>;
556 }; 556 };
557 }; 557 };
558 }; 558 };
559 pd_dma_lpspi0: PD_DMA_SPI_0 { 559 pd_dma_lpspi0: PD_DMA_SPI_0 {
560 reg = <SC_R_SPI_0>; 560 reg = <SC_R_SPI_0>;
561 #power-domain-cells = <0>; 561 #power-domain-cells = <0>;
562 power-domains = <&pd_dma>; 562 power-domains = <&pd_dma>;
563 #address-cells = <1>; 563 #address-cells = <1>;
564 #size-cells = <0>; 564 #size-cells = <0>;
565 565
566 pd_dma0_chan0: PD_LPSPI0_RX { 566 pd_dma0_chan0: PD_LPSPI0_RX {
567 reg = <SC_R_DMA_0_CH0>; 567 reg = <SC_R_DMA_0_CH0>;
568 power-domains =<&pd_dma_lpspi0>; 568 power-domains =<&pd_dma_lpspi0>;
569 #power-domain-cells = <0>; 569 #power-domain-cells = <0>;
570 #address-cells = <1>; 570 #address-cells = <1>;
571 #size-cells = <0>; 571 #size-cells = <0>;
572 572
573 pd_dma0_chan1: PD_LPSPI0_TX { 573 pd_dma0_chan1: PD_LPSPI0_TX {
574 reg = <SC_R_DMA_0_CH1>; 574 reg = <SC_R_DMA_0_CH1>;
575 power-domains =<&pd_dma0_chan0>; 575 power-domains =<&pd_dma0_chan0>;
576 #power-domain-cells = <0>; 576 #power-domain-cells = <0>;
577 #address-cells = <1>; 577 #address-cells = <1>;
578 #size-cells = <0>; 578 #size-cells = <0>;
579 }; 579 };
580 }; 580 };
581 }; 581 };
582 pd_dma_lpspi1: PD_DMA_SPI_1 { 582 pd_dma_lpspi1: PD_DMA_SPI_1 {
583 reg = <SC_R_SPI_1>; 583 reg = <SC_R_SPI_1>;
584 #power-domain-cells = <0>; 584 #power-domain-cells = <0>;
585 power-domains = <&pd_dma>; 585 power-domains = <&pd_dma>;
586 }; 586 };
587 pd_dma_lpspi2: PD_DMA_SPI_2 { 587 pd_dma_lpspi2: PD_DMA_SPI_2 {
588 reg = <SC_R_SPI_2>; 588 reg = <SC_R_SPI_2>;
589 #power-domain-cells = <0>; 589 #power-domain-cells = <0>;
590 power-domains = <&pd_dma>; 590 power-domains = <&pd_dma>;
591 }; 591 };
592 pd_dma_lpspi3: PD_DMA_SPI_3 { 592 pd_dma_lpspi3: PD_DMA_SPI_3 {
593 reg = <SC_R_SPI_3>; 593 reg = <SC_R_SPI_3>;
594 #power-domain-cells = <0>; 594 #power-domain-cells = <0>;
595 power-domains = <&pd_dma>; 595 power-domains = <&pd_dma>;
596 #address-cells = <1>; 596 #address-cells = <1>;
597 #size-cells = <0>; 597 #size-cells = <0>;
598 598
599 pd_dma0_chan6: PD_LPSPI3_RX { 599 pd_dma0_chan6: PD_LPSPI3_RX {
600 reg = <SC_R_DMA_0_CH6>; 600 reg = <SC_R_DMA_0_CH6>;
601 power-domains =<&pd_dma_lpspi3>; 601 power-domains =<&pd_dma_lpspi3>;
602 #power-domain-cells = <0>; 602 #power-domain-cells = <0>;
603 #address-cells = <1>; 603 #address-cells = <1>;
604 #size-cells = <0>; 604 #size-cells = <0>;
605 605
606 pd_dma0_chan7: PD_LPSPI3_TX { 606 pd_dma0_chan7: PD_LPSPI3_TX {
607 reg = <SC_R_DMA_0_CH7>; 607 reg = <SC_R_DMA_0_CH7>;
608 power-domains =<&pd_dma0_chan6>; 608 power-domains =<&pd_dma0_chan6>;
609 #power-domain-cells = <0>; 609 #power-domain-cells = <0>;
610 #address-cells = <1>; 610 #address-cells = <1>;
611 #size-cells = <0>; 611 #size-cells = <0>;
612 }; 612 };
613 }; 613 };
614 }; 614 };
615 pd_dma_emvsim0: PD_DMA_EMVSIM_0 { 615 pd_dma_emvsim0: PD_DMA_EMVSIM_0 {
616 reg = <SC_R_EMVSIM_0>; 616 reg = <SC_R_EMVSIM_0>;
617 power-domains = <&pd_dma>; 617 power-domains = <&pd_dma>;
618 #power-domain-cells = <0>; 618 #power-domain-cells = <0>;
619 #address-cells = <1>; 619 #address-cells = <1>;
620 #size-cells = <0>; 620 #size-cells = <0>;
621 621
622 pd_ldo1_sim: LDO1_SIM { 622 pd_ldo1_sim: LDO1_SIM {
623 reg = <SC_R_BOARD_R2>; 623 reg = <SC_R_BOARD_R2>;
624 #power-domain-cells = <0>; 624 #power-domain-cells = <0>;
625 power-domains = <&pd_dma_emvsim0>; 625 power-domains = <&pd_dma_emvsim0>;
626 }; 626 };
627 }; 627 };
628 pd_dma_emvsim1: PD_DMA_EMVSIM_1 { 628 pd_dma_emvsim1: PD_DMA_EMVSIM_1 {
629 reg = <SC_R_EMVSIM_1>; 629 reg = <SC_R_EMVSIM_1>;
630 #power-domain-cells = <0>; 630 #power-domain-cells = <0>;
631 power-domains = <&pd_dma>; 631 power-domains = <&pd_dma>;
632 }; 632 };
633 }; 633 };
634 634
635 635
636 pd_isi_ch0: PD_IMAGING { 636 pd_isi_ch0: PD_IMAGING {
637 compatible = "nxp,imx8-pd"; 637 compatible = "nxp,imx8-pd";
638 reg = <SC_R_ISI_CH0>; 638 reg = <SC_R_ISI_CH0>;
639 #power-domain-cells = <0>; 639 #power-domain-cells = <0>;
640 #address-cells = <1>; 640 #address-cells = <1>;
641 #size-cells = <0>; 641 #size-cells = <0>;
642 642
643 pd_hdmi_rx: PD_HDMI_RX { 643 pd_hdmi_rx: PD_HDMI_RX {
644 reg = <SC_R_HDMI_RX>; 644 reg = <SC_R_HDMI_RX>;
645 #power-domain-cells = <0>; 645 #power-domain-cells = <0>;
646 power-domains =<&pd_isi_ch0>; 646 power-domains =<&pd_isi_ch0>;
647 #address-cells = <1>; 647 #address-cells = <1>;
648 #size-cells = <0>; 648 #size-cells = <0>;
649 649
650 pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS { 650 pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS {
651 reg = <SC_R_HDMI_RX_BYPASS>; 651 reg = <SC_R_HDMI_RX_BYPASS>;
652 #power-domain-cells = <0>; 652 #power-domain-cells = <0>;
653 power-domains =<&pd_hdmi_rx>; 653 power-domains =<&pd_hdmi_rx>;
654 #address-cells = <1>; 654 #address-cells = <1>;
655 #size-cells = <0>; 655 #size-cells = <0>;
656 656
657 pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C { 657 pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C {
658 reg = <SC_R_HDMI_RX_I2C_0>; 658 reg = <SC_R_HDMI_RX_I2C_0>;
659 #power-domain-cells = <0>; 659 #power-domain-cells = <0>;
660 power-domains =<&pd_hdmi_rx_bypass>; 660 power-domains =<&pd_hdmi_rx_bypass>;
661 }; 661 };
662 662
663 pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM { 663 pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM {
664 reg = <SC_R_HDMI_RX_PWM_0>; 664 reg = <SC_R_HDMI_RX_PWM_0>;
665 #power-domain-cells = <0>; 665 #power-domain-cells = <0>;
666 power-domains =<&pd_hdmi_rx_bypass>; 666 power-domains =<&pd_hdmi_rx_bypass>;
667 }; 667 };
668 }; 668 };
669 }; 669 };
670 670
671 }; 671 };
672 672
673 pd_caam: PD_CAAM { 673 pd_caam: PD_CAAM {
674 compatible = "nxp,imx8-pd"; 674 compatible = "nxp,imx8-pd";
675 reg = <SC_R_NONE>; 675 reg = <SC_R_NONE>;
676 #power-domain-cells = <0>; 676 #power-domain-cells = <0>;
677 #address-cells = <1>; 677 #address-cells = <1>;
678 #size-cells = <0>; 678 #size-cells = <0>;
679 679
680 pd_caam_jr1: PD_CAAM_JR1 { 680 pd_caam_jr1: PD_CAAM_JR1 {
681 reg = <SC_R_CAAM_JR1>; 681 reg = <SC_R_CAAM_JR1>;
682 #power-domain-cells = <0>; 682 #power-domain-cells = <0>;
683 power-domains = <&pd_caam>; 683 power-domains = <&pd_caam>;
684 }; 684 };
685 pd_caam_jr2: PD_CAAM_JR2 { 685 pd_caam_jr2: PD_CAAM_JR2 {
686 reg = <SC_R_CAAM_JR2>; 686 reg = <SC_R_CAAM_JR2>;
687 #power-domain-cells = <0>; 687 #power-domain-cells = <0>;
688 power-domains = <&pd_caam>; 688 power-domains = <&pd_caam>;
689 }; 689 };
690 pd_caam_jr3: PD_CAAM_JR3 { 690 pd_caam_jr3: PD_CAAM_JR3 {
691 reg = <SC_R_CAAM_JR3>; 691 reg = <SC_R_CAAM_JR3>;
692 #power-domain-cells = <0>; 692 #power-domain-cells = <0>;
693 power-domains = <&pd_caam>; 693 power-domains = <&pd_caam>;
694 }; 694 };
695 }; 695 };
696 }; 696 };
697 697
698 tsens: thermal-sensor { 698 tsens: thermal-sensor {
699 compatible = "nxp,imx8qm-sc-tsens"; 699 compatible = "nxp,imx8qm-sc-tsens";
700 u-boot,dm-pre-reloc; 700 u-boot,dm-pre-reloc;
701 /* number of the temp sensor on the chip */ 701 /* number of the temp sensor on the chip */
702 tsens-num = <5>; 702 tsens-num = <5>;
703 #thermal-sensor-cells = <1>; 703 #thermal-sensor-cells = <1>;
704 }; 704 };
705 705
706 thermal_zones: thermal-zones { 706 thermal_zones: thermal-zones {
707 /* cpu thermal */ 707 /* cpu thermal */
708 cpu-thermal0 { 708 cpu-thermal0 {
709 polling-delay-passive = <250>; 709 polling-delay-passive = <250>;
710 polling-delay = <2000>; 710 polling-delay = <2000>;
711 /*the slope and offset of the temp sensor */ 711 /*the slope and offset of the temp sensor */
712 thermal-sensors = <&tsens 0>; 712 thermal-sensors = <&tsens 0>;
713 trips { 713 trips {
714 cpu_alert0: trip0 { 714 cpu_alert0: trip0 {
715 temperature = <107000>; 715 temperature = <107000>;
716 hysteresis = <2000>; 716 hysteresis = <2000>;
717 type = "passive"; 717 type = "passive";
718 }; 718 };
719 cpu_crit0: trip1 { 719 cpu_crit0: trip1 {
720 temperature = <127000>; 720 temperature = <127000>;
721 hysteresis = <2000>; 721 hysteresis = <2000>;
722 type = "critical"; 722 type = "critical";
723 }; 723 };
724 }; 724 };
725 cooling-maps { 725 cooling-maps {
726 map0 { 726 map0 {
727 trip = <&cpu_alert0>; 727 trip = <&cpu_alert0>;
728 cooling-device = 728 cooling-device =
729 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 729 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
730 }; 730 };
731 }; 731 };
732 }; 732 };
733 733
734 cpu-thermal1 { 734 cpu-thermal1 {
735 polling-delay-passive = <250>; 735 polling-delay-passive = <250>;
736 polling-delay = <2000>; 736 polling-delay = <2000>;
737 thermal-sensors = <&tsens 1>; 737 thermal-sensors = <&tsens 1>;
738 trips { 738 trips {
739 cpu_alert1: trip0 { 739 cpu_alert1: trip0 {
740 temperature = <107000>; 740 temperature = <107000>;
741 hysteresis = <2000>; 741 hysteresis = <2000>;
742 type = "passive"; 742 type = "passive";
743 }; 743 };
744 cpu_crit1: trip1 { 744 cpu_crit1: trip1 {
745 temperature = <127000>; 745 temperature = <127000>;
746 hysteresis = <2000>; 746 hysteresis = <2000>;
747 type = "critical"; 747 type = "critical";
748 }; 748 };
749 }; 749 };
750 cooling-maps { 750 cooling-maps {
751 map0 { 751 map0 {
752 trip = <&cpu_alert1>; 752 trip = <&cpu_alert1>;
753 cooling-device = 753 cooling-device =
754 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 754 <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
755 }; 755 };
756 }; 756 };
757 }; 757 };
758 758
759 gpu-thermal0 { 759 gpu-thermal0 {
760 polling-delay-passive = <250>; 760 polling-delay-passive = <250>;
761 polling-delay = <2000>; 761 polling-delay = <2000>;
762 thermal-sensors = <&tsens 2>; 762 thermal-sensors = <&tsens 2>;
763 trips { 763 trips {
764 gpu_alert0: trip0 { 764 gpu_alert0: trip0 {
765 temperature = <107000>; 765 temperature = <107000>;
766 hysteresis = <2000>; 766 hysteresis = <2000>;
767 type = "passive"; 767 type = "passive";
768 }; 768 };
769 gpu_crit0: trip1 { 769 gpu_crit0: trip1 {
770 temperature = <127000>; 770 temperature = <127000>;
771 hysteresis = <2000>; 771 hysteresis = <2000>;
772 type = "critical"; 772 type = "critical";
773 }; 773 };
774 }; 774 };
775 }; 775 };
776 776
777 gpu-thermal1 { 777 gpu-thermal1 {
778 polling-delay-passive = <250>; 778 polling-delay-passive = <250>;
779 polling-delay = <2000>; 779 polling-delay = <2000>;
780 thermal-sensors = <&tsens 3>; 780 thermal-sensors = <&tsens 3>;
781 trips { 781 trips {
782 gpu_alert1: trip0 { 782 gpu_alert1: trip0 {
783 temperature = <107000>; 783 temperature = <107000>;
784 hysteresis = <2000>; 784 hysteresis = <2000>;
785 type = "passive"; 785 type = "passive";
786 }; 786 };
787 gpu_crit1: trip1 { 787 gpu_crit1: trip1 {
788 temperature = <127000>; 788 temperature = <127000>;
789 hysteresis = <2000>; 789 hysteresis = <2000>;
790 type = "critical"; 790 type = "critical";
791 }; 791 };
792 }; 792 };
793 }; 793 };
794 794
795 drc-thermal0 { 795 drc-thermal0 {
796 polling-delay-passive = <250>; 796 polling-delay-passive = <250>;
797 polling-delay = <2000>; 797 polling-delay = <2000>;
798 thermal-sensors = <&tsens 4>; 798 thermal-sensors = <&tsens 4>;
799 trips { 799 trips {
800 drc_alert0: trip0 { 800 drc_alert0: trip0 {
801 temperature = <107000>; 801 temperature = <107000>;
802 hysteresis = <2000>; 802 hysteresis = <2000>;
803 type = "passive"; 803 type = "passive";
804 }; 804 };
805 drc_crit0: trip1 { 805 drc_crit0: trip1 {
806 temperature = <127000>; 806 temperature = <127000>;
807 hysteresis = <2000>; 807 hysteresis = <2000>;
808 type = "critical"; 808 type = "critical";
809 }; 809 };
810 }; 810 };
811 }; 811 };
812 }; 812 };
813 813
814 rtc: rtc { 814 rtc: rtc {
815 compatible = "fsl,imx-sc-rtc"; 815 compatible = "fsl,imx-sc-rtc";
816 }; 816 };
817 817
818 dpu1_intsteer: dpu_intsteer@56000000 { 818 dpu1_intsteer: dpu_intsteer@56000000 {
819 compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; 819 compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
820 reg = <0x0 0x56000000 0x0 0x10000>; 820 reg = <0x0 0x56000000 0x0 0x10000>;
821 }; 821 };
822 822
823 dpu1: dpu@56180000 { 823 dpu1: dpu@56180000 {
824 #address-cells = <1>; 824 #address-cells = <1>;
825 #size-cells = <0>; 825 #size-cells = <0>;
826 compatible = "fsl,imx8qm-dpu"; 826 compatible = "fsl,imx8qm-dpu";
827 reg = <0x0 0x56180000 0x0 0x40000>; 827 reg = <0x0 0x56180000 0x0 0x40000>;
828 intsteer = <&dpu1_intsteer>; 828 intsteer = <&dpu1_intsteer>;
829 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 829 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 838 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
839 interrupt-names = "irq_common", 839 interrupt-names = "irq_common",
840 "irq_stream0a", 840 "irq_stream0a",
841 "irq_stream0b", /* to M4? */ 841 "irq_stream0b", /* to M4? */
842 "irq_stream1a", 842 "irq_stream1a",
843 "irq_stream1b", /* to M4? */ 843 "irq_stream1b", /* to M4? */
844 "irq_reserved0", 844 "irq_reserved0",
845 "irq_reserved1", 845 "irq_reserved1",
846 "irq_blit", 846 "irq_blit",
847 "irq_dpr0", 847 "irq_dpr0",
848 "irq_dpr1"; 848 "irq_dpr1";
849 clocks = <&clk IMX8QM_DC0_PLL0_CLK>, 849 clocks = <&clk IMX8QM_DC0_PLL0_CLK>,
850 <&clk IMX8QM_DC0_PLL1_CLK>, 850 <&clk IMX8QM_DC0_PLL1_CLK>,
851 <&clk IMX8QM_DC0_BYPASS_0_DIV>, 851 <&clk IMX8QM_DC0_BYPASS_0_DIV>,
852 <&clk IMX8QM_DC0_DISP0_SEL>, 852 <&clk IMX8QM_DC0_DISP0_SEL>,
853 <&clk IMX8QM_DC0_DISP1_SEL>, 853 <&clk IMX8QM_DC0_DISP1_SEL>,
854 <&clk IMX8QM_DC0_DISP0_CLK>, 854 <&clk IMX8QM_DC0_DISP0_CLK>,
855 <&clk IMX8QM_DC0_DISP1_CLK>; 855 <&clk IMX8QM_DC0_DISP1_CLK>;
856 clock-names = "pll0", "pll1", "bypass0", 856 clock-names = "pll0", "pll1", "bypass0",
857 "disp0_sel", "disp1_sel", "disp0", "disp1"; 857 "disp0_sel", "disp1_sel", "disp0", "disp1";
858 power-domains = <&pd_dc0_pll1>; 858 power-domains = <&pd_dc0_pll1>;
859 status = "disabled"; 859 status = "disabled";
860 860
861 dpu1_disp0: port@0 { 861 dpu1_disp0: port@0 {
862 reg = <0>; 862 reg = <0>;
863 863
864 dpu1_disp0_hdmi: hdmi-endpoint { 864 dpu1_disp0_hdmi: hdmi-endpoint {
865 remote-endpoint = <&hdmi_disp>; 865 remote-endpoint = <&hdmi_disp>;
866 }; 866 };
867 867
868 dpu1_disp0_mipi_dsi: mipi-dsi-endpoint { 868 dpu1_disp0_mipi_dsi: mipi-dsi-endpoint {
869 remote-endpoint = <&mipi_dsi1_in>; 869 remote-endpoint = <&mipi_dsi1_in>;
870 }; 870 };
871 }; 871 };
872 872
873 dpu1_disp1: port@1 { 873 dpu1_disp1: port@1 {
874 reg = <1>; 874 reg = <1>;
875 875
876 dpu1_disp1_lvds0: lvds0-endpoint { 876 dpu1_disp1_lvds0: lvds0-endpoint {
877 remote-endpoint = <&ldb1_lvds0>; 877 remote-endpoint = <&ldb1_lvds0>;
878 }; 878 };
879 879
880 dpu1_disp1_lvds1: lvds1-endpoint { 880 dpu1_disp1_lvds1: lvds1-endpoint {
881 remote-endpoint = <&ldb1_lvds1>; 881 remote-endpoint = <&ldb1_lvds1>;
882 }; 882 };
883 }; 883 };
884 }; 884 };
885 885
886 hdmi:hdmi@56268000 { 886 hdmi:hdmi@56268000 {
887 #address-cells = <1>; 887 #address-cells = <1>;
888 #size-cells = <0>; 888 #size-cells = <0>;
889 reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */ 889 reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */
890 <0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR */ 890 <0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR */
891 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 891 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
892 <13 IRQ_TYPE_LEVEL_HIGH>; 892 <13 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "plug_in", "plug_out"; 893 interrupt-names = "plug_in", "plug_out";
894 interrupt-parent = <&irqsteer_hdmi>; 894 interrupt-parent = <&irqsteer_hdmi>;
895 status = "disabled"; 895 status = "disabled";
896 clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, 896 clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
897 <&clk IMX8QM_HDMI_AV_PLL_CLK>, 897 <&clk IMX8QM_HDMI_AV_PLL_CLK>,
898 <&clk IMX8QM_HDMI_IPG_CLK>, 898 <&clk IMX8QM_HDMI_IPG_CLK>,
899 <&clk IMX8QM_HDMI_HDP_CORE_CLK>, 899 <&clk IMX8QM_HDMI_HDP_CORE_CLK>,
900 <&clk IMX8QM_HDMI_PXL_CLK>, 900 <&clk IMX8QM_HDMI_PXL_CLK>,
901 <&clk IMX8QM_HDMI_PXL_MUX_CLK>, 901 <&clk IMX8QM_HDMI_PXL_MUX_CLK>,
902 <&clk IMX8QM_HDMI_PXL_LINK_CLK>, 902 <&clk IMX8QM_HDMI_PXL_LINK_CLK>,
903 <&clk IMX8QM_HDMI_HDP_CLK>, 903 <&clk IMX8QM_HDMI_HDP_CLK>,
904 <&clk IMX8QM_HDMI_HDP_PHY_CLK>, 904 <&clk IMX8QM_HDMI_HDP_PHY_CLK>,
905 <&clk IMX8QM_HDMI_APB_CLK>, 905 <&clk IMX8QM_HDMI_APB_CLK>,
906 <&clk IMX8QM_HDMI_LIS_IPG_CLK>, 906 <&clk IMX8QM_HDMI_LIS_IPG_CLK>,
907 <&clk IMX8QM_HDMI_MSI_HCLK>, 907 <&clk IMX8QM_HDMI_MSI_HCLK>,
908 <&clk IMX8QM_HDMI_PXL_LPCG_CLK>, 908 <&clk IMX8QM_HDMI_PXL_LPCG_CLK>,
909 <&clk IMX8QM_HDMI_PXL_EVEN_CLK>, 909 <&clk IMX8QM_HDMI_PXL_EVEN_CLK>,
910 <&clk IMX8QM_HDMI_PXL_DBL_CLK>, 910 <&clk IMX8QM_HDMI_PXL_DBL_CLK>,
911 <&clk IMX8QM_HDMI_VIF_CLK>, 911 <&clk IMX8QM_HDMI_VIF_CLK>,
912 <&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>, 912 <&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>,
913 <&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>, 913 <&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>,
914 <&clk IMX8QM_HDMI_I2S_CLK>, 914 <&clk IMX8QM_HDMI_I2S_CLK>,
915 <&clk IMX8QM_HDMI_I2S_BYPASS_CLK>; 915 <&clk IMX8QM_HDMI_I2S_BYPASS_CLK>;
916 clock-names = "dig_pll", "av_pll", "clk_ipg", 916 clock-names = "dig_pll", "av_pll", "clk_ipg",
917 "clk_core", "clk_pxl", "clk_pxl_mux", 917 "clk_core", "clk_pxl", "clk_pxl_mux",
918 "clk_pxl_link", "clk_hdp", "clk_phy", 918 "clk_pxl_link", "clk_hdp", "clk_phy",
919 "clk_apb", "clk_lis","clk_msi", 919 "clk_apb", "clk_lis","clk_msi",
920 "clk_lpcg", "clk_even","clk_dbl", 920 "clk_lpcg", "clk_even","clk_dbl",
921 "clk_vif", "clk_apb_csr","clk_apb_ctrl", 921 "clk_vif", "clk_apb_csr","clk_apb_ctrl",
922 "clk_i2s", "clk_i2s_bypass"; 922 "clk_i2s", "clk_i2s_bypass";
923 power-domains = <&pd_hdmi_i2s>; 923 power-domains = <&pd_hdmi_i2s>;
924 924
925 port@0 { 925 port@0 {
926 reg = <0>; 926 reg = <0>;
927 hdmi_disp: endpoint { 927 hdmi_disp: endpoint {
928 remote-endpoint = <&dpu1_disp0_hdmi>; 928 remote-endpoint = <&dpu1_disp0_hdmi>;
929 }; 929 };
930 }; 930 };
931 }; 931 };
932 932
933 irqsteer_dsi0: irqsteer@56220000 { 933 irqsteer_dsi0: irqsteer@56220000 {
934 compatible = "nxp,imx-irqsteer"; 934 compatible = "nxp,imx-irqsteer";
935 reg = <0x0 0x56220000 0x0 0x1000>; 935 reg = <0x0 0x56220000 0x0 0x1000>;
936 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 936 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
937 interrupt-controller; 937 interrupt-controller;
938 interrupt-parent = <&gic>; 938 interrupt-parent = <&gic>;
939 #interrupt-cells = <2>; 939 #interrupt-cells = <2>;
940 clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>; 940 clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>;
941 clock-names = "ipg"; 941 clock-names = "ipg";
942 power-domains = <&pd_mipi0>; 942 power-domains = <&pd_mipi0>;
943 }; 943 };
944 944
945 i2c0_mipi_dsi0: i2c@56226000 { 945 i2c0_mipi_dsi0: i2c@56226000 {
946 compatible = "fsl,imx8qm-lpi2c"; 946 compatible = "fsl,imx8qm-lpi2c";
947 reg = <0x0 0x56226000 0x0 0x1000>; 947 reg = <0x0 0x56226000 0x0 0x1000>;
948 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 948 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
949 interrupt-parent = <&irqsteer_dsi0>; 949 interrupt-parent = <&irqsteer_dsi0>;
950 clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>, 950 clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>,
951 <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>; 951 <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>;
952 clock-names = "per", "ipg"; 952 clock-names = "per", "ipg";
953 assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>; 953 assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>;
954 assigned-clock-rates = <24000000>; 954 assigned-clock-rates = <24000000>;
955 power-domains = <&pd_mipi0_i2c0>; 955 power-domains = <&pd_mipi0_i2c0>;
956 status = "disabled"; 956 status = "disabled";
957 }; 957 };
958 958
959 mipi_dsi_csr1: csr@56221000 { 959 mipi_dsi_csr1: csr@56221000 {
960 compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; 960 compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
961 reg = <0x0 0x56221000 0x0 0x1000>; 961 reg = <0x0 0x56221000 0x0 0x1000>;
962 }; 962 };
963 963
964 mipi_dsi_phy1: dsi_phy@56228300 { 964 mipi_dsi_phy1: dsi_phy@56228300 {
965 #address-cells = <1>; 965 #address-cells = <1>;
966 #size-cells = <0>; 966 #size-cells = <0>;
967 compatible = "mixel,imx8qm-mipi-dsi-phy"; 967 compatible = "mixel,imx8qm-mipi-dsi-phy";
968 reg = <0x0 0x56228300 0x0 0x100>; 968 reg = <0x0 0x56228300 0x0 0x100>;
969 power-domains = <&pd_mipi0>; 969 power-domains = <&pd_mipi0>;
970 #phy-cells = <0>; 970 #phy-cells = <0>;
971 status = "disabled"; 971 status = "disabled";
972 }; 972 };
973 973
974 mipi_dsi1: mipi_dsi@56228000 { 974 mipi_dsi1: mipi_dsi@56228000 {
975 compatible = "fsl,imx8qm-mipi-dsi"; 975 compatible = "fsl,imx8qm-mipi-dsi";
976 clocks = 976 clocks =
977 <&clk IMX8QM_MIPI0_PXL_CLK>, 977 <&clk IMX8QM_MIPI0_PXL_CLK>,
978 <&clk IMX8QM_MIPI0_BYPASS_CLK>, 978 <&clk IMX8QM_MIPI0_BYPASS_CLK>,
979 <&clk IMX8QM_CLK_DUMMY>; 979 <&clk IMX8QM_CLK_DUMMY>;
980 clock-names = "pixel", "bypass", "phy_ref"; 980 clock-names = "pixel", "bypass", "phy_ref";
981 power-domains = <&pd_mipi0>; 981 power-domains = <&pd_mipi0>;
982 csr = <&mipi_dsi_csr1>; 982 csr = <&mipi_dsi_csr1>;
983 phys = <&mipi_dsi_phy1>; 983 phys = <&mipi_dsi_phy1>;
984 phy-names = "dphy"; 984 phy-names = "dphy";
985 pwr-delay = <100>; 985 pwr-delay = <100>;
986 status = "disabled"; 986 status = "disabled";
987 987
988 port@0 { 988 port@0 {
989 mipi_dsi1_in: endpoint { 989 mipi_dsi1_in: endpoint {
990 remote-endpoint = <&dpu1_disp0_mipi_dsi>; 990 remote-endpoint = <&dpu1_disp0_mipi_dsi>;
991 }; 991 };
992 }; 992 };
993 993
994 port@1 { 994 port@1 {
995 mipi_dsi1_out: endpoint { 995 mipi_dsi1_out: endpoint {
996 remote-endpoint = <&mipi_dsi_bridge1_in>; 996 remote-endpoint = <&mipi_dsi_bridge1_in>;
997 }; 997 };
998 }; 998 };
999 }; 999 };
1000 1000
1001 mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { 1001 mipi_dsi_bridge1: mipi_dsi_bridge@56228000 {
1002 #address-cells = <1>; 1002 #address-cells = <1>;
1003 #size-cells = <0>; 1003 #size-cells = <0>;
1004 compatible = "nwl,mipi-dsi"; 1004 compatible = "nwl,mipi-dsi";
1005 reg = <0x0 0x56228000 0x0 0x300>; 1005 reg = <0x0 0x56228000 0x0 0x300>;
1006 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
1007 interrupt-parent = <&irqsteer_dsi0>; 1007 interrupt-parent = <&irqsteer_dsi0>;
1008 clocks = 1008 clocks =
1009 <&clk IMX8QM_MIPI0_BYPASS_CLK>, 1009 <&clk IMX8QM_MIPI0_BYPASS_CLK>,
1010 <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, 1010 <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>,
1011 <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; 1011 <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>;
1012 clock-names = "phy_ref", "tx_esc", "rx_esc"; 1012 clock-names = "phy_ref", "tx_esc", "rx_esc";
1013 assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>, 1013 assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>,
1014 <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>; 1014 <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>;
1015 assigned-clock-rates = <18000000>, <72000000>; 1015 assigned-clock-rates = <18000000>, <72000000>;
1016 power-domains = <&pd_mipi0>; 1016 power-domains = <&pd_mipi0>;
1017 phys = <&mipi_dsi_phy1>; 1017 phys = <&mipi_dsi_phy1>;
1018 phy-names = "dphy"; 1018 phy-names = "dphy";
1019 status = "disabled"; 1019 status = "disabled";
1020 1020
1021 port@0 { 1021 port@0 {
1022 mipi_dsi_bridge1_in: endpoint { 1022 mipi_dsi_bridge1_in: endpoint {
1023 remote-endpoint = <&mipi_dsi1_out>; 1023 remote-endpoint = <&mipi_dsi1_out>;
1024 }; 1024 };
1025 }; 1025 };
1026 }; 1026 };
1027 1027
1028 lvds_region1: lvds_region@56240000 { 1028 lvds_region1: lvds_region@56240000 {
1029 compatible = "fsl,imx8qm-lvds-region", "syscon"; 1029 compatible = "fsl,imx8qm-lvds-region", "syscon";
1030 reg = <0x0 0x56240000 0x0 0x10000>; 1030 reg = <0x0 0x56240000 0x0 0x10000>;
1031 }; 1031 };
1032 1032
1033 ldb1_phy: ldb_phy@56241000 { 1033 ldb1_phy: ldb_phy@56241000 {
1034 #address-cells = <1>; 1034 #address-cells = <1>;
1035 #size-cells = <0>; 1035 #size-cells = <0>;
1036 compatible = "mixel,lvds-phy"; 1036 compatible = "mixel,lvds-phy";
1037 reg = <0x0 0x56241000 0x0 0x100>; 1037 reg = <0x0 0x56241000 0x0 0x100>;
1038 clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; 1038 clocks = <&clk IMX8QM_LVDS0_PHY_CLK>;
1039 clock-names = "phy"; 1039 clock-names = "phy";
1040 power-domains = <&pd_lvds0>; 1040 power-domains = <&pd_lvds0>;
1041 status = "disabled"; 1041 status = "disabled";
1042 1042
1043 ldb1_phy1: port@0 { 1043 ldb1_phy1: port@0 {
1044 reg = <0>; 1044 reg = <0>;
1045 #phy-cells = <0>; 1045 #phy-cells = <0>;
1046 }; 1046 };
1047 1047
1048 ldb1_phy2: port@1 { 1048 ldb1_phy2: port@1 {
1049 reg = <1>; 1049 reg = <1>;
1050 #phy-cells = <0>; 1050 #phy-cells = <0>;
1051 }; 1051 };
1052 }; 1052 };
1053 1053
1054 ldb1: ldb@562410e0 { 1054 ldb1: ldb@562410e0 {
1055 #address-cells = <1>; 1055 #address-cells = <1>;
1056 #size-cells = <0>; 1056 #size-cells = <0>;
1057 compatible = "fsl,imx8qm-ldb"; 1057 compatible = "fsl,imx8qm-ldb";
1058 clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, 1058 clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>,
1059 <&clk IMX8QM_LVDS0_BYPASS_CLK>; 1059 <&clk IMX8QM_LVDS0_BYPASS_CLK>;
1060 clock-names = "pixel", "bypass"; 1060 clock-names = "pixel", "bypass";
1061 power-domains = <&pd_lvds0>; 1061 power-domains = <&pd_lvds0>;
1062 gpr = <&lvds_region1>; 1062 gpr = <&lvds_region1>;
1063 status = "disabled"; 1063 status = "disabled";
1064 1064
1065 lvds-channel@0 { 1065 lvds-channel@0 {
1066 #address-cells = <1>; 1066 #address-cells = <1>;
1067 #size-cells = <0>; 1067 #size-cells = <0>;
1068 reg = <0>; 1068 reg = <0>;
1069 phys = <&ldb1_phy1>; 1069 phys = <&ldb1_phy1>;
1070 phy-names = "ldb_phy"; 1070 phy-names = "ldb_phy";
1071 status = "disabled"; 1071 status = "disabled";
1072 1072
1073 port@0 { 1073 port@0 {
1074 reg = <0>; 1074 reg = <0>;
1075 1075
1076 ldb1_lvds0: endpoint { 1076 ldb1_lvds0: endpoint {
1077 remote-endpoint = <&dpu1_disp1_lvds0>; 1077 remote-endpoint = <&dpu1_disp1_lvds0>;
1078 }; 1078 };
1079 }; 1079 };
1080 }; 1080 };
1081 1081
1082 lvds-channel@1 { 1082 lvds-channel@1 {
1083 #address-cells = <1>; 1083 #address-cells = <1>;
1084 #size-cells = <0>; 1084 #size-cells = <0>;
1085 reg = <1>; 1085 reg = <1>;
1086 phys = <&ldb1_phy2>; 1086 phys = <&ldb1_phy2>;
1087 phy-names = "ldb_phy"; 1087 phy-names = "ldb_phy";
1088 status = "disabled"; 1088 status = "disabled";
1089 1089
1090 port@0 { 1090 port@0 {
1091 reg = <0>; 1091 reg = <0>;
1092 1092
1093 ldb1_lvds1: endpoint { 1093 ldb1_lvds1: endpoint {
1094 remote-endpoint = <&dpu1_disp1_lvds1>; 1094 remote-endpoint = <&dpu1_disp1_lvds1>;
1095 }; 1095 };
1096 }; 1096 };
1097 }; 1097 };
1098 }; 1098 };
1099 1099
1100 lvds0_pwm: pwm@56244000 { 1100 lvds0_pwm: pwm@56244000 {
1101 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; 1101 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
1102 reg = <0x0 0x56244000 0 0x1000>; 1102 reg = <0x0 0x56244000 0 0x1000>;
1103 clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>, 1103 clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>,
1104 <&clk IMX8QM_LVDS0_PWM0_CLK>; 1104 <&clk IMX8QM_LVDS0_PWM0_CLK>;
1105 clock-names = "ipg", "per"; 1105 clock-names = "ipg", "per";
1106 assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>; 1106 assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>;
1107 assigned-clock-rates = <24000000>; 1107 assigned-clock-rates = <24000000>;
1108 #pwm-cells = <2>; 1108 #pwm-cells = <2>;
1109 power-domains = <&pd_lvds0_pwm>; 1109 power-domains = <&pd_lvds0_pwm>;
1110 status = "disabled"; 1110 status = "disabled";
1111 }; 1111 };
1112 1112
1113 dpu2_intsteer: dpu_intsteer@57000000 { 1113 dpu2_intsteer: dpu_intsteer@57000000 {
1114 compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; 1114 compatible = "fsl,imx8qm-dpu-intsteer", "syscon";
1115 reg = <0x0 0x57000000 0x0 0x10000>; 1115 reg = <0x0 0x57000000 0x0 0x10000>;
1116 }; 1116 };
1117 1117
1118 dpu2: dpu@57180000 { 1118 dpu2: dpu@57180000 {
1119 #address-cells = <1>; 1119 #address-cells = <1>;
1120 #size-cells = <0>; 1120 #size-cells = <0>;
1121 compatible = "fsl,imx8qm-dpu"; 1121 compatible = "fsl,imx8qm-dpu";
1122 reg = <0x0 0x57180000 0x0 0x40000>; 1122 reg = <0x0 0x57180000 0x0 0x40000>;
1123 intsteer = <&dpu2_intsteer>; 1123 intsteer = <&dpu2_intsteer>;
1124 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1124 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1125 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1126 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 1133 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1134 interrupt-names = "irq_common", 1134 interrupt-names = "irq_common",
1135 "irq_stream0a", 1135 "irq_stream0a",
1136 "irq_stream0b", /* to M4? */ 1136 "irq_stream0b", /* to M4? */
1137 "irq_stream1a", 1137 "irq_stream1a",
1138 "irq_stream1b", /* to M4? */ 1138 "irq_stream1b", /* to M4? */
1139 "irq_reserved0", 1139 "irq_reserved0",
1140 "irq_reserved1", 1140 "irq_reserved1",
1141 "irq_blit", 1141 "irq_blit",
1142 "irq_dpr0", 1142 "irq_dpr0",
1143 "irq_dpr1"; 1143 "irq_dpr1";
1144 clocks = <&clk IMX8QM_DC1_PLL0_CLK>, 1144 clocks = <&clk IMX8QM_DC1_PLL0_CLK>,
1145 <&clk IMX8QM_DC1_PLL1_CLK>, 1145 <&clk IMX8QM_DC1_PLL1_CLK>,
1146 <&clk IMX8QM_DC1_BYPASS_0_DIV>, 1146 <&clk IMX8QM_DC1_BYPASS_0_DIV>,
1147 <&clk IMX8QM_DC1_DISP0_SEL>, 1147 <&clk IMX8QM_DC1_DISP0_SEL>,
1148 <&clk IMX8QM_DC1_DISP1_SEL>, 1148 <&clk IMX8QM_DC1_DISP1_SEL>,
1149 <&clk IMX8QM_DC1_DISP0_CLK>, 1149 <&clk IMX8QM_DC1_DISP0_CLK>,
1150 <&clk IMX8QM_DC1_DISP1_CLK>; 1150 <&clk IMX8QM_DC1_DISP1_CLK>;
1151 clock-names = "pll0", "pll1", "bypass0", 1151 clock-names = "pll0", "pll1", "bypass0",
1152 "disp0_sel", "disp1_sel", "disp0", "disp1"; 1152 "disp0_sel", "disp1_sel", "disp0", "disp1";
1153 power-domains = <&pd_dc1_pll1>; 1153 power-domains = <&pd_dc1_pll1>;
1154 status = "disabled"; 1154 status = "disabled";
1155 1155
1156 dpu2_disp0: port@0 { 1156 dpu2_disp0: port@0 {
1157 reg = <0>; 1157 reg = <0>;
1158 1158
1159 dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { 1159 dpu2_disp0_mipi_dsi: mipi-dsi-endpoint {
1160 remote-endpoint = <&mipi_dsi2_in>; 1160 remote-endpoint = <&mipi_dsi2_in>;
1161 }; 1161 };
1162 }; 1162 };
1163 1163
1164 dpu2_disp1: port@1 { 1164 dpu2_disp1: port@1 {
1165 reg = <1>; 1165 reg = <1>;
1166 1166
1167 dpu2_disp1_lvds0: lvds0-endpoint { 1167 dpu2_disp1_lvds0: lvds0-endpoint {
1168 remote-endpoint = <&ldb2_lvds0>; 1168 remote-endpoint = <&ldb2_lvds0>;
1169 }; 1169 };
1170 1170
1171 dpu2_disp1_lvds1: lvds1-endpoint { 1171 dpu2_disp1_lvds1: lvds1-endpoint {
1172 remote-endpoint = <&ldb2_lvds1>; 1172 remote-endpoint = <&ldb2_lvds1>;
1173 }; 1173 };
1174 }; 1174 };
1175 }; 1175 };
1176 1176
1177 irqsteer_dsi1: irqsteer@57220000 { 1177 irqsteer_dsi1: irqsteer@57220000 {
1178 compatible = "nxp,imx-irqsteer"; 1178 compatible = "nxp,imx-irqsteer";
1179 reg = <0x0 0x57220000 0x0 0x1000>; 1179 reg = <0x0 0x57220000 0x0 0x1000>;
1180 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1180 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-controller; 1181 interrupt-controller;
1182 interrupt-parent = <&gic>; 1182 interrupt-parent = <&gic>;
1183 #interrupt-cells = <2>; 1183 #interrupt-cells = <2>;
1184 clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>; 1184 clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>;
1185 clock-names = "ipg"; 1185 clock-names = "ipg";
1186 power-domains = <&pd_mipi1>; 1186 power-domains = <&pd_mipi1>;
1187 }; 1187 };
1188 1188
1189 i2c0_mipi_dsi1: i2c@57226000 { 1189 i2c0_mipi_dsi1: i2c@57226000 {
1190 compatible = "fsl,imx8qm-lpi2c"; 1190 compatible = "fsl,imx8qm-lpi2c";
1191 reg = <0x0 0x57226000 0x0 0x1000>; 1191 reg = <0x0 0x57226000 0x0 0x1000>;
1192 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1192 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1193 interrupt-parent = <&irqsteer_dsi1>; 1193 interrupt-parent = <&irqsteer_dsi1>;
1194 clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>, 1194 clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>,
1195 <&clk IMX8QM_MIPI1_I2C0_IPG_CLK>; 1195 <&clk IMX8QM_MIPI1_I2C0_IPG_CLK>;
1196 clock-names = "per", "ipg"; 1196 clock-names = "per", "ipg";
1197 assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>; 1197 assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>;
1198 assigned-clock-rates = <24000000>; 1198 assigned-clock-rates = <24000000>;
1199 power-domains = <&pd_mipi1_i2c0>; 1199 power-domains = <&pd_mipi1_i2c0>;
1200 status = "disabled"; 1200 status = "disabled";
1201 }; 1201 };
1202 1202
1203 mipi_dsi_csr2: csr@57221000 { 1203 mipi_dsi_csr2: csr@57221000 {
1204 compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; 1204 compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon";
1205 reg = <0x0 0x57221000 0x0 0x1000>; 1205 reg = <0x0 0x57221000 0x0 0x1000>;
1206 }; 1206 };
1207 1207
1208 mipi_dsi_phy2: mipi_phy@57228300 { 1208 mipi_dsi_phy2: mipi_phy@57228300 {
1209 #address-cells = <1>; 1209 #address-cells = <1>;
1210 #size-cells = <0>; 1210 #size-cells = <0>;
1211 compatible = "mixel,imx8qm-mipi-dsi-phy"; 1211 compatible = "mixel,imx8qm-mipi-dsi-phy";
1212 reg = <0x0 0x57228300 0x0 0x100>; 1212 reg = <0x0 0x57228300 0x0 0x100>;
1213 power-domains = <&pd_mipi1>; 1213 power-domains = <&pd_mipi1>;
1214 #phy-cells = <0>; 1214 #phy-cells = <0>;
1215 status = "disabled"; 1215 status = "disabled";
1216 }; 1216 };
1217 1217
1218 mipi_dsi2: mipi_dsi@57228000 { 1218 mipi_dsi2: mipi_dsi@57228000 {
1219 compatible = "fsl,imx8qm-mipi-dsi"; 1219 compatible = "fsl,imx8qm-mipi-dsi";
1220 clocks = 1220 clocks =
1221 <&clk IMX8QM_MIPI1_PXL_CLK>, 1221 <&clk IMX8QM_MIPI1_PXL_CLK>,
1222 <&clk IMX8QM_MIPI1_BYPASS_CLK>, 1222 <&clk IMX8QM_MIPI1_BYPASS_CLK>,
1223 <&clk IMX8QM_CLK_DUMMY>; 1223 <&clk IMX8QM_CLK_DUMMY>;
1224 clock-names = "pixel", "bypass", "phy_ref"; 1224 clock-names = "pixel", "bypass", "phy_ref";
1225 power-domains = <&pd_mipi1>; 1225 power-domains = <&pd_mipi1>;
1226 csr = <&mipi_dsi_csr2>; 1226 csr = <&mipi_dsi_csr2>;
1227 phys = <&mipi_dsi_phy2>; 1227 phys = <&mipi_dsi_phy2>;
1228 phy-names = "dphy"; 1228 phy-names = "dphy";
1229 pwr-delay = <100>; 1229 pwr-delay = <100>;
1230 status = "disabled"; 1230 status = "disabled";
1231 1231
1232 port@0 { 1232 port@0 {
1233 mipi_dsi2_in: endpoint { 1233 mipi_dsi2_in: endpoint {
1234 remote-endpoint = <&dpu2_disp0_mipi_dsi>; 1234 remote-endpoint = <&dpu2_disp0_mipi_dsi>;
1235 }; 1235 };
1236 }; 1236 };
1237 1237
1238 port@1 { 1238 port@1 {
1239 mipi_dsi2_out: endpoint { 1239 mipi_dsi2_out: endpoint {
1240 remote-endpoint = <&mipi_dsi_bridge2_in>; 1240 remote-endpoint = <&mipi_dsi_bridge2_in>;
1241 }; 1241 };
1242 }; 1242 };
1243 }; 1243 };
1244 1244
1245 mipi_dsi_bridge2: mipi_dsi_bridge@57228000 { 1245 mipi_dsi_bridge2: mipi_dsi_bridge@57228000 {
1246 #address-cells = <1>; 1246 #address-cells = <1>;
1247 #size-cells = <0>; 1247 #size-cells = <0>;
1248 compatible = "nwl,mipi-dsi"; 1248 compatible = "nwl,mipi-dsi";
1249 reg = <0x0 0x57228000 0x0 0x300>; 1249 reg = <0x0 0x57228000 0x0 0x300>;
1250 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 1250 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
1251 interrupt-parent = <&irqsteer_dsi1>; 1251 interrupt-parent = <&irqsteer_dsi1>;
1252 clocks = 1252 clocks =
1253 <&clk IMX8QM_MIPI1_BYPASS_CLK>, 1253 <&clk IMX8QM_MIPI1_BYPASS_CLK>,
1254 <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, 1254 <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>,
1255 <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; 1255 <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>;
1256 clock-names = "phy_ref", "tx_esc", "rx_esc"; 1256 clock-names = "phy_ref", "tx_esc", "rx_esc";
1257 assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>, 1257 assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>,
1258 <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>; 1258 <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>;
1259 assigned-clock-rates = <18000000>, <72000000>; 1259 assigned-clock-rates = <18000000>, <72000000>;
1260 power-domains = <&pd_mipi1>; 1260 power-domains = <&pd_mipi1>;
1261 phys = <&mipi_dsi_phy2>; 1261 phys = <&mipi_dsi_phy2>;
1262 phy-names = "dphy"; 1262 phy-names = "dphy";
1263 status = "disabled"; 1263 status = "disabled";
1264 1264
1265 port@0 { 1265 port@0 {
1266 mipi_dsi_bridge2_in: endpoint { 1266 mipi_dsi_bridge2_in: endpoint {
1267 remote-endpoint = <&mipi_dsi2_out>; 1267 remote-endpoint = <&mipi_dsi2_out>;
1268 }; 1268 };
1269 }; 1269 };
1270 }; 1270 };
1271 1271
1272 lvds_region2: lvds_region@57240000 { 1272 lvds_region2: lvds_region@57240000 {
1273 compatible = "fsl,imx8qm-lvds-region", "syscon"; 1273 compatible = "fsl,imx8qm-lvds-region", "syscon";
1274 reg = <0x0 0x57240000 0x0 0x10000>; 1274 reg = <0x0 0x57240000 0x0 0x10000>;
1275 }; 1275 };
1276 1276
1277 ldb2_phy: ldb_phy@57241000 { 1277 ldb2_phy: ldb_phy@57241000 {
1278 #address-cells = <1>; 1278 #address-cells = <1>;
1279 #size-cells = <0>; 1279 #size-cells = <0>;
1280 compatible = "mixel,lvds-phy"; 1280 compatible = "mixel,lvds-phy";
1281 reg = <0x0 0x57241000 0x0 0x100>; 1281 reg = <0x0 0x57241000 0x0 0x100>;
1282 clocks = <&clk IMX8QM_LVDS1_PHY_CLK>; 1282 clocks = <&clk IMX8QM_LVDS1_PHY_CLK>;
1283 clock-names = "phy"; 1283 clock-names = "phy";
1284 power-domains = <&pd_lvds1>; 1284 power-domains = <&pd_lvds1>;
1285 status = "disabled"; 1285 status = "disabled";
1286 1286
1287 ldb2_phy1: port@0 { 1287 ldb2_phy1: port@0 {
1288 reg = <0>; 1288 reg = <0>;
1289 #phy-cells = <0>; 1289 #phy-cells = <0>;
1290 }; 1290 };
1291 1291
1292 ldb2_phy2: port@1 { 1292 ldb2_phy2: port@1 {
1293 reg = <1>; 1293 reg = <1>;
1294 #phy-cells = <0>; 1294 #phy-cells = <0>;
1295 }; 1295 };
1296 }; 1296 };
1297 1297
1298 ldb2: ldb@572410e0 { 1298 ldb2: ldb@572410e0 {
1299 #address-cells = <1>; 1299 #address-cells = <1>;
1300 #size-cells = <0>; 1300 #size-cells = <0>;
1301 compatible = "fsl,imx8qm-ldb"; 1301 compatible = "fsl,imx8qm-ldb";
1302 clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, 1302 clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>,
1303 <&clk IMX8QM_LVDS1_BYPASS_CLK>; 1303 <&clk IMX8QM_LVDS1_BYPASS_CLK>;
1304 clock-names = "pixel", "bypass"; 1304 clock-names = "pixel", "bypass";
1305 power-domains = <&pd_lvds1>; 1305 power-domains = <&pd_lvds1>;
1306 gpr = <&lvds_region2>; 1306 gpr = <&lvds_region2>;
1307 status = "disabled"; 1307 status = "disabled";
1308 1308
1309 lvds-channel@0 { 1309 lvds-channel@0 {
1310 #address-cells = <1>; 1310 #address-cells = <1>;
1311 #size-cells = <0>; 1311 #size-cells = <0>;
1312 reg = <0>; 1312 reg = <0>;
1313 phys = <&ldb2_phy1>; 1313 phys = <&ldb2_phy1>;
1314 phy-names = "ldb_phy"; 1314 phy-names = "ldb_phy";
1315 status = "disabled"; 1315 status = "disabled";
1316 1316
1317 port@0 { 1317 port@0 {
1318 reg = <0>; 1318 reg = <0>;
1319 1319
1320 ldb2_lvds0: endpoint { 1320 ldb2_lvds0: endpoint {
1321 remote-endpoint = <&dpu2_disp1_lvds0>; 1321 remote-endpoint = <&dpu2_disp1_lvds0>;
1322 }; 1322 };
1323 }; 1323 };
1324 }; 1324 };
1325 1325
1326 lvds-channel@1 { 1326 lvds-channel@1 {
1327 #address-cells = <1>; 1327 #address-cells = <1>;
1328 #size-cells = <0>; 1328 #size-cells = <0>;
1329 reg = <1>; 1329 reg = <1>;
1330 phys = <&ldb2_phy2>; 1330 phys = <&ldb2_phy2>;
1331 phy-names = "ldb_phy"; 1331 phy-names = "ldb_phy";
1332 status = "disabled"; 1332 status = "disabled";
1333 1333
1334 port@0 { 1334 port@0 {
1335 reg = <0>; 1335 reg = <0>;
1336 1336
1337 ldb2_lvds1: endpoint { 1337 ldb2_lvds1: endpoint {
1338 remote-endpoint = <&dpu2_disp1_lvds1>; 1338 remote-endpoint = <&dpu2_disp1_lvds1>;
1339 }; 1339 };
1340 }; 1340 };
1341 }; 1341 };
1342 }; 1342 };
1343 1343
1344 lvds1_pwm: pwm@57244000 { 1344 lvds1_pwm: pwm@57244000 {
1345 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; 1345 compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
1346 reg = <0x0 0x57244000 0 0x1000>; 1346 reg = <0x0 0x57244000 0 0x1000>;
1347 clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>, 1347 clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>,
1348 <&clk IMX8QM_LVDS1_PWM0_CLK>; 1348 <&clk IMX8QM_LVDS1_PWM0_CLK>;
1349 clock-names = "ipg", "per"; 1349 clock-names = "ipg", "per";
1350 assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>; 1350 assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>;
1351 assigned-clock-rates = <24000000>; 1351 assigned-clock-rates = <24000000>;
1352 #pwm-cells = <2>; 1352 #pwm-cells = <2>;
1353 power-domains = <&pd_lvds1_pwm>; 1353 power-domains = <&pd_lvds1_pwm>;
1354 status = "disabled"; 1354 status = "disabled";
1355 }; 1355 };
1356 1356
1357 camera: camera { 1357 camera: camera {
1358 compatible = "fsl,mxc-md", "simple-bus"; 1358 compatible = "fsl,mxc-md", "simple-bus";
1359 #address-cells = <2>; 1359 #address-cells = <2>;
1360 #size-cells = <2>; 1360 #size-cells = <2>;
1361 ranges; 1361 ranges;
1362 1362
1363 isi_0: isi@58100000 { 1363 isi_0: isi@58100000 {
1364 compatible = "fsl,imx8-isi"; 1364 compatible = "fsl,imx8-isi";
1365 reg = <0x0 0x58100000 0x0 0x10000>; 1365 reg = <0x0 0x58100000 0x0 0x10000>;
1366 interrupts = <0 297 0>; 1366 interrupts = <0 297 0>;
1367 interface = <2 0 2>; /* <Input MIPI_VCx Output> 1367 interface = <2 0 2>; /* <Input MIPI_VCx Output>
1368 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM 1368 Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM
1369 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only 1369 VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
1370 Output: 0-DC0, 1-DC1, 2-MEM */ 1370 Output: 0-DC0, 1-DC1, 2-MEM */
1371 clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; 1371 clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
1372 clock-names = "per"; 1372 clock-names = "per";
1373 assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; 1373 assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>;
1374 assigned-clock-rates = <600000000>; 1374 assigned-clock-rates = <600000000>;
1375 power-domains =<&pd_isi_ch0>; 1375 power-domains =<&pd_isi_ch0>;
1376 status = "disabled"; 1376 status = "disabled";
1377 }; 1377 };
1378 1378
1379 hdmi_rx: hdmi_rx@58268000 { 1379 hdmi_rx: hdmi_rx@58268000 {
1380 compatible = "fsl,imx-hdmi-rx"; 1380 compatible = "fsl,imx-hdmi-rx";
1381 reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */ 1381 reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */
1382 <0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR */ 1382 <0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR */
1383 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 1383 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
1384 <13 IRQ_TYPE_LEVEL_HIGH>; 1384 <13 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "plug_in", "plug_out"; 1385 interrupt-names = "plug_in", "plug_out";
1386 1386
1387 interrupt-parent = <&irqsteer_hdmi_rx>; 1387 interrupt-parent = <&irqsteer_hdmi_rx>;
1388 clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>, 1388 clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>,
1389 <&clk IMX8QM_HDMI_RX_HD_CORE_CLK>, 1389 <&clk IMX8QM_HDMI_RX_HD_CORE_CLK>,
1390 <&clk IMX8QM_HDMI_RX_PXL_CLK>, 1390 <&clk IMX8QM_HDMI_RX_PXL_CLK>,
1391 <&clk IMX8QM_HDMI_RX_SINK_PCLK>, 1391 <&clk IMX8QM_HDMI_RX_SINK_PCLK>,
1392 <&clk IMX8QM_HDMI_RX_SINK_SCLK>, 1392 <&clk IMX8QM_HDMI_RX_SINK_SCLK>,
1393 <&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>, 1393 <&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>,
1394 <&clk IMX8QM_HDMI_RX_I2S_CLK>, 1394 <&clk IMX8QM_HDMI_RX_I2S_CLK>,
1395 <&clk IMX8QM_HDMI_RX_SPDIF_CLK>, 1395 <&clk IMX8QM_HDMI_RX_SPDIF_CLK>,
1396 <&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>; 1396 <&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>;
1397 clock-names = "ref_clk", "core_clk", "pxl_clk", 1397 clock-names = "ref_clk", "core_clk", "pxl_clk",
1398 "pclk", "sclk", "enc_clk", 1398 "pclk", "sclk", "enc_clk",
1399 "i2s_clk", "spdif_clk", 1399 "i2s_clk", "spdif_clk",
1400 "pxl_link_clk"; 1400 "pxl_link_clk";
1401 power-domains = <&pd_hdmi_rx_bypass>; 1401 power-domains = <&pd_hdmi_rx_bypass>;
1402 status = "disabled"; 1402 status = "disabled";
1403 }; 1403 };
1404 }; 1404 };
1405 1405
1406 i2c0: i2c@5a800000 { 1406 i2c0: i2c@5a800000 {
1407 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1407 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1408 reg = <0x0 0x5a800000 0x0 0x4000>; 1408 reg = <0x0 0x5a800000 0x0 0x4000>;
1409 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1409 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1410 interrupt-parent = <&gic>; 1410 interrupt-parent = <&gic>;
1411 clocks = <&clk IMX8QM_I2C0_CLK>, 1411 clocks = <&clk IMX8QM_I2C0_CLK>,
1412 <&clk IMX8QM_I2C0_IPG_CLK>; 1412 <&clk IMX8QM_I2C0_IPG_CLK>;
1413 clock-names = "per", "ipg"; 1413 clock-names = "per", "ipg";
1414 assigned-clocks = <&clk IMX8QM_I2C0_CLK>; 1414 assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
1415 assigned-clock-rates = <24000000>; 1415 assigned-clock-rates = <24000000>;
1416 power-domains = <&pd_dma_lpi2c0>; 1416 power-domains = <&pd_dma_lpi2c0>;
1417 status = "disabled"; 1417 status = "disabled";
1418 }; 1418 };
1419 1419
1420 i2c1: i2c@5a810000 { 1420 i2c1: i2c@5a810000 {
1421 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1421 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1422 reg = <0x0 0x5a810000 0x0 0x4000>; 1422 reg = <0x0 0x5a810000 0x0 0x4000>;
1423 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1424 interrupt-parent = <&gic>; 1424 interrupt-parent = <&gic>;
1425 clocks = <&clk IMX8QM_I2C1_CLK>, 1425 clocks = <&clk IMX8QM_I2C1_CLK>,
1426 <&clk IMX8QM_I2C1_IPG_CLK>; 1426 <&clk IMX8QM_I2C1_IPG_CLK>;
1427 clock-names = "per", "ipg"; 1427 clock-names = "per", "ipg";
1428 assigned-clocks = <&clk IMX8QM_I2C1_CLK>; 1428 assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
1429 assigned-clock-rates = <24000000>; 1429 assigned-clock-rates = <24000000>;
1430 power-domains = <&pd_dma_lpi2c1>; 1430 power-domains = <&pd_dma_lpi2c1>;
1431 status = "disabled"; 1431 status = "disabled";
1432 }; 1432 };
1433 1433
1434 i2c2: i2c@5a820000 { 1434 i2c2: i2c@5a820000 {
1435 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1435 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1436 reg = <0x0 0x5a820000 0x0 0x4000>; 1436 reg = <0x0 0x5a820000 0x0 0x4000>;
1437 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1437 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1438 interrupt-parent = <&gic>; 1438 interrupt-parent = <&gic>;
1439 clocks = <&clk IMX8QM_I2C2_CLK>, 1439 clocks = <&clk IMX8QM_I2C2_CLK>,
1440 <&clk IMX8QM_I2C2_IPG_CLK>; 1440 <&clk IMX8QM_I2C2_IPG_CLK>;
1441 clock-names = "per", "ipg"; 1441 clock-names = "per", "ipg";
1442 assigned-clocks = <&clk IMX8QM_I2C2_CLK>; 1442 assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
1443 assigned-clock-rates = <24000000>; 1443 assigned-clock-rates = <24000000>;
1444 power-domains = <&pd_dma_lpi2c2>; 1444 power-domains = <&pd_dma_lpi2c2>;
1445 status = "disabled"; 1445 status = "disabled";
1446 }; 1446 };
1447 1447
1448 i2c3: i2c@5a830000 { 1448 i2c3: i2c@5a830000 {
1449 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1449 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1450 reg = <0x0 0x5a830000 0x0 0x4000>; 1450 reg = <0x0 0x5a830000 0x0 0x4000>;
1451 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1451 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-parent = <&gic>; 1452 interrupt-parent = <&gic>;
1453 clocks = <&clk IMX8QM_I2C3_CLK>, 1453 clocks = <&clk IMX8QM_I2C3_CLK>,
1454 <&clk IMX8QM_I2C3_IPG_CLK>; 1454 <&clk IMX8QM_I2C3_IPG_CLK>;
1455 clock-names = "per", "ipg"; 1455 clock-names = "per", "ipg";
1456 assigned-clocks = <&clk IMX8QM_I2C3_CLK>; 1456 assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
1457 assigned-clock-rates = <24000000>; 1457 assigned-clock-rates = <24000000>;
1458 power-domains = <&pd_dma_lpi2c3>; 1458 power-domains = <&pd_dma_lpi2c3>;
1459 status = "disabled"; 1459 status = "disabled";
1460 }; 1460 };
1461 1461
1462 i2c4: i2c@5a840000 { 1462 i2c4: i2c@5a840000 {
1463 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; 1463 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
1464 reg = <0x0 0x5a840000 0x0 0x4000>; 1464 reg = <0x0 0x5a840000 0x0 0x4000>;
1465 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1465 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
1466 interrupt-parent = <&gic>; 1466 interrupt-parent = <&gic>;
1467 clocks = <&clk IMX8QM_I2C4_CLK>, 1467 clocks = <&clk IMX8QM_I2C4_CLK>,
1468 <&clk IMX8QM_I2C4_IPG_CLK>; 1468 <&clk IMX8QM_I2C4_IPG_CLK>;
1469 clock-names = "per", "ipg"; 1469 clock-names = "per", "ipg";
1470 assigned-clocks = <&clk IMX8QM_I2C4_CLK>; 1470 assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
1471 assigned-clock-rates = <24000000>; 1471 assigned-clock-rates = <24000000>;
1472 power-domains = <&pd_dma_lpi2c4>; 1472 power-domains = <&pd_dma_lpi2c4>;
1473 status = "disabled"; 1473 status = "disabled";
1474 }; 1474 };
1475 1475
1476 irqsteer_hdmi: irqsteer@56260000 { 1476 irqsteer_hdmi: irqsteer@56260000 {
1477 compatible = "nxp,imx-irqsteer"; 1477 compatible = "nxp,imx-irqsteer";
1478 reg = <0x0 0x56260000 0x0 0x1000>; 1478 reg = <0x0 0x56260000 0x0 0x1000>;
1479 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1479 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1480 interrupt-controller; 1480 interrupt-controller;
1481 interrupt-parent = <&gic>; 1481 interrupt-parent = <&gic>;
1482 #interrupt-cells = <2>; 1482 #interrupt-cells = <2>;
1483 clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>; 1483 clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
1484 clock-names = "ipg"; 1484 clock-names = "ipg";
1485 assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, 1485 assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>,
1486 <&clk IMX8QM_HDMI_LIS_IPG_CLK>; 1486 <&clk IMX8QM_HDMI_LIS_IPG_CLK>;
1487 assigned-clock-rates = <675000000>, <84375000>; 1487 assigned-clock-rates = <675000000>, <84375000>;
1488 power-domains = <&pd_hdmi>; 1488 power-domains = <&pd_hdmi>;
1489 status = "disabled"; 1489 status = "disabled";
1490 }; 1490 };
1491 1491
1492 irqsteer_hdmi_rx: irqsteer@58260000 { 1492 irqsteer_hdmi_rx: irqsteer@58260000 {
1493 compatible = "nxp,imx-irqsteer"; 1493 compatible = "nxp,imx-irqsteer";
1494 reg = <0x0 0x58260000 0x0 0x1000>; 1494 reg = <0x0 0x58260000 0x0 0x1000>;
1495 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 1495 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
1496 interrupt-controller; 1496 interrupt-controller;
1497 #interrupt-cells = <2>; 1497 #interrupt-cells = <2>;
1498 clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>; 1498 clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>;
1499 clock-names = "ipg"; 1499 clock-names = "ipg";
1500 power-domains = <&pd_hdmi_rx>; 1500 power-domains = <&pd_hdmi_rx>;
1501 }; 1501 };
1502 1502
1503 1503
1504 i2c0_hdmi: i2c@56266000 { 1504 i2c0_hdmi: i2c@56266000 {
1505 compatible = "fsl,imx8qm-lpi2c"; 1505 compatible = "fsl,imx8qm-lpi2c";
1506 reg = <0x0 0x56266000 0x0 0x1000>; 1506 reg = <0x0 0x56266000 0x0 0x1000>;
1507 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 1507 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
1508 interrupt-parent = <&irqsteer_hdmi>; 1508 interrupt-parent = <&irqsteer_hdmi>;
1509 clocks = <&clk IMX8QM_HDMI_I2C0_CLK>, 1509 clocks = <&clk IMX8QM_HDMI_I2C0_CLK>,
1510 <&clk IMX8QM_HDMI_I2C_IPG_CLK>; 1510 <&clk IMX8QM_HDMI_I2C_IPG_CLK>;
1511 clock-names = "per", "ipg"; 1511 clock-names = "per", "ipg";
1512 assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; 1512 assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>;
1513 assigned-clock-rates = <24000000>; 1513 assigned-clock-rates = <24000000>;
1514 power-domains = <&pd_hdmi_i2c0>; 1514 power-domains = <&pd_hdmi_i2c0>;
1515 status = "disabled"; 1515 status = "disabled";
1516 }; 1516 };
1517 1517
1518 irqsteer_lvds0: irqsteer@562400000 { 1518 irqsteer_lvds0: irqsteer@562400000 {
1519 compatible = "nxp,imx-irqsteer"; 1519 compatible = "nxp,imx-irqsteer";
1520 reg = <0x0 0x56240000 0x0 0x1000>; 1520 reg = <0x0 0x56240000 0x0 0x1000>;
1521 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1522 interrupt-controller; 1522 interrupt-controller;
1523 interrupt-parent = <&gic>; 1523 interrupt-parent = <&gic>;
1524 #interrupt-cells = <2>; 1524 #interrupt-cells = <2>;
1525 clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>; 1525 clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>;
1526 clock-names = "ipg"; 1526 clock-names = "ipg";
1527 power-domains = <&pd_lvds0>; 1527 power-domains = <&pd_lvds0>;
1528 }; 1528 };
1529 1529
1530 1530
1531 i2c1_lvds0: i2c@56247000 { 1531 i2c1_lvds0: i2c@56247000 {
1532 compatible = "fsl,imx8qm-lpi2c"; 1532 compatible = "fsl,imx8qm-lpi2c";
1533 reg = <0x0 0x56247000 0x0 0x1000>; 1533 reg = <0x0 0x56247000 0x0 0x1000>;
1534 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1534 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1535 interrupt-parent = <&irqsteer_lvds0>; 1535 interrupt-parent = <&irqsteer_lvds0>;
1536 clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>, 1536 clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>,
1537 <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>; 1537 <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>;
1538 clock-names = "per", "ipg"; 1538 clock-names = "per", "ipg";
1539 assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; 1539 assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>;
1540 assigned-clock-rates = <24000000>; 1540 assigned-clock-rates = <24000000>;
1541 power-domains = <&pd_lvds0_i2c0>; 1541 power-domains = <&pd_lvds0_i2c0>;
1542 status = "disabled"; 1542 status = "disabled";
1543 }; 1543 };
1544 1544
1545 irqsteer_lvds1: irqsteer@572400000 { 1545 irqsteer_lvds1: irqsteer@572400000 {
1546 compatible = "nxp,imx-irqsteer"; 1546 compatible = "nxp,imx-irqsteer";
1547 reg = <0x0 0x57240000 0x0 0x1000>; 1547 reg = <0x0 0x57240000 0x0 0x1000>;
1548 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1548 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1549 interrupt-controller; 1549 interrupt-controller;
1550 interrupt-parent = <&gic>; 1550 interrupt-parent = <&gic>;
1551 #interrupt-cells = <2>; 1551 #interrupt-cells = <2>;
1552 clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>; 1552 clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>;
1553 clock-names = "ipg"; 1553 clock-names = "ipg";
1554 power-domains = <&pd_lvds1>; 1554 power-domains = <&pd_lvds1>;
1555 }; 1555 };
1556 1556
1557 i2c1_lvds1: i2c@57247000 { 1557 i2c1_lvds1: i2c@57247000 {
1558 compatible = "fsl,imx8qm-lpi2c"; 1558 compatible = "fsl,imx8qm-lpi2c";
1559 reg = <0x0 0x57247000 0x0 0x1000>; 1559 reg = <0x0 0x57247000 0x0 0x1000>;
1560 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 1560 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
1561 interrupt-parent = <&irqsteer_lvds1>; 1561 interrupt-parent = <&irqsteer_lvds1>;
1562 clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, 1562 clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>,
1563 <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; 1563 <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>;
1564 clock-names = "per", "ipg"; 1564 clock-names = "per", "ipg";
1565 assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; 1565 assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>;
1566 assigned-clock-rates = <24000000>; 1566 assigned-clock-rates = <24000000>;
1567 power-domains = <&pd_lvds1_i2c0>; 1567 power-domains = <&pd_lvds1_i2c0>;
1568 status = "disabled"; 1568 status = "disabled";
1569 }; 1569 };
1570 1570
1571 lpspi0: lpspi@5a000000 { 1571 lpspi0: lpspi@5a000000 {
1572 compatible = "fsl,imx7ulp-spi"; 1572 compatible = "fsl,imx7ulp-spi";
1573 reg = <0x0 0x5a000000 0x0 0x10000>; 1573 reg = <0x0 0x5a000000 0x0 0x10000>;
1574 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1574 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1575 interrupt-parent = <&gic>; 1575 interrupt-parent = <&gic>;
1576 clocks = <&clk IMX8QM_SPI0_CLK>, 1576 clocks = <&clk IMX8QM_SPI0_CLK>,
1577 <&clk IMX8QM_SPI0_IPG_CLK>; 1577 <&clk IMX8QM_SPI0_IPG_CLK>;
1578 clock-names = "per", "ipg"; 1578 clock-names = "per", "ipg";
1579 assigned-clocks = <&clk IMX8QM_SPI0_CLK>; 1579 assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
1580 assigned-clock-rates = <20000000>; 1580 assigned-clock-rates = <20000000>;
1581 power-domains = <&pd_dma0_chan1>; 1581 power-domains = <&pd_dma0_chan1>;
1582 dma-names = "tx","rx"; 1582 dma-names = "tx","rx";
1583 dmas = <&edma0 1 0 0>, <&edma0 0 0 1>; 1583 dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
1584 status = "disabled"; 1584 status = "disabled";
1585 }; 1585 };
1586 1586
1587 lpspi3: lpspi@5a030000 { 1587 lpspi3: lpspi@5a030000 {
1588 compatible = "fsl,imx7ulp-spi"; 1588 compatible = "fsl,imx7ulp-spi";
1589 reg = <0x0 0x5a030000 0x0 0x10000>; 1589 reg = <0x0 0x5a030000 0x0 0x10000>;
1590 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 1590 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
1591 interrupt-parent = <&gic>; 1591 interrupt-parent = <&gic>;
1592 clocks = <&clk IMX8QM_SPI3_CLK>, 1592 clocks = <&clk IMX8QM_SPI3_CLK>,
1593 <&clk IMX8QM_SPI3_IPG_CLK>; 1593 <&clk IMX8QM_SPI3_IPG_CLK>;
1594 clock-names = "per", "ipg"; 1594 clock-names = "per", "ipg";
1595 assigned-clocks = <&clk IMX8QM_SPI3_CLK>; 1595 assigned-clocks = <&clk IMX8QM_SPI3_CLK>;
1596 assigned-clock-rates = <60000000>; 1596 assigned-clock-rates = <60000000>;
1597 power-domains = <&pd_dma0_chan7>; 1597 power-domains = <&pd_dma0_chan7>;
1598 dma-names = "tx","rx"; 1598 dma-names = "tx","rx";
1599 dmas = <&edma0 7 0 0>, <&edma0 6 0 1>; 1599 dmas = <&edma0 7 0 0>, <&edma0 6 0 1>;
1600 status = "disabled"; 1600 status = "disabled";
1601 }; 1601 };
1602 1602
1603 lpuart0: serial@5a060000 { 1603 lpuart0: serial@5a060000 {
1604 compatible = "fsl,imx8qm-lpuart"; 1604 compatible = "fsl,imx8qm-lpuart";
1605 reg = <0x0 0x5a060000 0x0 0x1000>; 1605 reg = <0x0 0x5a060000 0x0 0x1000>;
1606 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1606 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1607 interrupt-parent = <&wu>; 1607 interrupt-parent = <&wu>;
1608 clocks = <&clk IMX8QM_UART0_CLK>, 1608 clocks = <&clk IMX8QM_UART0_CLK>,
1609 <&clk IMX8QM_UART0_IPG_CLK>; 1609 <&clk IMX8QM_UART0_IPG_CLK>;
1610 clock-names = "per", "ipg"; 1610 clock-names = "per", "ipg";
1611 assigned-clocks = <&clk IMX8QM_UART0_CLK>; 1611 assigned-clocks = <&clk IMX8QM_UART0_CLK>;
1612 assigned-clock-rates = <80000000>; 1612 assigned-clock-rates = <80000000>;
1613 power-domains = <&pd_dma_lpuart0>; 1613 power-domains = <&pd_dma_lpuart0>;
1614 status = "disabled"; 1614 status = "disabled";
1615 }; 1615 };
1616 1616
1617 lpuart1: serial@5a070000 { 1617 lpuart1: serial@5a070000 {
1618 compatible = "fsl,imx8qm-lpuart"; 1618 compatible = "fsl,imx8qm-lpuart";
1619 reg = <0x0 0x5a070000 0x0 0x1000>; 1619 reg = <0x0 0x5a070000 0x0 0x1000>;
1620 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 1620 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1621 interrupt-parent = <&wu>; 1621 interrupt-parent = <&wu>;
1622 clocks = <&clk IMX8QM_UART1_CLK>, 1622 clocks = <&clk IMX8QM_UART1_CLK>,
1623 <&clk IMX8QM_UART1_IPG_CLK>; 1623 <&clk IMX8QM_UART1_IPG_CLK>;
1624 clock-names = "per", "ipg"; 1624 clock-names = "per", "ipg";
1625 assigned-clocks = <&clk IMX8QM_UART1_CLK>; 1625 assigned-clocks = <&clk IMX8QM_UART1_CLK>;
1626 assigned-clock-rates = <80000000>; 1626 assigned-clock-rates = <80000000>;
1627 power-domains = <&pd_dma0_chan15>; 1627 power-domains = <&pd_dma0_chan15>;
1628 dma-names = "tx","rx"; 1628 dma-names = "tx","rx";
1629 dmas = <&edma0 15 0 0>, 1629 dmas = <&edma0 15 0 0>,
1630 <&edma0 14 0 1>; 1630 <&edma0 14 0 1>;
1631 status = "disabled"; 1631 status = "disabled";
1632 }; 1632 };
1633 1633
1634 lpuart2: serial@5a080000 { 1634 lpuart2: serial@5a080000 {
1635 compatible = "fsl,imx8qm-lpuart"; 1635 compatible = "fsl,imx8qm-lpuart";
1636 reg = <0x0 0x5a080000 0x0 0x1000>; 1636 reg = <0x0 0x5a080000 0x0 0x1000>;
1637 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1637 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
1638 interrupt-parent = <&wu>; 1638 interrupt-parent = <&wu>;
1639 clocks = <&clk IMX8QM_UART2_CLK>, 1639 clocks = <&clk IMX8QM_UART2_CLK>,
1640 <&clk IMX8QM_UART2_IPG_CLK>; 1640 <&clk IMX8QM_UART2_IPG_CLK>;
1641 clock-names = "per", "ipg"; 1641 clock-names = "per", "ipg";
1642 assigned-clocks = <&clk IMX8QM_UART2_CLK>; 1642 assigned-clocks = <&clk IMX8QM_UART2_CLK>;
1643 assigned-clock-rates = <80000000>; 1643 assigned-clock-rates = <80000000>;
1644 power-domains = <&pd_dma0_chan17>; 1644 power-domains = <&pd_dma0_chan17>;
1645 dma-names = "tx","rx"; 1645 dma-names = "tx","rx";
1646 dmas = <&edma0 17 0 0>, 1646 dmas = <&edma0 17 0 0>,
1647 <&edma0 16 0 1>; 1647 <&edma0 16 0 1>;
1648 status = "disabled"; 1648 status = "disabled";
1649 }; 1649 };
1650 1650
1651 lpuart3: serial@5a090000 { 1651 lpuart3: serial@5a090000 {
1652 compatible = "fsl,imx8qm-lpuart"; 1652 compatible = "fsl,imx8qm-lpuart";
1653 reg = <0x0 0x5a090000 0x0 0x1000>; 1653 reg = <0x0 0x5a090000 0x0 0x1000>;
1654 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
1655 interrupt-parent = <&wu>; 1655 interrupt-parent = <&wu>;
1656 clocks = <&clk IMX8QM_UART3_CLK>, 1656 clocks = <&clk IMX8QM_UART3_CLK>,
1657 <&clk IMX8QM_UART3_IPG_CLK>; 1657 <&clk IMX8QM_UART3_IPG_CLK>;
1658 clock-names = "per", "ipg"; 1658 clock-names = "per", "ipg";
1659 assigned-clocks = <&clk IMX8QM_UART3_CLK>; 1659 assigned-clocks = <&clk IMX8QM_UART3_CLK>;
1660 assigned-clock-rates = <80000000>; 1660 assigned-clock-rates = <80000000>;
1661 power-domains = <&pd_dma0_chan19>; 1661 power-domains = <&pd_dma0_chan19>;
1662 dma-names = "tx","rx"; 1662 dma-names = "tx","rx";
1663 dmas = <&edma0 19 0 0>, 1663 dmas = <&edma0 19 0 0>,
1664 <&edma0 18 0 1>; 1664 <&edma0 18 0 1>;
1665 status = "disabled"; 1665 status = "disabled";
1666 }; 1666 };
1667 1667
1668 lpuart4: serial@5a0a0000 { 1668 lpuart4: serial@5a0a0000 {
1669 compatible = "fsl,imx8qm-lpuart"; 1669 compatible = "fsl,imx8qm-lpuart";
1670 reg = <0x0 0x5a0a0000 0x0 0x1000>; 1670 reg = <0x0 0x5a0a0000 0x0 0x1000>;
1671 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1671 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
1672 interrupt-parent = <&wu>; 1672 interrupt-parent = <&wu>;
1673 clocks = <&clk IMX8QM_UART4_CLK>, 1673 clocks = <&clk IMX8QM_UART4_CLK>,
1674 <&clk IMX8QM_UART4_IPG_CLK>; 1674 <&clk IMX8QM_UART4_IPG_CLK>;
1675 clock-names = "per", "ipg"; 1675 clock-names = "per", "ipg";
1676 assigned-clocks = <&clk IMX8QM_UART4_CLK>; 1676 assigned-clocks = <&clk IMX8QM_UART4_CLK>;
1677 assigned-clock-rates = <80000000>; 1677 assigned-clock-rates = <80000000>;
1678 power-domains = <&pd_dma0_chan21>; 1678 power-domains = <&pd_dma0_chan21>;
1679 dma-names = "tx","rx"; 1679 dma-names = "tx","rx";
1680 dmas = <&edma0 21 0 0>, 1680 dmas = <&edma0 21 0 0>,
1681 <&edma0 20 0 1>; 1681 <&edma0 20 0 1>;
1682 status = "disabled"; 1682 status = "disabled";
1683 }; 1683 };
1684 1684
1685 edma0: dma-controller@5a1f0000 { 1685 edma0: dma-controller@5a1f0000 {
1686 compatible = "fsl,imx8qm-edma"; 1686 compatible = "fsl,imx8qm-edma";
1687 reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ 1687 reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
1688 <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ 1688 <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */
1689 <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ 1689 <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
1690 <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ 1690 <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */
1691 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ 1691 <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
1692 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ 1692 <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
1693 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ 1693 <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
1694 <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ 1694 <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */
1695 <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ 1695 <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
1696 <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */ 1696 <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */
1697 <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ 1697 <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
1698 <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */ 1698 <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */
1699 <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ 1699 <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
1700 <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ 1700 <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
1701 #dma-cells = <3>; 1701 #dma-cells = <3>;
1702 dma-channels = <14>; 1702 dma-channels = <14>;
1703 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1703 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1704 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1705 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1706 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 1708 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 1709 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 1710 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 1711 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
1716 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; 1716 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1717 interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", 1717 interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
1718 "edma0-chan6-rx", "edma0-chan7-tx", 1718 "edma0-chan6-rx", "edma0-chan7-tx",
1719 "edma0-chan12-rx", "edma0-chan13-tx", 1719 "edma0-chan12-rx", "edma0-chan13-tx",
1720 "edma0-chan14-rx", "edma0-chan15-tx", 1720 "edma0-chan14-rx", "edma0-chan15-tx",
1721 "edma0-chan16-rx", "edma0-chan17-tx", 1721 "edma0-chan16-rx", "edma0-chan17-tx",
1722 "edma0-chan18-rx", "edma0-chan19-tx", 1722 "edma0-chan18-rx", "edma0-chan19-tx",
1723 "edma0-chan20-rx", "edma0-chan21-tx"; 1723 "edma0-chan20-rx", "edma0-chan21-tx";
1724 status = "okay"; 1724 status = "okay";
1725 }; 1725 };
1726 1726
1727 edma2: dma-controller@591F0000 { 1727 edma2: dma-controller@591F0000 {
1728 compatible = "fsl,imx8qm-adma"; 1728 compatible = "fsl,imx8qm-adma";
1729 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ 1729 reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
1730 <0x0 0x59210000 0x0 0x10000>, 1730 <0x0 0x59210000 0x0 0x10000>,
1731 <0x0 0x59220000 0x0 0x10000>, 1731 <0x0 0x59220000 0x0 0x10000>,
1732 <0x0 0x59230000 0x0 0x10000>, 1732 <0x0 0x59230000 0x0 0x10000>,
1733 <0x0 0x59240000 0x0 0x10000>, 1733 <0x0 0x59240000 0x0 0x10000>,
1734 <0x0 0x59250000 0x0 0x10000>, 1734 <0x0 0x59250000 0x0 0x10000>,
1735 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ 1735 <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
1736 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ 1736 <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */
1737 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ 1737 <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
1738 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ 1738 <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
1739 <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */ 1739 <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */
1740 <0x0 0x592B0000 0x0 0x10000>, /* spdif1 tx */ 1740 <0x0 0x592B0000 0x0 0x10000>, /* spdif1 tx */
1741 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ 1741 <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
1742 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ 1742 <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
1743 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ 1743 <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
1744 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ 1744 <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
1745 <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */ 1745 <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */
1746 <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */ 1746 <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */
1747 #dma-cells = <3>; 1747 #dma-cells = <3>;
1748 shared-interrupt; 1748 shared-interrupt;
1749 dma-channels = <18>; 1749 dma-channels = <18>;
1750 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ 1750 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
1751 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
1752 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ 1756 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
1757 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 1758 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
1759 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */ 1760 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
1761 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 1762 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
1763 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 1764 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
1765 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 1766 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
1767 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 1767 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
1768 interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ 1768 interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
1769 "edma2-chan2-rx", "edma2-chan3-tx", 1769 "edma2-chan2-rx", "edma2-chan3-tx",
1770 "edma2-chan4-tx", "edma2-chan5-tx", 1770 "edma2-chan4-tx", "edma2-chan5-tx",
1771 "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ 1771 "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */
1772 "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ 1772 "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */
1773 "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ 1773 "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */
1774 "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ 1774 "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
1775 "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ 1775 "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
1776 "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ 1776 "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */
1777 status = "okay"; 1777 status = "okay";
1778 }; 1778 };
1779 1779
1780 edma3: dma-controller@599F0000 { 1780 edma3: dma-controller@599F0000 {
1781 compatible = "fsl,imx8qm-adma"; 1781 compatible = "fsl,imx8qm-adma";
1782 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ 1782 reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */
1783 <0x0 0x59A10000 0x0 0x10000>, 1783 <0x0 0x59A10000 0x0 0x10000>,
1784 <0x0 0x59A20000 0x0 0x10000>, 1784 <0x0 0x59A20000 0x0 0x10000>,
1785 <0x0 0x59A30000 0x0 0x10000>, 1785 <0x0 0x59A30000 0x0 0x10000>,
1786 <0x0 0x59A40000 0x0 0x10000>, 1786 <0x0 0x59A40000 0x0 0x10000>,
1787 <0x0 0x59A50000 0x0 0x10000>, 1787 <0x0 0x59A50000 0x0 0x10000>,
1788 <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */ 1788 <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */
1789 <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */ 1789 <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */
1790 <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */ 1790 <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */
1791 #dma-cells = <3>; 1791 #dma-cells = <3>;
1792 shared-interrupt; 1792 shared-interrupt;
1793 dma-channels = <9>; 1793 dma-channels = <9>;
1794 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ 1794 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */
1795 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ 1800 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */
1801 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ 1802 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */
1803 interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ 1803 interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */
1804 "edma3-chan2-rx", "edma3-chan3-tx", 1804 "edma3-chan2-rx", "edma3-chan3-tx",
1805 "edma3-chan4-tx", "edma3-chan5-tx", 1805 "edma3-chan4-tx", "edma3-chan5-tx",
1806 "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ 1806 "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */
1807 "edma3-chan10-tx"; /* sai7 */ 1807 "edma3-chan10-tx"; /* sai7 */
1808 status = "okay"; 1808 status = "okay";
1809 }; 1809 };
1810 1810
1811 wu: wu { 1811 wu: wu {
1812 compatible = "fsl,imx8-wu"; 1812 compatible = "fsl,imx8-wu";
1813 interrupt-controller; 1813 interrupt-controller;
1814 #interrupt-cells = <3>; 1814 #interrupt-cells = <3>;
1815 interrupt-parent = <&gic>; 1815 interrupt-parent = <&gic>;
1816 }; 1816 };
1817 1817
1818 gpio0: gpio@5d080000 { 1818 gpio0: gpio@5d080000 {
1819 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1819 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1820 reg = <0x0 0x5d080000 0x0 0x10000>; 1820 reg = <0x0 0x5d080000 0x0 0x10000>;
1821 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1821 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1822 gpio-controller; 1822 gpio-controller;
1823 #gpio-cells = <2>; 1823 #gpio-cells = <2>;
1824 power-domains = <&pd_lsio_gpio0>; 1824 power-domains = <&pd_lsio_gpio0>;
1825 interrupt-controller; 1825 interrupt-controller;
1826 #interrupt-cells = <2>; 1826 #interrupt-cells = <2>;
1827 }; 1827 };
1828 1828
1829 gpio1: gpio@5d090000 { 1829 gpio1: gpio@5d090000 {
1830 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1830 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1831 reg = <0x0 0x5d090000 0x0 0x10000>; 1831 reg = <0x0 0x5d090000 0x0 0x10000>;
1832 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1832 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1833 gpio-controller; 1833 gpio-controller;
1834 #gpio-cells = <2>; 1834 #gpio-cells = <2>;
1835 power-domains = <&pd_lsio_gpio1>; 1835 power-domains = <&pd_lsio_gpio1>;
1836 interrupt-controller; 1836 interrupt-controller;
1837 #interrupt-cells = <2>; 1837 #interrupt-cells = <2>;
1838 }; 1838 };
1839 1839
1840 gpio2: gpio@5d0a0000 { 1840 gpio2: gpio@5d0a0000 {
1841 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1841 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1842 reg = <0x0 0x5d0a0000 0x0 0x10000>; 1842 reg = <0x0 0x5d0a0000 0x0 0x10000>;
1843 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1843 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
1844 gpio-controller; 1844 gpio-controller;
1845 #gpio-cells = <2>; 1845 #gpio-cells = <2>;
1846 power-domains = <&pd_lsio_gpio2>; 1846 power-domains = <&pd_lsio_gpio2>;
1847 interrupt-controller; 1847 interrupt-controller;
1848 #interrupt-cells = <2>; 1848 #interrupt-cells = <2>;
1849 }; 1849 };
1850 1850
1851 gpio3: gpio@5d0b0000 { 1851 gpio3: gpio@5d0b0000 {
1852 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1852 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1853 reg = <0x0 0x5d0b0000 0x0 0x10000>; 1853 reg = <0x0 0x5d0b0000 0x0 0x10000>;
1854 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1854 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1855 gpio-controller; 1855 gpio-controller;
1856 #gpio-cells = <2>; 1856 #gpio-cells = <2>;
1857 power-domains = <&pd_lsio_gpio3>; 1857 power-domains = <&pd_lsio_gpio3>;
1858 interrupt-controller; 1858 interrupt-controller;
1859 #interrupt-cells = <2>; 1859 #interrupt-cells = <2>;
1860 }; 1860 };
1861 1861
1862 gpio4: gpio@5d0c0000 { 1862 gpio4: gpio@5d0c0000 {
1863 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1863 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1864 reg = <0x0 0x5d0c0000 0x0 0x10000>; 1864 reg = <0x0 0x5d0c0000 0x0 0x10000>;
1865 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1865 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1866 gpio-controller; 1866 gpio-controller;
1867 #gpio-cells = <2>; 1867 #gpio-cells = <2>;
1868 power-domains = <&pd_lsio_gpio4>; 1868 power-domains = <&pd_lsio_gpio4>;
1869 interrupt-controller; 1869 interrupt-controller;
1870 #interrupt-cells = <2>; 1870 #interrupt-cells = <2>;
1871 }; 1871 };
1872 1872
1873 gpio5: gpio@5d0d0000 { 1873 gpio5: gpio@5d0d0000 {
1874 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1874 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1875 reg = <0x0 0x5d0d0000 0x0 0x10000>; 1875 reg = <0x0 0x5d0d0000 0x0 0x10000>;
1876 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1876 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
1877 gpio-controller; 1877 gpio-controller;
1878 #gpio-cells = <2>; 1878 #gpio-cells = <2>;
1879 power-domains = <&pd_lsio_gpio5>; 1879 power-domains = <&pd_lsio_gpio5>;
1880 interrupt-controller; 1880 interrupt-controller;
1881 #interrupt-cells = <2>; 1881 #interrupt-cells = <2>;
1882 }; 1882 };
1883 1883
1884 gpio6: gpio@5d0e0000 { 1884 gpio6: gpio@5d0e0000 {
1885 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1885 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1886 reg = <0x0 0x5d0e0000 0x0 0x10000>; 1886 reg = <0x0 0x5d0e0000 0x0 0x10000>;
1887 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1887 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1888 gpio-controller; 1888 gpio-controller;
1889 #gpio-cells = <2>; 1889 #gpio-cells = <2>;
1890 power-domains = <&pd_lsio_gpio6>; 1890 power-domains = <&pd_lsio_gpio6>;
1891 interrupt-controller; 1891 interrupt-controller;
1892 #interrupt-cells = <2>; 1892 #interrupt-cells = <2>;
1893 }; 1893 };
1894 1894
1895 gpio7: gpio@5d0f0000 { 1895 gpio7: gpio@5d0f0000 {
1896 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; 1896 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
1897 reg = <0x0 0x5d0f0000 0x0 0x10000>; 1897 reg = <0x0 0x5d0f0000 0x0 0x10000>;
1898 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1898 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
1899 gpio-controller; 1899 gpio-controller;
1900 #gpio-cells = <2>; 1900 #gpio-cells = <2>;
1901 power-domains = <&pd_lsio_gpio7>; 1901 power-domains = <&pd_lsio_gpio7>;
1902 interrupt-controller; 1902 interrupt-controller;
1903 #interrupt-cells = <2>; 1903 #interrupt-cells = <2>;
1904 }; 1904 };
1905 1905
1906 mlb: mlb@5B060000 { 1906 mlb: mlb@5B060000 {
1907 compatible = "fsl,imx6q-mlb150"; 1907 compatible = "fsl,imx6q-mlb150";
1908 reg = <0x0 0x5B060000 0x0 0x10000>; 1908 reg = <0x0 0x5B060000 0x0 0x10000>;
1909 interrupt-parent = <&gic>; 1909 interrupt-parent = <&gic>;
1910 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, 1910 interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>,
1911 <0 266 IRQ_TYPE_LEVEL_HIGH>; 1911 <0 266 IRQ_TYPE_LEVEL_HIGH>;
1912 clocks = <&clk IMX8QM_MLB_CLK>, 1912 clocks = <&clk IMX8QM_MLB_CLK>,
1913 <&clk IMX8QM_MLB_HCLK>, 1913 <&clk IMX8QM_MLB_HCLK>,
1914 <&clk IMX8QM_MLB_IPG_CLK>; 1914 <&clk IMX8QM_MLB_IPG_CLK>;
1915 clock-names = "mlb", "hclk", "ipg"; 1915 clock-names = "mlb", "hclk", "ipg";
1916 assigned-clocks = <&clk IMX8QM_MLB_CLK>, 1916 assigned-clocks = <&clk IMX8QM_MLB_CLK>,
1917 <&clk IMX8QM_MLB_HCLK>, 1917 <&clk IMX8QM_MLB_HCLK>,
1918 <&clk IMX8QM_MLB_IPG_CLK>; 1918 <&clk IMX8QM_MLB_IPG_CLK>;
1919 assigned-clock-rates = <333333333>, <333333333>, <83333333>; 1919 assigned-clock-rates = <333333333>, <333333333>, <83333333>;
1920 power-domains = <&pd_conn_mlb0>; 1920 power-domains = <&pd_conn_mlb0>;
1921 status = "disabled"; 1921 status = "disabled";
1922 }; 1922 };
1923 1923
1924 usdhc1: usdhc@5b010000 { 1924 usdhc1: usdhc@5b010000 {
1925 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1925 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1926 interrupt-parent = <&gic>; 1926 interrupt-parent = <&gic>;
1927 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1927 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1928 reg = <0x0 0x5b010000 0x0 0x10000>; 1928 reg = <0x0 0x5b010000 0x0 0x10000>;
1929 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, 1929 clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
1930 <&clk IMX8QM_SDHC0_CLK>, 1930 <&clk IMX8QM_SDHC0_CLK>,
1931 <&clk IMX8QM_SDHC0_AHB_CLK>; 1931 <&clk IMX8QM_SDHC0_AHB_CLK>;
1932 clock-names = "ipg", "per", "ahb"; 1932 clock-names = "ipg", "per", "ahb";
1933 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; 1933 assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
1934 assigned-clock-rates = <400000000>; 1934 assigned-clock-rates = <400000000>;
1935 power-domains = <&pd_conn_sdch0>; 1935 power-domains = <&pd_conn_sdch0>;
1936 fsl,tuning-start-tap = <20>; 1936 fsl,tuning-start-tap = <20>;
1937 fsl,tuning-step= <2>; 1937 fsl,tuning-step= <2>;
1938 iommus = <&smmu 0x11 0x7f80>; 1938 iommus = <&smmu 0x11 0x7f80>;
1939 status = "disabled"; 1939 status = "disabled";
1940 }; 1940 };
1941 1941
1942 usdhc2: usdhc@5b020000 { 1942 usdhc2: usdhc@5b020000 {
1943 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1943 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1944 interrupt-parent = <&gic>; 1944 interrupt-parent = <&gic>;
1945 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1945 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1946 reg = <0x0 0x5b020000 0x0 0x10000>; 1946 reg = <0x0 0x5b020000 0x0 0x10000>;
1947 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, 1947 clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
1948 <&clk IMX8QM_SDHC1_CLK>, 1948 <&clk IMX8QM_SDHC1_CLK>,
1949 <&clk IMX8QM_SDHC1_AHB_CLK>; 1949 <&clk IMX8QM_SDHC1_AHB_CLK>;
1950 clock-names = "ipg", "per", "ahb"; 1950 clock-names = "ipg", "per", "ahb";
1951 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; 1951 assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
1952 assigned-clock-rates = <200000000>; 1952 assigned-clock-rates = <200000000>;
1953 power-domains = <&pd_conn_sdch1>; 1953 power-domains = <&pd_conn_sdch1>;
1954 fsl,tuning-start-tap = <20>; 1954 fsl,tuning-start-tap = <20>;
1955 fsl,tuning-step= <2>; 1955 fsl,tuning-step= <2>;
1956 iommus = <&smmu 0x11 0x7f80>; 1956 iommus = <&smmu 0x11 0x7f80>;
1957 status = "disabled"; 1957 status = "disabled";
1958 }; 1958 };
1959 1959
1960 usdhc3: usdhc@5b030000 { 1960 usdhc3: usdhc@5b030000 {
1961 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; 1961 compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
1962 interrupt-parent = <&gic>; 1962 interrupt-parent = <&gic>;
1963 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1963 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
1964 reg = <0x0 0x5b030000 0x0 0x10000>; 1964 reg = <0x0 0x5b030000 0x0 0x10000>;
1965 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, 1965 clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
1966 <&clk IMX8QM_SDHC2_CLK>, 1966 <&clk IMX8QM_SDHC2_CLK>,
1967 <&clk IMX8QM_SDHC2_AHB_CLK>; 1967 <&clk IMX8QM_SDHC2_AHB_CLK>;
1968 clock-names = "ipg", "per", "ahb"; 1968 clock-names = "ipg", "per", "ahb";
1969 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; 1969 assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
1970 assigned-clock-rates = <200000000>; 1970 assigned-clock-rates = <200000000>;
1971 power-domains = <&pd_conn_sdch2>; 1971 power-domains = <&pd_conn_sdch2>;
1972 iommus = <&smmu 0x11 0x7f80>; 1972 iommus = <&smmu 0x11 0x7f80>;
1973 status = "disabled"; 1973 status = "disabled";
1974 }; 1974 };
1975 1975
1976 fec1: ethernet@5b040000 { 1976 fec1: ethernet@5b040000 {
1977 compatible = "fsl,imx8qm-fec"; 1977 compatible = "fsl,imx8qm-fec";
1978 reg = <0x0 0x5b040000 0x0 0x10000>; 1978 reg = <0x0 0x5b040000 0x0 0x10000>;
1979 interrupt-parent = <&wu>; 1979 interrupt-parent = <&wu>;
1980 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 1980 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
1981 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 1983 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
1984 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>, 1984 clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>,
1985 <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>; 1985 <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>;
1986 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 1986 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
1987 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, 1987 assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
1988 <&clk IMX8QM_ENET0_REF_DIV>; 1988 <&clk IMX8QM_ENET0_REF_DIV>;
1989 assigned-clock-rates = <250000000>, <125000000>; 1989 assigned-clock-rates = <250000000>, <125000000>;
1990 fsl,num-tx-queues=<3>; 1990 fsl,num-tx-queues=<3>;
1991 fsl,num-rx-queues=<3>; 1991 fsl,num-rx-queues=<3>;
1992 fsl,wakeup_irq = <0>; 1992 fsl,wakeup_irq = <0>;
1993 power-domains = <&pd_conn_enet0>; 1993 power-domains = <&pd_conn_enet0>;
1994 iommus = <&smmu 0x12 0x7f80>; 1994 iommus = <&smmu 0x12 0x7f80>;
1995 status = "disabled"; 1995 status = "disabled";
1996 }; 1996 };
1997 1997
1998 fec2: ethernet@5b050000 { 1998 fec2: ethernet@5b050000 {
1999 compatible = "fsl,imx8qm-fec"; 1999 compatible = "fsl,imx8qm-fec";
2000 reg = <0x0 0x5b050000 0x0 0x10000>; 2000 reg = <0x0 0x5b050000 0x0 0x10000>;
2001 interrupt-parent = <&wu>; 2001 interrupt-parent = <&wu>;
2002 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2002 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 2005 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2006 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>, 2006 clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>,
2007 <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>; 2007 <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>;
2008 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; 2008 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
2009 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, 2009 assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
2010 <&clk IMX8QM_ENET1_REF_DIV>; 2010 <&clk IMX8QM_ENET1_REF_DIV>;
2011 assigned-clock-rates = <250000000>, <125000000>; 2011 assigned-clock-rates = <250000000>, <125000000>;
2012 fsl,num-tx-queues=<3>; 2012 fsl,num-tx-queues=<3>;
2013 fsl,num-rx-queues=<3>; 2013 fsl,num-rx-queues=<3>;
2014 fsl,wakeup_irq = <0>; 2014 fsl,wakeup_irq = <0>;
2015 power-domains = <&pd_conn_enet1>; 2015 power-domains = <&pd_conn_enet1>;
2016 iommus = <&smmu 0x12 0x7f80>; 2016 iommus = <&smmu 0x12 0x7f80>;
2017 status = "disabled"; 2017 status = "disabled";
2018 }; 2018 };
2019 2019
2020 usbmisc1: usbmisc@5b0d0200 { 2020 usbmisc1: usbmisc@5b0d0200 {
2021 #index-cells = <1>; 2021 #index-cells = <1>;
2022 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; 2022 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
2023 reg = <0x0 0x5b0d0200 0x0 0x200>; 2023 reg = <0x0 0x5b0d0200 0x0 0x200>;
2024 }; 2024 };
2025 2025
2026 usbmisc2: usbmisc@5b0e0200 { 2026 usbmisc2: usbmisc@5b0e0200 {
2027 #index-cells = <1>; 2027 #index-cells = <1>;
2028 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; 2028 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
2029 reg = <0x0 0x5b0e0200 0x0 0x200>; 2029 reg = <0x0 0x5b0e0200 0x0 0x200>;
2030 }; 2030 };
2031 2031
2032 usbphy1: usbphy@0x5b100000 { 2032 usbphy1: usbphy@0x5b100000 {
2033 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; 2033 compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
2034 reg = <0x0 0x5b100000 0x0 0x1000>; 2034 reg = <0x0 0x5b100000 0x0 0x1000>;
2035 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; 2035 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
2036 power-domains = <&pd_conn_usbotg0_phy>; 2036 power-domains = <&pd_conn_usbotg0_phy>;
2037 }; 2037 };
2038 2038
2039 usbphynop1: usbphynop1 { 2039 usbphynop1: usbphynop1 {
2040 compatible = "usb-nop-xceiv"; 2040 compatible = "usb-nop-xceiv";
2041 clocks = <&clk IMX8QM_USB3_PHY_CLK>; 2041 clocks = <&clk IMX8QM_USB3_PHY_CLK>;
2042 clock-names = "main_clk"; 2042 clock-names = "main_clk";
2043 power-domains = <&pd_conn_usb2_phy>; 2043 power-domains = <&pd_conn_usb2_phy>;
2044 }; 2044 };
2045 2045
2046 usbphynop2: usbphynop2 { 2046 usbphynop2: usbphynop2 {
2047 compatible = "usb-nop-xceiv"; 2047 compatible = "usb-nop-xceiv";
2048 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; 2048 clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>;
2049 clock-names = "main_clk"; 2049 clock-names = "main_clk";
2050 power-domains = <&pd_conn_usbotg0_phy>; 2050 power-domains = <&pd_conn_usbotg0_phy>;
2051 }; 2051 };
2052 2052
2053 usbotg1: usb@5b0d0000 { 2053 usbotg1: usb@5b0d0000 {
2054 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; 2054 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
2055 reg = <0x0 0x5b0d0000 0x0 0x200>; 2055 reg = <0x0 0x5b0d0000 0x0 0x200>;
2056 interrupt-parent = <&wu>; 2056 interrupt-parent = <&wu>;
2057 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
2058 fsl,usbphy = <&usbphy1>; 2058 fsl,usbphy = <&usbphy1>;
2059 fsl,usbmisc = <&usbmisc1 0>; 2059 fsl,usbmisc = <&usbmisc1 0>;
2060 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; 2060 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
2061 ahb-burst-config = <0x0>; 2061 ahb-burst-config = <0x0>;
2062 tx-burst-size-dword = <0x10>; 2062 tx-burst-size-dword = <0x10>;
2063 rx-burst-size-dword = <0x10>; 2063 rx-burst-size-dword = <0x10>;
2064 #stream-id-cells = <1>; 2064 #stream-id-cells = <1>;
2065 power-domains = <&pd_conn_usbotg0>; 2065 power-domains = <&pd_conn_usbotg0>;
2066 status = "disabled"; 2066 status = "disabled";
2067 }; 2067 };
2068 2068
2069 usbh1: usb@5b0e0000 { 2069 usbh1: usb@5b0e0000 {
2070 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; 2070 compatible = "fsl,imx8qm-usb", "fsl,imx27-usb";
2071 reg = <0x0 0x5b0e0000 0x0 0x200>; 2071 reg = <0x0 0x5b0e0000 0x0 0x200>;
2072 interrupt-parent = <&wu>; 2072 interrupt-parent = <&wu>;
2073 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 2073 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2074 phy_type = "hsic"; 2074 phy_type = "hsic";
2075 dr_mode = "host"; 2075 dr_mode = "host";
2076 fsl,usbphy = <&usbphynop2>; 2076 fsl,usbphy = <&usbphynop2>;
2077 fsl,usbmisc = <&usbmisc2 0>; 2077 fsl,usbmisc = <&usbmisc2 0>;
2078 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; 2078 clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>;
2079 ahb-burst-config = <0x0>; 2079 ahb-burst-config = <0x0>;
2080 tx-burst-size-dword = <0x10>; 2080 tx-burst-size-dword = <0x10>;
2081 rx-burst-size-dword = <0x10>; 2081 rx-burst-size-dword = <0x10>;
2082 #stream-id-cells = <1>; 2082 #stream-id-cells = <1>;
2083 power-domains = <&pd_conn_usbh1>; 2083 power-domains = <&pd_conn_usbh1>;
2084 status = "disabled"; 2084 status = "disabled";
2085 }; 2085 };
2086 2086
2087 usbotg3: usb3@5b110000 { 2087 usbotg3: usb3@5b110000 {
2088 compatible = "Cadence,usb3"; 2088 compatible = "Cadence,usb3";
2089 reg = <0x0 0x5B110000 0x0 0x10000>, 2089 reg = <0x0 0x5B110000 0x0 0x10000>,
2090 <0x0 0x5B130000 0x0 0x10000>, 2090 <0x0 0x5B130000 0x0 0x10000>,
2091 <0x0 0x5B140000 0x0 0x10000>, 2091 <0x0 0x5B140000 0x0 0x10000>,
2092 <0x0 0x5B160000 0x0 0x40000>, 2092 <0x0 0x5B160000 0x0 0x40000>,
2093 <0x0 0x5B120000 0x0 0x10000>; 2093 <0x0 0x5B120000 0x0 0x10000>;
2094 reg-names = "none-core", "xhci", "dev", "phy", "otg"; 2094 reg-names = "none-core", "xhci", "dev", "phy", "otg";
2095 interrupt-parent = <&wu>; 2095 interrupt-parent = <&wu>;
2096 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; 2096 interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
2097 clocks = <&clk IMX8QM_USB3_LPM_CLK>, 2097 clocks = <&clk IMX8QM_USB3_LPM_CLK>,
2098 <&clk IMX8QM_USB3_BUS_CLK>, 2098 <&clk IMX8QM_USB3_BUS_CLK>,
2099 <&clk IMX8QM_USB3_ACLK>, 2099 <&clk IMX8QM_USB3_ACLK>,
2100 <&clk IMX8QM_USB3_IPG_CLK>, 2100 <&clk IMX8QM_USB3_IPG_CLK>,
2101 <&clk IMX8QM_USB3_CORE_PCLK>; 2101 <&clk IMX8QM_USB3_CORE_PCLK>;
2102 clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", 2102 clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
2103 "usb3_ipg_clk", "usb3_core_pclk"; 2103 "usb3_ipg_clk", "usb3_core_pclk";
2104 assigned-clocks = <&clk IMX8QM_USB3_ACLK_DIV>, 2104 assigned-clocks = <&clk IMX8QM_USB3_ACLK_DIV>,
2105 <&clk IMX8QM_USB3_LPM_DIV>, 2105 <&clk IMX8QM_USB3_LPM_DIV>,
2106 <&clk IMX8QM_USB3_BUS_DIV>; 2106 <&clk IMX8QM_USB3_BUS_DIV>;
2107 assigned-clock-rates = <125000000>, <12000000>, <250000000>; 2107 assigned-clock-rates = <125000000>, <12000000>, <250000000>;
2108 power-domains = <&pd_conn_usb2>; 2108 power-domains = <&pd_conn_usb2>;
2109 cdns3,usbphy = <&usbphynop1>; 2109 cdns3,usbphy = <&usbphynop1>;
2110 status = "disabled"; 2110 status = "disabled";
2111 }; 2111 };
2112 2112
2113 ddr_pmu0: ddr_pmu@5c020000 { 2113 ddr_pmu0: ddr_pmu@5c020000 {
2114 compatible = "fsl,imx8-ddr-pmu"; 2114 compatible = "fsl,imx8-ddr-pmu";
2115 reg = <0x0 0x5c020000 0x0 0x10000>; 2115 reg = <0x0 0x5c020000 0x0 0x10000>;
2116 interrupt-parent = <&gic>; 2116 interrupt-parent = <&gic>;
2117 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
2118 }; 2118 };
2119 2119
2120 ddr_pmu1: ddr_pmu@5c120000 { 2120 ddr_pmu1: ddr_pmu@5c120000 {
2121 compatible = "fsl,imx8-ddr-pmu"; 2121 compatible = "fsl,imx8-ddr-pmu";
2122 reg = <0x0 0x5c120000 0x0 0x10000>; 2122 reg = <0x0 0x5c120000 0x0 0x10000>;
2123 interrupt-parent = <&gic>; 2123 interrupt-parent = <&gic>;
2124 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2124 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2125 }; 2125 };
2126 2126
2127 flexspi0: flexspi@05d120000 { 2127 flexspi0: flexspi@05d120000 {
2128 #address-cells = <1>; 2128 #address-cells = <1>;
2129 #size-cells = <0>; 2129 #size-cells = <0>;
2130 compatible = "fsl,imx8qm-flexspi"; 2130 compatible = "fsl,imx8qm-flexspi";
2131 reg = <0x0 0x5d120000 0x0 0x10000>, 2131 reg = <0x0 0x5d120000 0x0 0x10000>,
2132 <0x0 0x08000000 0x0 0x19ffffff>; 2132 <0x0 0x08000000 0x0 0x19ffffff>;
2133 reg-names = "FlexSPI", "FlexSPI-memory"; 2133 reg-names = "FlexSPI", "FlexSPI-memory";
2134 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2135 clocks = <&clk IMX8QM_FSPI0_CLK>; 2135 clocks = <&clk IMX8QM_FSPI0_CLK>;
2136 assigned-clocks = <&clk IMX8QM_FSPI0_DIV>; 2136 assigned-clocks = <&clk IMX8QM_FSPI0_DIV>;
2137 assigned-clock-rates = <29000000>; 2137 assigned-clock-rates = <29000000>;
2138 power-domains = <&pd_lsio_flexspi0>; 2138 power-domains = <&pd_lsio_flexspi0>;
2139 clock-names = "fspi"; 2139 clock-names = "fspi";
2140 status = "disabled"; 2140 status = "disabled";
2141 }; 2141 };
2142 2142
2143 display: display-subsystem { 2143 display: display-subsystem {
2144 compatible = "fsl,imx-display-subsystem"; 2144 compatible = "fsl,imx-display-subsystem";
2145 ports = <&dpu1_disp0>, <&dpu1_disp1>, 2145 ports = <&dpu1_disp0>, <&dpu1_disp1>,
2146 <&dpu2_disp0>, <&dpu2_disp1>; 2146 <&dpu2_disp0>, <&dpu2_disp1>;
2147 }; 2147 };
2148 2148
2149 dma_cap: dma_cap { 2149 dma_cap: dma_cap {
2150 compatible = "dma-capability"; 2150 compatible = "dma-capability";
2151 only-dma-mask32 = <1>; 2151 only-dma-mask32 = <1>;
2152 }; 2152 };
2153 2153
2154 hsio: hsio@5f080000 { 2154 hsio: hsio@5f080000 {
2155 compatible = "fsl,imx8qm-hsio", "syscon"; 2155 compatible = "fsl,imx8qm-hsio", "syscon";
2156 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ 2156 reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
2157 }; 2157 };
2158 2158
2159 ocotp: ocotp { 2159 ocotp: ocotp {
2160 #address-cells = <1>; 2160 #address-cells = <1>;
2161 #size-cells = <1>; 2161 #size-cells = <1>;
2162 compatible = "fsl,imx8qm-ocotp", "syscon"; 2162 compatible = "fsl,imx8qm-ocotp", "syscon";
2163 }; 2163 };
2164 2164
2165 pciea: pcie@0x5f000000 { 2165 pciea: pcie@0x5f000000 {
2166 compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; 2166 compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
2167 reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ 2167 reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */
2168 <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ 2168 <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */
2169 reg-names = "dbi", "config"; 2169 reg-names = "dbi", "config";
2170 reserved-region = <&rpmsg_reserved>; 2170 reserved-region = <&rpmsg_reserved>;
2171 #address-cells = <3>; 2171 #address-cells = <3>;
2172 #size-cells = <2>; 2172 #size-cells = <2>;
2173 device_type = "pci"; 2173 device_type = "pci";
2174 ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ 2174 ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */
2175 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ 2175 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
2176 num-lanes = <1>; 2176 num-lanes = <1>;
2177 2177
2178 #interrupt-cells = <1>; 2178 #interrupt-cells = <1>;
2179 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 2179 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
2180 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2180 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
2181 interrupt-names = "msi"; 2181 interrupt-names = "msi";
2182 2182
2183 /* 2183 /*
2184 * Set these clocks in default, then clocks should be 2184 * Set these clocks in default, then clocks should be
2185 * refined for exact hw design of imx8 pcie. 2185 * refined for exact hw design of imx8 pcie.
2186 */ 2186 */
2187 clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, 2187 clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
2188 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, 2188 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
2189 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, 2189 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
2190 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, 2190 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
2191 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; 2191 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>,
2192 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; 2192 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
2193 2193 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
2194 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
2195 "phy_per", "misc_per";
2194 interrupt-map-mask = <0 0 0 0x7>; 2196 interrupt-map-mask = <0 0 0 0x7>;
2195 interrupt-map = <0 0 0 1 &gic 0 73 4>, 2197 interrupt-map = <0 0 0 1 &gic 0 73 4>,
2196 <0 0 0 2 &gic 0 74 4>, 2198 <0 0 0 2 &gic 0 74 4>,
2197 <0 0 0 3 &gic 0 75 4>, 2199 <0 0 0 3 &gic 0 75 4>,
2198 <0 0 0 4 &gic 0 76 4>; 2200 <0 0 0 4 &gic 0 76 4>;
2199 power-domains = <&pd_pcie1>; 2201 power-domains = <&pd_pcie1>;
2200 fsl,max-link-speed = <3>; 2202 fsl,max-link-speed = <3>;
2201 hsio-cfg = <PCIEAX1PCIEBX1SATA>; 2203 hsio-cfg = <PCIEAX1PCIEBX1SATA>;
2202 hsio = <&hsio>; 2204 hsio = <&hsio>;
2203 ctrl-id = <0>; /* pciea */ 2205 ctrl-id = <0>; /* pciea */
2204 cpu-base-addr = <0x40000000>; 2206 cpu-base-addr = <0x40000000>;
2205 status = "disabled"; 2207 status = "disabled";
2206 }; 2208 };
2207 2209
2208 pcieb: pcie@0x5f010000 { 2210 pcieb: pcie@0x5f010000 {
2209 compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; 2211 compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
2210 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ 2212 reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */
2211 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ 2213 <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */
2212 reg-names = "dbi", "config"; 2214 reg-names = "dbi", "config";
2213 reserved-region = <&rpmsg_reserved>; 2215 reserved-region = <&rpmsg_reserved>;
2214 #address-cells = <3>; 2216 #address-cells = <3>;
2215 #size-cells = <2>; 2217 #size-cells = <2>;
2216 device_type = "pci"; 2218 device_type = "pci";
2217 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 2219 ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
2218 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ 2220 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
2219 num-lanes = <1>; 2221 num-lanes = <1>;
2220 2222
2221 #interrupt-cells = <1>; 2223 #interrupt-cells = <1>;
2222 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2224 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2223 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2225 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
2224 interrupt-names = "msi"; 2226 interrupt-names = "msi";
2225 2227
2226 /* 2228 /*
2227 * Set these clocks in default, then clocks should be 2229 * Set these clocks in default, then clocks should be
2228 * refined for exact hw design of imx8 pcie. 2230 * refined for exact hw design of imx8 pcie.
2229 */ 2231 */
2230 clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, 2232 clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
2231 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, 2233 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
2232 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, 2234 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
2233 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, 2235 <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
2234 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; 2236 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>,
2235 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; 2237 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
2236 2238 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
2239 <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>,
2240 <&clk IMX8QM_HSIO_MISC_PER_CLK>;
2241 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi",
2242 "pciex2_per", "pcie_phy_pclk", "phy_per", "misc_per";
2237 interrupt-map-mask = <0 0 0 0x7>; 2243 interrupt-map-mask = <0 0 0 0x7>;
2238 interrupt-map = <0 0 0 1 &gic 0 105 4>, 2244 interrupt-map = <0 0 0 1 &gic 0 105 4>,
2239 <0 0 0 2 &gic 0 106 4>, 2245 <0 0 0 2 &gic 0 106 4>,
2240 <0 0 0 3 &gic 0 107 4>, 2246 <0 0 0 3 &gic 0 107 4>,
2241 <0 0 0 4 &gic 0 108 4>; 2247 <0 0 0 4 &gic 0 108 4>;
2242 power-domains = <&pd_pcie1>; 2248 power-domains = <&pd_pcie1>;
2243 fsl,max-link-speed = <3>; 2249 fsl,max-link-speed = <3>;
2244 hsio-cfg = <PCIEAX1PCIEBX1SATA>; 2250 hsio-cfg = <PCIEAX1PCIEBX1SATA>;
2245 hsio = <&hsio>; 2251 hsio = <&hsio>;
2246 ctrl-id = <1>; /* pcieb */ 2252 ctrl-id = <1>; /* pcieb */
2247 cpu-base-addr = <0x80000000>; 2253 cpu-base-addr = <0x80000000>;
2248 status = "disabled"; 2254 status = "disabled";
2249 }; 2255 };
2250 2256
2251 sata: sata@5f020000 { 2257 sata: sata@5f020000 {
2252 compatible = "fsl,imx8qm-ahci"; 2258 compatible = "fsl,imx8qm-ahci";
2253 reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */ 2259 reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */
2254 <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */ 2260 <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */
2255 reg-names = "ctl", "phy"; 2261 reg-names = "ctl", "phy";
2256 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 2262 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
2257 clocks = <&clk IMX8QM_HSIO_SATA_CLK>, 2263 clocks = <&clk IMX8QM_HSIO_SATA_CLK>,
2258 <&clk IMX8QM_HSIO_PHY_X1_PCLK>, 2264 <&clk IMX8QM_HSIO_PHY_X1_PCLK>,
2259 <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, 2265 <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>,
2260 <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, 2266 <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>,
2261 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, 2267 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
2262 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, 2268 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
2263 <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; 2269 <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>;
2264 clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", 2270 clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx",
2265 "phy_pclk0", "phy_pclk1", "phy_apbclk"; 2271 "phy_pclk0", "phy_pclk1", "phy_apbclk";
2266 hsio = <&hsio>; 2272 hsio = <&hsio>;
2267 power-domains = <&pd_sata0>; 2273 power-domains = <&pd_sata0>;
2268 iommus = <&smmu 0x13 0x7f80>; 2274 iommus = <&smmu 0x13 0x7f80>;
2269 status = "disabled"; 2275 status = "disabled";
2270 }; 2276 };
2271 2277
2272 imx_rpmsg: imx_rpmsg { 2278 imx_rpmsg: imx_rpmsg {
2273 compatible = "fsl,rpmsg-bus", "simple-bus"; 2279 compatible = "fsl,rpmsg-bus", "simple-bus";
2274 #address-cells = <2>; 2280 #address-cells = <2>;
2275 #size-cells = <2>; 2281 #size-cells = <2>;
2276 ranges; 2282 ranges;
2277 2283
2278 mu_rpmsg: mu_rpmsg@5d200000 { 2284 mu_rpmsg: mu_rpmsg@5d200000 {
2279 compatible = "fsl,imx6sx-mu"; 2285 compatible = "fsl,imx6sx-mu";
2280 reg = <0x0 0x5d200000 0x0 0x10000>; 2286 reg = <0x0 0x5d200000 0x0 0x10000>;
2281 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2287 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
2282 clocks = <&clk IMX8QM_LSIO_MU5A_IPG_CLK>; 2288 clocks = <&clk IMX8QM_LSIO_MU5A_IPG_CLK>;
2283 clock-names = "ipg"; 2289 clock-names = "ipg";
2284 power-domains = <&pd_lsio_mu5a>; 2290 power-domains = <&pd_lsio_mu5a>;
2285 status = "okay"; 2291 status = "okay";
2286 }; 2292 };
2287 2293
2288 rpmsg: rpmsg { 2294 rpmsg: rpmsg {
2289 compatible = "fsl,imx8qm-rpmsg"; 2295 compatible = "fsl,imx8qm-rpmsg";
2290 power-domains = <&pd_lsio_mu5a>; 2296 power-domains = <&pd_lsio_mu5a>;
2291 mub-partition = <3>; 2297 mub-partition = <3>;
2292 memory-region = <&rpmsg_dma_reserved>; 2298 memory-region = <&rpmsg_dma_reserved>;
2293 status = "disabled"; 2299 status = "disabled";
2294 }; 2300 };
2295 2301
2296 mu_rpmsg1: mu_rpmsg1@5d210000 { 2302 mu_rpmsg1: mu_rpmsg1@5d210000 {
2297 compatible = "fsl,imx-mu-rpmsg1"; 2303 compatible = "fsl,imx-mu-rpmsg1";
2298 reg = <0x0 0x5d210000 0x0 0x10000>; 2304 reg = <0x0 0x5d210000 0x0 0x10000>;
2299 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2305 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
2300 clocks = <&clk IMX8QM_LSIO_MU6A_IPG_CLK>; 2306 clocks = <&clk IMX8QM_LSIO_MU6A_IPG_CLK>;
2301 clock-names = "ipg"; 2307 clock-names = "ipg";
2302 power-domains = <&pd_lsio_mu6a>; 2308 power-domains = <&pd_lsio_mu6a>;
2303 status = "okay"; 2309 status = "okay";
2304 }; 2310 };
2305 2311
2306 rpmsg1: rpmsg1{ 2312 rpmsg1: rpmsg1{
2307 compatible = "fsl,imx8qm-rpmsg"; 2313 compatible = "fsl,imx8qm-rpmsg";
2308 multi-core-id = <1>; 2314 multi-core-id = <1>;
2309 mub-partition = <4>; 2315 mub-partition = <4>;
2310 power-domains = <&pd_lsio_mu6a>; 2316 power-domains = <&pd_lsio_mu6a>;
2311 memory-region = <&rpmsg_dma_reserved>; 2317 memory-region = <&rpmsg_dma_reserved>;
2312 status = "disabled"; 2318 status = "disabled";
2313 }; 2319 };
2314 }; 2320 };
2315 2321
2316 crypto: caam@0x31400000 { 2322 crypto: caam@0x31400000 {
2317 compatible = "fsl,sec-v4.0"; 2323 compatible = "fsl,sec-v4.0";
2318 reg = <0 0x31400000 0 0x400000>; 2324 reg = <0 0x31400000 0 0x400000>;
2319 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2325 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2320 #address-cells = <1>; 2326 #address-cells = <1>;
2321 #size-cells = <1>; 2327 #size-cells = <1>;
2322 ranges = <0 0 0x31400000 0x400000>; 2328 ranges = <0 0 0x31400000 0x400000>;
2323 fsl,first-jr-index = <2>; 2329 fsl,first-jr-index = <2>;
2324 fsl,sec-era = <9>; 2330 fsl,sec-era = <9>;
2325 2331
2326 sec_jr1: jr1@0x20000 { 2332 sec_jr1: jr1@0x20000 {
2327 compatible = "fsl,sec-v4.0-job-ring"; 2333 compatible = "fsl,sec-v4.0-job-ring";
2328 reg = <0x20000 0x1000>; 2334 reg = <0x20000 0x1000>;
2329 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 2335 interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&pd_caam_jr1>; 2336 power-domains = <&pd_caam_jr1>;
2331 status = "disabled"; 2337 status = "disabled";
2332 }; 2338 };
2333 2339
2334 sec_jr2: jr2@30000 { 2340 sec_jr2: jr2@30000 {
2335 compatible = "fsl,sec-v4.0-job-ring"; 2341 compatible = "fsl,sec-v4.0-job-ring";
2336 reg = <0x30000 0x1000>; 2342 reg = <0x30000 0x1000>;
2337 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; 2343 interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
2338 power-domains = <&pd_caam_jr2>; 2344 power-domains = <&pd_caam_jr2>;
2339 status = "okay"; 2345 status = "okay";
2340 }; 2346 };
2341 2347
2342 sec_jr3: jr3@40000 { 2348 sec_jr3: jr3@40000 {
2343 compatible = "fsl,sec-v4.0-job-ring"; 2349 compatible = "fsl,sec-v4.0-job-ring";
2344 reg = <0x40000 0x1000>; 2350 reg = <0x40000 0x1000>;
2345 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 2351 interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
2346 power-domains = <&pd_caam_jr3>; 2352 power-domains = <&pd_caam_jr3>;
2347 status = "okay"; 2353 status = "okay";
2348 }; 2354 };
2349 }; 2355 };
2350 2356
2351 caam_sm: caam-sm@31800000 { 2357 caam_sm: caam-sm@31800000 {
2352 compatible = "fsl,imx6q-caam-sm"; 2358 compatible = "fsl,imx6q-caam-sm";
2353 reg = <0 0x31800000 0 0x10000>; 2359 reg = <0 0x31800000 0 0x10000>;
2354 }; 2360 };
2355 2361
2356 i2c_rpbus_0: i2c-rpbus-0 { 2362 i2c_rpbus_0: i2c-rpbus-0 {
2357 compatible = "fsl,i2c-rpbus"; 2363 compatible = "fsl,i2c-rpbus";
2358 status = "disabled"; 2364 status = "disabled";
2359 }; 2365 };
2360 2366
2361 i2c_rpbus_1: i2c-rpbus-1 { 2367 i2c_rpbus_1: i2c-rpbus-1 {
2362 compatible = "fsl,i2c-rpbus"; 2368 compatible = "fsl,i2c-rpbus";
2363 status = "disabled"; 2369 status = "disabled";
2364 }; 2370 };
2365 2371
2366 sc_pwrkey: sc-powerkey { 2372 sc_pwrkey: sc-powerkey {
2367 compatible = "fsl,imx8-pwrkey"; 2373 compatible = "fsl,imx8-pwrkey";
2368 linux,keycode = <KEY_POWER>; 2374 linux,keycode = <KEY_POWER>;
2369 wakeup-source; 2375 wakeup-source;
2370 }; 2376 };
2371 2377
2372 wdog: wdog { 2378 wdog: wdog {
2373 compatible = "fsl,imx8-wdt"; 2379 compatible = "fsl,imx8-wdt";
2374 }; 2380 };
2375 2381