Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Tom Rini
2 parents cdce889959 49d87b1325
Showing 7 changed files Side-by-side Diff
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc8xxx/fdt.c
arch/powerpc/include/asm/config_mpc85xx.h
arch/powerpc/include/asm/immap_85xx.h
board/freescale/c29xpcie/README
include/fsl_usb.h
@@ -22,6 +22,7 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <fsl_usb.h>
 #include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
@@ -605,7 +606,7 @@
  
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 	{
-		ccsr_usb_phy_t *usb_phy1 =
+		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -613,7 +614,7 @@
 #endif
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 	{
-		ccsr_usb_phy_t *usb_phy2 =
+		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
@@ -635,7 +636,7 @@
 #endif
  
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
-		ccsr_usb_phy_t *usb_phy =
+		struct ccsr_usb_phy __iomem *usb_phy =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
@@ -13,8 +13,12 @@
 #include <asm/errno.h>
 #include "fsl_corenet2_serdes.h"
  
+#ifdef CONFIG_SYS_FSL_SRDS_1
 static u64 serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 static u64 serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 static u64 serdes3_prtcl_map;
 #endif
  
  
@@ -78,8 +82,12 @@
 {
 	u64 ret = 0;
  
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	ret |= (1ULL << device) & serdes1_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	ret |= (1ULL << device) & serdes2_prtcl_map;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	ret |= (1ULL << device) & serdes3_prtcl_map;
 #endif
  
  
@@ -97,14 +105,18 @@
 	int i;
  
 	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	case FSL_SRDS_1:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	case FSL_SRDS_2:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 		break;
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	case FSL_SRDS_3:
 		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
  
  
@@ -163,14 +175,18 @@
 void fsl_serdes_init(void)
 {
  
+#ifdef CONFIG_SYS_FSL_SRDS_1
 	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
 	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
 		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#endif
 #ifdef CONFIG_SYS_FSL_SRDS_3
 	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
 		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
@@ -121,11 +121,8 @@
 {
 	const char *modes[] = { "host", "peripheral", "otg" };
 	const char *phys[] = { "ulpi", "utmi" };
-	const char *mode = NULL;
-	const char *phy_type = NULL;
 	const char *dr_mode_type = NULL;
 	const char *dr_phy_type = NULL;
-	char usb1_defined = 0;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
 	char str[5];
@@ -159,12 +156,6 @@
 			dr_mode_type = modes[mode_idx];
 			dr_phy_type = phys[phy_idx];
  
-			/* use usb_dr_mode and usb_phy_type if
-			   usb1_defined = 0; these variables are to
-			   be deprecated */
-			if (!strcmp(str, "usb1"))
-				usb1_defined = 1;
-
 			if (mode_idx < 0 && phy_idx < 0) {
 				printf("WARNING: invalid phy or mode\n");
 				return;
@@ -182,19 +173,6 @@
  
 		if (usb_phy_off < 0)
 			return;
-	}
-
-	if (!usb1_defined) {
-		int usb_off = -1;
-		mode = getenv("usb_dr_mode");
-		phy_type = getenv("usb_phy_type");
-		if (mode || phy_type) {
-			printf("WARNING: usb_dr_mode and usb_phy_type "
-				"are to be deprecated soon. Use "
-				"hwconfig to set these values instead!!\n");
-			fdt_fixup_usb_mode_phy_type(blob, mode,
-				phy_type, usb_off);
-		}
 	}
 }
 #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
@@ -535,6 +535,8 @@
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	5
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
@@ -565,6 +567,8 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT	4
 #define CONFIG_SYS_NUM_FMAN		1
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
@@ -2846,54 +2846,6 @@
 	u8	res4[0x400];
 } ccsr_pme_t;
  
-#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
-struct ccsr_usb_port_ctrl {
-	u32	ctrl;
-	u32	drvvbuscfg;
-	u32	pwrfltcfg;
-	u32	sts;
-	u8	res_14[0xc];
-	u32	bistcfg;
-	u32	biststs;
-	u32	abistcfg;
-	u32	abiststs;
-	u8	res_30[0x10];
-	u32	xcvrprg;
-	u32	anaprg;
-	u32	anadrv;
-	u32	anasts;
-};
-
-typedef struct ccsr_usb_phy {
-	u32	id;
-	struct  ccsr_usb_port_ctrl port1;
-	u8	res_50[0xc];
-	u32	tvr;
-	u32	pllprg[4];
-	u8	res_70[0x4];
-	u32	anaccfg;
-	u32	dbg;
-	u8	res_7c[0x4];
-	struct  ccsr_usb_port_ctrl port2;
-	u8	res_dc[0x334];
-} ccsr_usb_phy_t;
-
-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
-#else
-typedef struct ccsr_usb_phy {
-	u8	res0[0x18];
-	u32	usb_enable_override;
-	u8	res[0xe4];
-} ccsr_usb_phy_t;
-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
-#endif
-
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
+Overview
+=========
+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
+as public key crypto accelerator or secure key management module.
+It includes C293PCIE board, C293PCIE board and C291PCIE board.
+The Freescale C29x family is a high performance crypto co-processor.
+It combines a single e500v2 core with necessary SEC engines.
+(maximum core frequency 1000/1200 MHz).
+
+The C29xPCIE board features are as follows:
+Memory subsystem:
+	- 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+	- 64 Mbyte NOR flash single-chip memory
+	- 4 Gbyte NAND flash memory
+	- 1 Mbit AT24C1024 I2C EEPROM
+	- 16 Mbyte SPI memory
+
+Interfaces:
+	- 10/100/1000 BaseT Ethernet ports:
+		- eTSEC1, RGMII: one 10/100/1000 port
+		- eTSEC2, RGMII: one 10/100/1000 port
+	- DUART interface:
+		- DUART interface: supports two UARTs up to 115200 bps for
+		   console display
+
+Board connectors:
+	- Mini-ITX power supply connector
+	- JTAG/COP for debugging
+
+Physical Memory Map on C29xPCIE
+===============================
+Address Start   Address End   Memory type
+0x0_0000_0000 - 0x0_1fff_ffff   512MB DDR
+0xc_0000_0000 - 0xc_8fff_ffff   256MB PCIE memory
+0xf_ec00_0000 - 0xf_efff_ffff   64MB NOR flash
+0xf_ffb0_0000 - 0xf_ffb7_ffff   512KB SRAM
+0xf_ffc0_0000 - 0xf_ffc0_ffff   64KB PCIE IO
+0xf_ffdf_0000 - 0xf_ffdf_0fff   4KB CPLD
+0xf_ffe0_0000 - 0xf_ffef_ffff   1MB CCSR
+
+Serial Port Configuration on C29xPCIE
+=====================================
+Configure the serial port of the attached computer with the following values:
+	-Data rate: 115200 bps
+	-Number of data bits: 8
+	-Parity: None
+	-Number of Stop bits: 1
+	-Flow Control: Hardware/None
+
+Settings of DIP-switch
+======================
+  SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
+  SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
+Note: 1 stands for 'off', 0 stands for 'on'
+
+Build and program u-boot to NOR flash
+==================================
+1. Build u-boot.bin image example:
+	export ARCH=powerpc
+	export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
+	make C293PCIE
+
+2. Program u-boot.bin into NOR flash
+	=> tftp $loadaddr $uboot
+	=> protect off eff80000 +$filesize
+	=> erase eff80000 +$filesize
+	=> cp.b $loadaddr eff80000 $filesize
+
+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
+
+Alternate NOR bank
+==================
+There are four banks in C29XPCIE board, example to change bank booting:
+1. Program u-boot.bin into alternate NOR bank
+	=> tftp $loadaddr $uboot
+	=> protect off e9f80000 +$filesize
+	=> erase e9f80000 +$filesize
+	=> cp.b $loadaddr e9f80000 $filesize
+
+2. Switch to alternate NOR bank
+	=> cpld_cmd reset altbank [bank]
+	- [bank] bank value select 1-4
+	- bank 1 on the flash 0x0000000~0x0ffffff
+	- bank 2 on the flash 0x1000000~0x1ffffff
+	- bank 3 on the flash 0x2000000~0x2ffffff
+	- bank 4 on the flash 0x3000000~0x3ffffff
+	or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
+
+Build and program u-boot to SPI flash
+==================================
+1. Build u-boot-spi.bin image
+	make C29xPCIE_SPIFLASH_config; make
+	Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
+
+2. Program u-boot-spi.bin into SPI flash
+	=> tftp $loadaddr $uboot-spi
+	=> sf erase 0 100000
+	=> sf write $loadaddr 0 $filesize
+
+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
+/*
+ * Freescale USB Controller
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_FSL_USB_H_
+#define _ASM_FSL_USB_H_
+
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+struct ccsr_usb_port_ctrl {
+	u32	ctrl;
+	u32	drvvbuscfg;
+	u32	pwrfltcfg;
+	u32	sts;
+	u8	res_14[0xc];
+	u32	bistcfg;
+	u32	biststs;
+	u32	abistcfg;
+	u32	abiststs;
+	u8	res_30[0x10];
+	u32	xcvrprg;
+	u32	anaprg;
+	u32	anadrv;
+	u32	anasts;
+};
+
+struct ccsr_usb_phy {
+	u32	id;
+	struct ccsr_usb_port_ctrl port1;
+	u8	res_50[0xc];
+	u32	tvr;
+	u32	pllprg[4];
+	u8	res_70[0x4];
+	u32	anaccfg;
+	u32	dbg;
+	u8	res_7c[0x4];
+	struct ccsr_usb_port_ctrl port2;
+	u8	res_dc[0x334];
+};
+
+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
+#else
+struct ccsr_usb_phy {
+	u8	res0[0x18];
+	u32	usb_enable_override;
+	u8	res[0xe4];
+};
+#define	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE	1
+#endif
+
+#endif /*_ASM_FSL_USB_H_ */
...	...	@@ -22,6 +22,7 @@
22	22	#include <asm/fsl_law.h>
23	23	#include <asm/fsl_serdes.h>
24	24	#include <asm/fsl_srio.h>
	25	+#include <fsl_usb.h>
25	26	#include <hwconfig.h>
26	27	#include <linux/compiler.h>
27	28	#include "mp.h"
...	...	@@ -605,7 +606,7 @@
605	606
606	607	#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
607	608	{
608		- ccsr_usb_phy_t *usb_phy1 =
	609	+ struct ccsr_usb_phy __iomem *usb_phy1 =
609	610	(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
610	611	out_be32(&usb_phy1->usb_enable_override,
611	612	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
...	...	@@ -613,7 +614,7 @@
613	614	#endif
614	615	#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
615	616	{
616		- ccsr_usb_phy_t *usb_phy2 =
	617	+ struct ccsr_usb_phy __iomem *usb_phy2 =
617	618	(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
618	619	out_be32(&usb_phy2->usb_enable_override,
619	620	CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
...	...	@@ -635,7 +636,7 @@
635	636	#endif
636	637
637	638	#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
638		- ccsr_usb_phy_t *usb_phy =
	639	+ struct ccsr_usb_phy __iomem *usb_phy =
639	640	(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
640	641	setbits_be32(&usb_phy->pllprg[1],
641	642	CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN \|
...	...	@@ -13,8 +13,12 @@
13	13	#include <asm/errno.h>
14	14	#include "fsl_corenet2_serdes.h"
15	15
	16	+#ifdef CONFIG_SYS_FSL_SRDS_1
16	17	static u64 serdes1_prtcl_map;
	18	+#endif
	19	+#ifdef CONFIG_SYS_FSL_SRDS_2
17	20	static u64 serdes2_prtcl_map;
	21	+#endif
18	22	#ifdef CONFIG_SYS_FSL_SRDS_3
19	23	static u64 serdes3_prtcl_map;
20	24	#endif
21	25
22	26
...	...	@@ -78,8 +82,12 @@
78	82	{
79	83	u64 ret = 0;
80	84
	85	+#ifdef CONFIG_SYS_FSL_SRDS_1
81	86	ret \|= (1ULL << device) & serdes1_prtcl_map;
	87	+#endif
	88	+#ifdef CONFIG_SYS_FSL_SRDS_2
82	89	ret \|= (1ULL << device) & serdes2_prtcl_map;
	90	+#endif
83	91	#ifdef CONFIG_SYS_FSL_SRDS_3
84	92	ret \|= (1ULL << device) & serdes3_prtcl_map;
85	93	#endif
86	94
87	95
...	...	@@ -97,14 +105,18 @@
97	105	int i;
98	106
99	107	switch (sd) {
	108	+#ifdef CONFIG_SYS_FSL_SRDS_1
100	109	case FSL_SRDS_1:
101	110	cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
102	111	cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
103	112	break;
	113	+#endif
	114	+#ifdef CONFIG_SYS_FSL_SRDS_2
104	115	case FSL_SRDS_2:
105	116	cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
106	117	cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
107	118	break;
	119	+#endif
108	120	#ifdef CONFIG_SYS_FSL_SRDS_3
109	121	case FSL_SRDS_3:
110	122	cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
111	123
112	124
...	...	@@ -163,14 +175,18 @@
163	175	void fsl_serdes_init(void)
164	176	{
165	177
	178	+#ifdef CONFIG_SYS_FSL_SRDS_1
166	179	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
167	180	CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
168	181	FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
169	182	FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
	183	+#endif
	184	+#ifdef CONFIG_SYS_FSL_SRDS_2
170	185	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
171	186	CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
172	187	FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
173	188	FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
	189	+#endif
174	190	#ifdef CONFIG_SYS_FSL_SRDS_3
175	191	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
176	192	CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
...	...	@@ -121,11 +121,8 @@
121	121	{
122	122	const char *modes[] = { "host", "peripheral", "otg" };
123	123	const char *phys[] = { "ulpi", "utmi" };
124		- const char *mode = NULL;
125		- const char *phy_type = NULL;
126	124	const char *dr_mode_type = NULL;
127	125	const char *dr_phy_type = NULL;
128		- char usb1_defined = 0;
129	126	int usb_mode_off = -1;
130	127	int usb_phy_off = -1;
131	128	char str[5];
...	...	@@ -159,12 +156,6 @@
159	156	dr_mode_type = modes[mode_idx];
160	157	dr_phy_type = phys[phy_idx];
161	158
162		- /* use usb_dr_mode and usb_phy_type if
163		- usb1_defined = 0; these variables are to
164		- be deprecated */
165		- if (!strcmp(str, "usb1"))
166		- usb1_defined = 1;
167		-
168	159	if (mode_idx < 0 && phy_idx < 0) {
169	160	printf("WARNING: invalid phy or mode\n");
170	161	return;
...	...	@@ -182,19 +173,6 @@
182	173
183	174	if (usb_phy_off < 0)
184	175	return;
185		- }
186		-
187		- if (!usb1_defined) {
188		- int usb_off = -1;
189		- mode = getenv("usb_dr_mode");
190		- phy_type = getenv("usb_phy_type");
191		- if (mode \|\| phy_type) {
192		- printf("WARNING: usb_dr_mode and usb_phy_type "
193		- "are to be deprecated soon. Use "
194		- "hwconfig to set these values instead!!\n");
195		- fdt_fixup_usb_mode_phy_type(blob, mode,
196		- phy_type, usb_off);
197		- }
198	176	}
199	177	}
200	178	#endif /* defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB) */
...	...	@@ -535,6 +535,8 @@
535	535	#endif
536	536	#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
537	537	#define CONFIG_SYS_FSL_NUM_LAWS 32
	538	+#define CONFIG_SYS_FSL_SRDS_1
	539	+#define CONFIG_SYS_FSL_SRDS_2
538	540	#define CONFIG_SYS_FSL_SRDS_3
539	541	#define CONFIG_SYS_FSL_SRDS_4
540	542	#define CONFIG_SYS_FSL_SEC_COMPAT 4
...	...	@@ -565,6 +567,8 @@
565	567	#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
566	568	#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
567	569	#define CONFIG_SYS_FSL_NUM_LAWS 32
	570	+#define CONFIG_SYS_FSL_SRDS_1
	571	+#define CONFIG_SYS_FSL_SRDS_2
568	572	#define CONFIG_SYS_FSL_SEC_COMPAT 4
569	573	#define CONFIG_SYS_NUM_FMAN 1
570	574	#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
...	...	@@ -2846,54 +2846,6 @@
2846	2846	u8 res4[0x400];
2847	2847	} ccsr_pme_t;
2848	2848
2849		-#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
2850		-struct ccsr_usb_port_ctrl {
2851		- u32 ctrl;
2852		- u32 drvvbuscfg;
2853		- u32 pwrfltcfg;
2854		- u32 sts;
2855		- u8 res_14[0xc];
2856		- u32 bistcfg;
2857		- u32 biststs;
2858		- u32 abistcfg;
2859		- u32 abiststs;
2860		- u8 res_30[0x10];
2861		- u32 xcvrprg;
2862		- u32 anaprg;
2863		- u32 anadrv;
2864		- u32 anasts;
2865		-};
2866		-
2867		-typedef struct ccsr_usb_phy {
2868		- u32 id;
2869		- struct ccsr_usb_port_ctrl port1;
2870		- u8 res_50[0xc];
2871		- u32 tvr;
2872		- u32 pllprg[4];
2873		- u8 res_70[0x4];
2874		- u32 anaccfg;
2875		- u32 dbg;
2876		- u8 res_7c[0x4];
2877		- struct ccsr_usb_port_ctrl port2;
2878		- u8 res_dc[0x334];
2879		-} ccsr_usb_phy_t;
2880		-
2881		-#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
2882		-#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
2883		-#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
2884		-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
2885		-#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
2886		-#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
2887		-#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
2888		-#else
2889		-typedef struct ccsr_usb_phy {
2890		- u8 res0[0x18];
2891		- u32 usb_enable_override;
2892		- u8 res[0xe4];
2893		-} ccsr_usb_phy_t;
2894		-#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
2895		-#endif
2896		-
2897	2849	#ifdef CONFIG_SYS_FSL_RAID_ENGINE
2898	2850	struct ccsr_raide {
2899	2851	u8 res0[0x543];
	1	+Overview
	2	+=========
	3	+C29XPCIE board is a series of Freescale PCIe add-in cards to perform
	4	+as public key crypto accelerator or secure key management module.
	5	+It includes C293PCIE board, C293PCIE board and C291PCIE board.
	6	+The Freescale C29x family is a high performance crypto co-processor.
	7	+It combines a single e500v2 core with necessary SEC engines.
	8	+(maximum core frequency 1000/1200 MHz).
	9	+
	10	+The C29xPCIE board features are as follows:
	11	+Memory subsystem:
	12	+ - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
	13	+ - 64 Mbyte NOR flash single-chip memory
	14	+ - 4 Gbyte NAND flash memory
	15	+ - 1 Mbit AT24C1024 I2C EEPROM
	16	+ - 16 Mbyte SPI memory
	17	+
	18	+Interfaces:
	19	+ - 10/100/1000 BaseT Ethernet ports:
	20	+ - eTSEC1, RGMII: one 10/100/1000 port
	21	+ - eTSEC2, RGMII: one 10/100/1000 port
	22	+ - DUART interface:
	23	+ - DUART interface: supports two UARTs up to 115200 bps for
	24	+ console display
	25	+
	26	+Board connectors:
	27	+ - Mini-ITX power supply connector
	28	+ - JTAG/COP for debugging
	29	+
	30	+Physical Memory Map on C29xPCIE
	31	+===============================
	32	+Address Start Address End Memory type
	33	+0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR
	34	+0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
	35	+0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
	36	+0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM
	37	+0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
	38	+0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD
	39	+0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR
	40	+
	41	+Serial Port Configuration on C29xPCIE
	42	+=====================================
	43	+Configure the serial port of the attached computer with the following values:
	44	+ -Data rate: 115200 bps
	45	+ -Number of data bits: 8
	46	+ -Parity: None
	47	+ -Number of Stop bits: 1
	48	+ -Flow Control: Hardware/None
	49	+
	50	+Settings of DIP-switch
	51	+======================
	52	+ SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
	53	+ SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash
	54	+Note: 1 stands for 'off', 0 stands for 'on'
	55	+
	56	+Build and program u-boot to NOR flash
	57	+==================================
	58	+1. Build u-boot.bin image example:
	59	+ export ARCH=powerpc
	60	+ export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
	61	+ make C293PCIE
	62	+
	63	+2. Program u-boot.bin into NOR flash
	64	+ => tftp $loadaddr $uboot
	65	+ => protect off eff80000 +$filesize
	66	+ => erase eff80000 +$filesize
	67	+ => cp.b $loadaddr eff80000 $filesize
	68	+
	69	+3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on.
	70	+
	71	+Alternate NOR bank
	72	+==================
	73	+There are four banks in C29XPCIE board, example to change bank booting:
	74	+1. Program u-boot.bin into alternate NOR bank
	75	+ => tftp $loadaddr $uboot
	76	+ => protect off e9f80000 +$filesize
	77	+ => erase e9f80000 +$filesize
	78	+ => cp.b $loadaddr e9f80000 $filesize
	79	+
	80	+2. Switch to alternate NOR bank
	81	+ => cpld_cmd reset altbank [bank]
	82	+ - [bank] bank value select 1-4
	83	+ - bank 1 on the flash 0x0000000~0x0ffffff
	84	+ - bank 2 on the flash 0x1000000~0x1ffffff
	85	+ - bank 3 on the flash 0x2000000~0x2ffffff
	86	+ - bank 4 on the flash 0x3000000~0x3ffffff
	87	+ or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again.
	88	+
	89	+Build and program u-boot to SPI flash
	90	+==================================
	91	+1. Build u-boot-spi.bin image
	92	+ make C29xPCIE_SPIFLASH_config; make
	93	+ Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin.
	94	+
	95	+2. Program u-boot-spi.bin into SPI flash
	96	+ => tftp $loadaddr $uboot-spi
	97	+ => sf erase 0 100000
	98	+ => sf write $loadaddr 0 $filesize
	99	+
	100	+3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on.
	1	+/*
	2	+ * Freescale USB Controller
	3	+ *
	4	+ * Copyright 2013 Freescale Semiconductor, Inc.
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef _ASM_FSL_USB_H_
	10	+#define _ASM_FSL_USB_H_
	11	+
	12	+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
	13	+struct ccsr_usb_port_ctrl {
	14	+ u32 ctrl;
	15	+ u32 drvvbuscfg;
	16	+ u32 pwrfltcfg;
	17	+ u32 sts;
	18	+ u8 res_14[0xc];
	19	+ u32 bistcfg;
	20	+ u32 biststs;
	21	+ u32 abistcfg;
	22	+ u32 abiststs;
	23	+ u8 res_30[0x10];
	24	+ u32 xcvrprg;
	25	+ u32 anaprg;
	26	+ u32 anadrv;
	27	+ u32 anasts;
	28	+};
	29	+
	30	+struct ccsr_usb_phy {
	31	+ u32 id;
	32	+ struct ccsr_usb_port_ctrl port1;
	33	+ u8 res_50[0xc];
	34	+ u32 tvr;
	35	+ u32 pllprg[4];
	36	+ u8 res_70[0x4];
	37	+ u32 anaccfg;
	38	+ u32 dbg;
	39	+ u8 res_7c[0x4];
	40	+ struct ccsr_usb_port_ctrl port2;
	41	+ u8 res_dc[0x334];
	42	+};
	43	+
	44	+#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
	45	+#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
	46	+#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
	47	+#define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
	48	+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
	49	+#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
	50	+#define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
	51	+#define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
	52	+#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
	53	+#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
	54	+#define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
	55	+#else
	56	+struct ccsr_usb_phy {
	57	+ u8 res0[0x18];
	58	+ u32 usb_enable_override;
	59	+ u8 res[0xe4];
	60	+};
	61	+#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
	62	+#endif
	63	+
	64	+#endif /_ASM_FSL_USB_H_ /