Eric Lee / smarc-uboot | Embedian Git Server

Commit 120b5ef2876c3a3aa2addaba0179791ddcbe8b58

Authored by Alex Marginean 2019-07-03 17:11:40 +0800

Committed by Joe Hershberger 2019-07-26 02:13:30 +0800

Exists in smarc_8mq_lf_v2020.04 and in 11 other branches

drivers: net: add NXP ENETC ethernet driver

Adds a driver for NXP ENETC ethernet controller currently integrated in
LS1028A.  ENETC is a fairly straight-forward BD ring device and interfaces
are presented as PCI EPs on the SoC ECAM.

Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Showing 4 changed files with 556 additions and 0 deletions Inline Diff

drivers/net/Kconfig
drivers/net/Makefile
drivers/net/fsl_enetc.c
drivers/net/fsl_enetc.h

drivers/net/Kconfig

Diff comments View file @ 120b5ef

 source "drivers/net/phy/Kconfig"
 source "drivers/net/pfe_eth/Kconfig"
 config DM_ETH
 	bool "Enable Driver Model for Ethernet drivers"
 	depends on DM
 	help
 	  Enable driver model for Ethernet.
 	  The eth_*() interface will be implemented by the UCLASS_ETH class
 	  This is currently implemented in net/eth-uclass.c
 	  Look in include/net.h for details.
 config DM_MDIO
 	bool "Enable Driver Model for MDIO devices"
 	depends on DM_ETH && PHYLIB
 	help
 	  Enable driver model for MDIO devices
 	  Adds UCLASS_MDIO DM class supporting MDIO buses that are probed as
 	  stand-alone devices.  Useful in particular for systems that support
 	  DM_ETH and have a stand-alone MDIO hardware block shared by multiple
 	  Ethernet interfaces.
 	  This is currently implemented in net/mdio-uclass.c
 	  Look in include/miiphy.h for details.
 config DM_MDIO_MUX
 	bool "Enable Driver Model for MDIO MUX devices"
 	depends on DM_MDIO
 	help
 	  Enable driver model for MDIO MUX devices
 	  Adds UCLASS_MDIO_MUX DM class supporting MDIO MUXes.  Useful for
 	  systems that support DM_MDIO and integrate one or multiple muxes on
 	  the MDIO bus.
 	  This is currently implemented in net/mdio-mux-uclass.c
 	  Look in include/miiphy.h for details.
 config MDIO_SANDBOX
 	depends on DM_MDIO && SANDBOX
 	default y
 	bool "Sandbox: Mocked MDIO driver"
 	help
 	  This driver implements dummy read/write/reset MDIO functions mimicking
 	  a bus with a single PHY.
 	  This driver is used in for testing in test/dm/mdio.c
 config MDIO_MUX_SANDBOX
 	depends on DM_MDIO_MUX && MDIO_SANDBOX
 	default y
 	bool "Sandbox: Mocked MDIO-MUX driver"
 	help
 	  This driver implements dummy select/deselect ops mimicking a MUX on
 	  the MDIO bux.  It uses mdio_sandbox driver as parent MDIO.
 	  This driver is used for testing in test/dm/mdio.c
 menuconfig NETDEVICES
 	bool "Network device support"
 	depends on NET
 	default y if DM_ETH
 	help
 	  You must select Y to enable any network device support
 	  Generally if you have any networking support this is a given
 	  If unsure, say Y
 if NETDEVICES
 config PHY_GIGE
 	bool "Enable GbE PHY status parsing and configuration"
 	help
 	  Enables support for parsing the status output and for
 	  configuring GbE PHYs (affects the inner workings of some
 	  commands and miiphyutil.c).
 config AG7XXX
 	bool "Atheros AG7xxx Ethernet MAC support"
 	depends on DM_ETH && ARCH_ATH79
 	select PHYLIB
 	help
 	  This driver supports the Atheros AG7xxx Ethernet MAC. This MAC is
 	  present in the Atheros AR7xxx, AR9xxx and QCA9xxx MIPS chips.
 config ALTERA_TSE
 	bool "Altera Triple-Speed Ethernet MAC support"
 	depends on DM_ETH
 	select PHYLIB
 	help
 	  This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
 	  Please find details on the "Triple-Speed Ethernet MegaCore Function
 	  Resource Center" of Altera.
 config BCM_SF2_ETH
 	bool "Broadcom SF2 (Starfighter2) Ethernet support"
 	select PHYLIB
 	help
 	  This is an abstract framework which provides a generic interface
 	  to MAC and DMA management for multiple Broadcom SoCs such as
 	  Cygnus, NSP and bcm28155_ap platforms.
 config BCM_SF2_ETH_DEFAULT_PORT
 	int "Broadcom SF2 (Starfighter2) Ethernet default port number"
 	depends on BCM_SF2_ETH
 	default 0
 	help
 	  Default port number for the Starfighter2 ethernet driver.
 config BCM_SF2_ETH_GMAC
 	bool "Broadcom SF2 (Starfighter2) GMAC Ethernet support"
 	depends on BCM_SF2_ETH
 	help
 	  This flag enables the ethernet support for Broadcom platforms with
 	  GMAC such as Cygnus. This driver is based on the framework provided
 	  by the BCM_SF2_ETH driver.
 	  Say Y to any bcmcygnus based platforms.
 config BCM6348_ETH
 	bool "BCM6348 EMAC support"
 	depends on DM_ETH && ARCH_BMIPS
 	select DMA
 	select DMA_CHANNELS
 	select MII
 	select PHYLIB
 	help
 	  This driver supports the BCM6348 Ethernet MAC.
 config BCM6368_ETH
 	bool "BCM6368 EMAC support"
 	depends on DM_ETH && ARCH_BMIPS
 	select DMA
 	select MII
 	help
 	  This driver supports the BCM6368 Ethernet MAC.
 config DWC_ETH_QOS
 	bool "Synopsys DWC Ethernet QOS device support"
 	depends on DM_ETH
 	select PHYLIB
 	help
 	  This driver supports the Synopsys Designware Ethernet QOS (Quality
 	  Of Service) IP block. The IP supports many options for bus type,
 	  clocking/reset structure, and feature list. This driver currently
 	  supports the specific configuration used in NVIDIA's Tegra186 chip,
 	  but should be extensible to other combinations quite easily.
 config E1000
 	bool "Intel PRO/1000 Gigabit Ethernet support"
 	help
 	  This driver supports Intel(R) PRO/1000 gigabit ethernet family of
 	  adapters.  For more information on how to identify your adapter, go
 	  to the Adapter & Driver ID Guide at:
 	  <http://support.intel.com/support/network/adapter/pro100/21397.htm>
 config E1000_SPI_GENERIC
 	bool "Allow access to the Intel 8257x SPI bus"
 	depends on E1000
 	help
 	  Allow generic access to the SPI bus on the Intel 8257x, for
 	  example with the "sspi" command.
 config E1000_SPI
 	bool "Enable SPI bus utility code"
 	depends on E1000
 	help
 	  Utility code for direct access to the SPI bus on Intel 8257x.
 	  This does not do anything useful unless you set at least one
 	  of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC.
 config CMD_E1000
 	bool "Enable the e1000 command"
 	depends on E1000
 	help
 	  This enables the 'e1000' management command for E1000 devices. When
 	  used on devices with SPI support you can reprogram the EEPROM from
 	  U-Boot.
 config ETH_SANDBOX
 	depends on DM_ETH && SANDBOX
 	default y
 	bool "Sandbox: Mocked Ethernet driver"
 	help
 	  This driver simply responds with fake ARP replies and ping
 	  replies that are used to verify network stack functionality
 	  This driver is particularly useful in the test/dm/eth.c tests
 config ETH_SANDBOX_RAW
 	depends on DM_ETH && SANDBOX
 	default y
 	bool "Sandbox: Bridge to Linux Raw Sockets"
 	help
 	  This driver is a bridge from the bottom of the network stack
 	  in U-Boot to the RAW AF_PACKET API in Linux. This allows real
 	  network traffic to be tested from within sandbox. See
 	  board/sandbox/README.sandbox for more details.
 config ETH_DESIGNWARE
 	bool "Synopsys Designware Ethernet MAC"
 	select PHYLIB
 	imply ETH_DESIGNWARE_SOCFPGA if ARCH_SOCFPGA
 	help
 	  This MAC is present in SoCs from various vendors. It supports
 	  100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to
 	  provide the PHY (physical media interface).
 config ETH_DESIGNWARE_SOCFPGA
 	select REGMAP
 	select SYSCON
 	bool "Altera SoCFPGA extras for Synopsys Designware Ethernet MAC"
 	depends on DM_ETH && ETH_DESIGNWARE
 	help
 	  The Altera SoCFPGA requires additional configuration of the
 	  Altera system manager to correctly interface with the PHY.
 	  This code handles those SoC specifics.
 config ETHOC
 	bool "OpenCores 10/100 Mbps Ethernet MAC"
 	help
 	  This MAC is present in OpenRISC and Xtensa XTFPGA boards.
 config FEC_MXC_SHARE_MDIO
 	bool "Share the MDIO bus for FEC controller"
 	depends on FEC_MXC
 config FEC_MXC_MDIO_BASE
 	hex "MDIO base address for the FEC controller"
 	depends on FEC_MXC_SHARE_MDIO
 	help
 	  This specifies the MDIO registers base address. It is used when
 	  two FEC controllers share MDIO bus.
 config FEC_MXC
 	bool "FEC Ethernet controller"
 	depends on MX5 || MX6 || MX7 || IMX8 || VF610
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
 config FMAN_ENET
 	bool "Freescale FMan ethernet support"
 	depends on ARM || PPC
 	help
 	  This driver support the Freescale FMan Ethernet controller
 config FTMAC100
 	bool "Ftmac100 Ethernet Support"
 	help
 	  This MAC is present in Andestech SoCs.
 config FTGMAC100
 	bool "Ftgmac100 Ethernet Support"
 	depends on DM_ETH
 	select PHYLIB
 	help
 	  This driver supports the Faraday's FTGMAC100 Gigabit SoC
 	  Ethernet controller that can be found on Aspeed SoCs (which
 	  include NCSI).
 	  It is fully compliant with IEEE 802.3 specification for
 	  10/100 Mbps Ethernet and IEEE 802.3z specification for 1000
 	  Mbps Ethernet and includes Reduced Media Independent
 	  Interface (RMII) and Reduced Gigabit Media Independent
 	  Interface (RGMII) interfaces. It adopts an AHB bus interface
 	  and integrates a link list DMA engine with direct M-Bus
 	  accesses for transmitting and receiving packets. It has
 	  independent TX/RX fifos, supports half and full duplex (1000
 	  Mbps mode only supports full duplex), flow control for full
 	  duplex and backpressure for half duplex.
 	  The FTGMAC100 also implements IP, TCP, UDP checksum offloads
 	  and supports IEEE 802.1Q VLAN tag insertion and removal. It
 	  offers high-priority transmit queue for QoS and CoS
 	  applications.
 config MVGBE
 	bool "Marvell Orion5x/Kirkwood network interface support"
 	depends on KIRKWOOD || ORION5X
 	select PHYLIB if DM_ETH
 	help
 	  This driver supports the network interface units in the
 	  Marvell Orion5x and Kirkwood SoCs
 config MVNETA
 	bool "Marvell Armada XP/385/3700 network interface support"
 	depends on ARMADA_XP || ARMADA_38X || ARMADA_3700
 	select PHYLIB
 	help
 	  This driver supports the network interface units in the
 	  Marvell ARMADA XP, ARMADA 38X and ARMADA 3700 SoCs
 config MVPP2
 	bool "Marvell Armada 375/7K/8K network interface support"
 	depends on ARMADA_375 || ARMADA_8K
 	select PHYLIB
 	help
 	  This driver supports the network interface units in the
 	  Marvell ARMADA 375, 7K and 8K SoCs.
 config MACB
 	bool "Cadence MACB/GEM Ethernet Interface"
 	depends on DM_ETH
 	select PHYLIB
 	help
 	  The Cadence MACB ethernet interface is found on many Atmel
 	  AT91 and SAMA5 parts.  This driver also supports the Cadence
 	  GEM (Gigabit Ethernet MAC) found in some ARM SoC devices.
 	  Say Y to include support for the MACB/GEM chip.
 config MACB_ZYNQ
 	bool "Cadence MACB/GEM Ethernet Interface for Xilinx Zynq"
 	depends on MACB
 	help
 	  The Cadence MACB ethernet interface was used on Zynq platform.
 	  Say Y to enable support for the MACB/GEM in Zynq chip.
 config MT7628_ETH
 	bool "MediaTek MT7628 Ethernet Interface"
 	depends on SOC_MT7628
 	help
 	  The MediaTek MT7628 ethernet interface is used on MT7628 and
 	  MT7688 based boards.
 config PCH_GBE
 	bool "Intel Platform Controller Hub EG20T GMAC driver"
 	depends on DM_ETH && DM_PCI
 	select PHYLIB
 	help
 	  This MAC is present in Intel Platform Controller Hub EG20T. It
 	  supports 10/100/1000 Mbps operation.
 config RGMII
 	bool "Enable RGMII"
 	help
 	  Enable the support of the Reduced Gigabit Media-Independent
 	  Interface (RGMII).
 config MII
 	bool "Enable MII"
 	help
 	  Enable support of the Media-Independent Interface (MII)
 config RTL8139
 	bool "Realtek 8139 series Ethernet controller driver"
 	help
 	  This driver supports Realtek 8139 series fast ethernet family of
 	  PCI chipsets/adapters.
 config RTL8169
 	bool "Realtek 8169 series Ethernet controller driver"
 	help
 	  This driver supports Realtek 8169 series gigabit ethernet family of
 	  PCI/PCIe chipsets/adapters.
 config SMC911X
 	bool "SMSC LAN911x and LAN921x controller driver"
 if SMC911X
 config SMC911X_BASE
 	hex "SMC911X Base Address"
 	help
 	  Define this to hold the physical address
 	  of the device (I/O space)
 choice
 	prompt "SMC911X bus width"
 	default SMC911X_16_BIT
 config SMC911X_32_BIT
 	bool "Enable 32-bit interface"
 config SMC911X_16_BIT
 	bool "Enable 16-bit interface"
 	help
 	  Define this if data bus is 16 bits. If your processor
 	  automatically converts one 32 bit word to two 16 bit
 	  words you may also try CONFIG_SMC911X_32_BIT.
 endchoice
 endif #SMC911X
 config SUN7I_GMAC
 	bool "Enable Allwinner GMAC Ethernet support"
 	help
 	  Enable the support for Sun7i GMAC Ethernet controller
 config SUN7I_GMAC_FORCE_TXERR
 	bool "Force PA17 as gmac function"
 	depends on SUN7I_GMAC
 	help
 	  Some ethernet phys needs TXERR control. Since the GMAC
 	  doesn't have such signal, setting PA17 as GMAC function
 	  makes the pin output low, which enables data transmission.
 config SUN4I_EMAC
 	bool "Allwinner Sun4i Ethernet MAC support"
 	depends on DM_ETH
 	select PHYLIB
 	help
 	  This driver supports the Allwinner based SUN4I Ethernet MAC.
 config SUN8I_EMAC
         bool "Allwinner Sun8i Ethernet MAC support"
         depends on DM_ETH
         select PHYLIB
 	select PHY_GIGE
         help
           This driver supports the  Allwinner based SUN8I/SUN50I Ethernet MAC.
 	  It can be found in H3/A64/A83T based SoCs and compatible with both
 	  External and Internal PHYs.
 config SH_ETHER
 	bool "Renesas SH Ethernet MAC"
 	select PHYLIB
 	help
 	  This driver supports the Ethernet for Renesas SH and ARM SoCs.
 source "drivers/net/ti/Kconfig"
 config XILINX_AXIEMAC
 	depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
 	select PHYLIB
 	select MII
 	bool "Xilinx AXI Ethernet"
 	help
 	  This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
 config XILINX_EMACLITE
 	depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || MIPS)
 	select PHYLIB
 	select MII
 	bool "Xilinx Ethernetlite"
 	help
 	  This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
 config ZYNQ_GEM
 	depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
 	select PHYLIB
 	bool "Xilinx Ethernet GEM"
 	help
 	  This MAC is present in Xilinx Zynq and ZynqMP SoCs.
 config PIC32_ETH
 	bool "Microchip PIC32 Ethernet Support"
 	depends on DM_ETH && MACH_PIC32
 	select PHYLIB
 	help
 	  This driver implements 10/100 Mbps Ethernet and MAC layer for
 	  Microchip PIC32 microcontrollers.
 config GMAC_ROCKCHIP
 	bool "Rockchip Synopsys Designware Ethernet MAC"
 	depends on DM_ETH && ETH_DESIGNWARE
 	help
 	  This driver provides Rockchip SoCs network support based on the
 	  Synopsys Designware driver.
 config RENESAS_RAVB
 	bool "Renesas Ethernet AVB MAC"
 	depends on DM_ETH && RCAR_GEN3
 	select PHYLIB
 	help
 	  This driver implements support for the Ethernet AVB block in
 	  Renesas M3 and H3 SoCs.
 config MPC8XX_FEC
 	bool "Fast Ethernet Controller on MPC8XX"
 	depends on MPC8xx
 	select MII
 	help
 	  This driver implements support for the Fast Ethernet Controller
 	  on MPC8XX
 config SNI_AVE
 	bool "Socionext AVE Ethernet support"
 	depends on DM_ETH && ARCH_UNIPHIER
 	select PHYLIB
 	select SYSCON
 	select REGMAP
 	help
 	  This driver implements support for the Socionext AVE Ethernet
 	  controller, as found on the Socionext UniPhier family.
 source "drivers/net/mscc_eswitch/Kconfig"
 config ETHER_ON_FEC1
 	bool "FEC1"
 	depends on MPC8XX_FEC
 	default y
 config FEC1_PHY
 	int "FEC1 PHY"
 	depends on ETHER_ON_FEC1
 	default -1
 	help
 	  Define to the hardcoded PHY address which corresponds
 	  to the given FEC; i. e.
 		#define CONFIG_FEC1_PHY 4
 	  means that the PHY with address 4 is connected to FEC1
 	  When set to -1, means to probe for first available.
 config PHY_NORXERR
 	bool "PHY_NORXERR"
 	depends on ETHER_ON_FEC1
 	default n
 	help
 	  The PHY does not have a RXERR line (RMII only).
 	  (so program the FEC to ignore it).
 config ETHER_ON_FEC2
 	bool "FEC2"
 	depends on MPC8XX_FEC && MPC885
 	default y
 config FEC2_PHY
 	int "FEC2 PHY"
 	depends on ETHER_ON_FEC2
 	default -1
 	help
 	  Define to the hardcoded PHY address which corresponds
 	  to the given FEC; i. e.
 		#define CONFIG_FEC1_PHY 4
 	  means that the PHY with address 4 is connected to FEC1
 	  When set to -1, means to probe for first available.
 config FEC2_PHY_NORXERR
 	bool "PHY_NORXERR"
 	depends on ETHER_ON_FEC2
 	default n
 	help
 	  The PHY does not have a RXERR line (RMII only).
 	  (so program the FEC to ignore it).
 config SYS_DPAA_QBMAN
 	bool "Device tree fixup for QBMan on freescale SOCs"
 	depends on (ARM || PPC) && !SPL_BUILD
 	default y if ARCH_B4860 || \
 		     ARCH_B4420 || \
 		     ARCH_P1023 || \
 		     ARCH_P2041 || \
 		     ARCH_T1023 || \
 		     ARCH_T1024 || \
 		     ARCH_T1040 || \
 		     ARCH_T1042 || \
 		     ARCH_T2080 || \
 		     ARCH_T2081 || \
 		     ARCH_T4240 || \
 		     ARCH_T4160 || \
 		     ARCH_P4080 || \
 		     ARCH_P3041 || \
 		     ARCH_P5040 || \
 		     ARCH_P5020 || \
 		     ARCH_LS1043A || \
 		     ARCH_LS1046A
 	help
 	  QBman fixups to allow deep sleep in DPAA 1 SOCs
 config TSEC_ENET
 	select PHYLIB
 	bool "Enable Three-Speed Ethernet Controller"
 	help
 	  This driver implements support for the (Enhanced) Three-Speed
 	  Ethernet Controller found on Freescale SoCs.
 config MEDIATEK_ETH
 	bool "MediaTek Ethernet GMAC Driver"
 	depends on DM_ETH
 	select PHYLIB
 	select DM_GPIO
 	select DM_RESET
 	help
 	  This Driver support MediaTek Ethernet GMAC
 	  Say Y to enable support for the MediaTek Ethernet GMAC.
 config HIGMACV300_ETH
 	bool "HiSilicon Gigabit Ethernet Controller"
 	depends on DM_ETH
 	select DM_RESET
 	select PHYLIB
 	help
 	  This driver supports HIGMACV300 Ethernet controller found on
 	  HiSilicon SoCs.
+config FSL_ENETC
+	bool "NXP ENETC Ethernet controller"
+	depends on DM_PCI && DM_ETH
+	help
+	  This driver supports the NXP ENETC Ethernet controller found on some
+	  of the NXP SoCs.
 endif # NETDEVICES

drivers/net/Makefile

Diff comments View file @ 120b5ef

 # SPDX-License-Identifier: GPL-2.0+
 #
 # (C) Copyright 2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 obj-$(CONFIG_ALTERA_TSE) += altera_tse.o
 obj-$(CONFIG_AG7XXX) += ag7xxx.o
 obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
 obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o
 obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o
 obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
 obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
 obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
 obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
 obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
 obj-$(CONFIG_CS8900) += cs8900.o
 obj-$(CONFIG_TULIP) += dc2114x.o
 obj-$(CONFIG_ETH_DESIGNWARE) += designware.o
 obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o
 obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 obj-$(CONFIG_DNET) += dnet.o
 obj-$(CONFIG_E1000) += e1000.o
 obj-$(CONFIG_E1000_SPI) += e1000_spi.o
 obj-$(CONFIG_EEPRO100) += eepro100.o
 obj-$(CONFIG_SUN4I_EMAC) += sunxi_emac.o
 obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o
 obj-$(CONFIG_EP93XX) += ep93xx_eth.o
 obj-$(CONFIG_ETHOC) += ethoc.o
 obj-$(CONFIG_FEC_MXC) += fec_mxc.o
 obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o
 obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o
 obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
 obj-$(CONFIG_MACB) += macb.o
 obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
 obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
 obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
 obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
 obj-$(CONFIG_MVGBE) += mvgbe.o
 obj-$(CONFIG_MVNETA) += mvneta.o
 obj-$(CONFIG_MVPP2) += mvpp2.o
 obj-$(CONFIG_NATSEMI) += natsemi.o
 obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
 obj-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
 obj-$(CONFIG_NETCONSOLE) += netconsole.o
 obj-$(CONFIG_NS8382X) += ns8382x.o
 obj-$(CONFIG_PCH_GBE) += pch_gbe.o
 obj-$(CONFIG_PCNET) += pcnet.o
 obj-$(CONFIG_RTL8139) += rtl8139.o
 obj-$(CONFIG_RTL8169) += rtl8169.o
 obj-$(CONFIG_ETH_SANDBOX) += sandbox.o
 obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o
 obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw-bus.o
 obj-$(CONFIG_SH_ETHER) += sh_eth.o
 obj-$(CONFIG_RENESAS_RAVB) += ravb.o
 obj-$(CONFIG_SMC91111) += smc91111.o
 obj-$(CONFIG_SMC911X) += smc911x.o
 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
 obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
 obj-$(CONFIG_ULI526X) += uli526x.o
 obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
 obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
 obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
 obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o
 obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
 obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
 obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
 obj-$(CONFIG_VSC9953) += vsc9953.o
 obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
 obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_FSL_PFE) += pfe_eth/
 obj-$(CONFIG_SNI_AVE) += sni_ave.o
 obj-y += ti/
 obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
 obj-y += mscc_eswitch/
 obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
 obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
+obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o

drivers/net/fsl_enetc.c

Diff comments View file @ 120b5ef

File was created	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* ENETC ethernet controller driver
	4	* Copyright 2017-2019 NXP
	5	*/
	6
	7	#include <common.h>
	8	#include <dm.h>
	9	#include <errno.h>
	10	#include <memalign.h>
	11	#include <asm/io.h>
	12	#include <pci.h>
	13
	14	#include "fsl_enetc.h"
	15
	16	/*
	17	* Bind the device:
	18	* - set a more explicit name on the interface
	19	*/
	20	static int enetc_bind(struct udevice *dev)
	21	{
	22	char name[16];
	23	static int eth_num_devices;
	24
	25	/*
	26	* prefer using PCI function numbers to number interfaces, but these
	27	* are only available if dts nodes are present. For PCI they are
	28	* optional, handle that case too. Just in case some nodes are present
	29	* and some are not, use different naming scheme - enetc-N based on
	30	* PCI function # and enetc#N based on interface count
	31	*/
	32	if (ofnode_valid(dev->node))
	33	sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
	34	else
	35	sprintf(name, "enetc#%u", eth_num_devices++);
	36	device_set_name(dev, name);
	37
	38	return 0;
	39	}
	40
	41	/*
	42	* Probe ENETC driver:
	43	* - initialize port and station interface BARs
	44	*/
	45	static int enetc_probe(struct udevice *dev)
	46	{
	47	struct enetc_priv *priv = dev_get_priv(dev);
	48
	49	if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
	50	enetc_dbg(dev, "interface disabled\n");
	51	return -ENODEV;
	52	}
	53
	54	priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
	55	sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
	56	priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
	57	sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
	58
	59	if (!priv->enetc_txbd \|\| !priv->enetc_rxbd) {
	60	/* free should be able to handle NULL, just free all pointers */
	61	free(priv->enetc_txbd);
	62	free(priv->enetc_rxbd);
	63
	64	return -ENOMEM;
	65	}
	66
	67	/* initialize register */
	68	priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
	69	if (!priv->regs_base) {
	70	enetc_dbg(dev, "failed to map BAR0\n");
	71	return -EINVAL;
	72	}
	73	priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
	74
	75	dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
	76
	77	return 0;
	78	}
	79
	80	/*
	81	* Remove the driver from an interface:
	82	* - free up allocated memory
	83	*/
	84	static int enetc_remove(struct udevice *dev)
	85	{
	86	struct enetc_priv *priv = dev_get_priv(dev);
	87
	88	free(priv->enetc_txbd);
	89	free(priv->enetc_rxbd);
	90
	91	return 0;
	92	}
	93
	94	/* ENETC Port MAC address registers, accepts big-endian format */
	95	static void enetc_set_primary_mac_addr(struct enetc_priv priv, const u8 addr)
	96	{
	97	u16 lower = (const u16 )(addr + 4);
	98	u32 upper = (const u32 )addr;
	99
	100	enetc_write_port(priv, ENETC_PSIPMAR0, upper);
	101	enetc_write_port(priv, ENETC_PSIPMAR1, lower);
	102	}
	103
	104	/* Configure port parameters (# of rings, frame size, enable port) */
	105	static void enetc_enable_si_port(struct enetc_priv *priv)
	106	{
	107	u32 val;
	108
	109	/* set Rx/Tx BDR count */
	110	val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
	111	val \|= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
	112	enetc_write_port(priv, ENETC_PSICFGR(0), val);
	113	/* set Rx max frame size */
	114	enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
	115	/* enable MAC port */
	116	enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
	117	/* enable port */
	118	enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
	119	/* set SI cache policy */
	120	enetc_write(priv, ENETC_SICAR0,
	121	ENETC_SICAR_RD_CFG \| ENETC_SICAR_WR_CFG);
	122	/* enable SI */
	123	enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
	124	}
	125
	126	/* returns DMA address for a given buffer index */
	127	static inline u64 enetc_rxb_address(struct udevice *dev, int i)
	128	{
	129	return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
	130	}
	131
	132	/*
	133	* Setup a single Tx BD Ring (ID = 0):
	134	* - set Tx buffer descriptor address
	135	* - set the BD count
	136	* - initialize the producer and consumer index
	137	*/
	138	static void enetc_setup_tx_bdr(struct udevice *dev)
	139	{
	140	struct enetc_priv *priv = dev_get_priv(dev);
	141	struct bd_ring *tx_bdr = &priv->tx_bdr;
	142	u64 tx_bd_add = (u64)priv->enetc_txbd;
	143
	144	/* used later to advance to the next Tx BD */
	145	tx_bdr->bd_count = ENETC_BD_CNT;
	146	tx_bdr->next_prod_idx = 0;
	147	tx_bdr->next_cons_idx = 0;
	148	tx_bdr->cons_idx = priv->regs_base +
	149	ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
	150	tx_bdr->prod_idx = priv->regs_base +
	151	ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
	152
	153	/* set Tx BD address */
	154	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
	155	lower_32_bits(tx_bd_add));
	156	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
	157	upper_32_bits(tx_bd_add));
	158	/* set Tx 8 BD count */
	159	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
	160	tx_bdr->bd_count);
	161
	162	/* reset both producer/consumer indexes */
	163	enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
	164	enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
	165
	166	/* enable TX ring */
	167	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
	168	}
	169
	170	/*
	171	* Setup a single Rx BD Ring (ID = 0):
	172	* - set Rx buffer descriptors address (one descriptor per buffer)
	173	* - set buffer size as max frame size
	174	* - enable Rx ring
	175	* - reset consumer and producer indexes
	176	* - set buffer for each descriptor
	177	*/
	178	static void enetc_setup_rx_bdr(struct udevice *dev)
	179	{
	180	struct enetc_priv *priv = dev_get_priv(dev);
	181	struct bd_ring *rx_bdr = &priv->rx_bdr;
	182	u64 rx_bd_add = (u64)priv->enetc_rxbd;
	183	int i;
	184
	185	/* used later to advance to the next BD produced by ENETC HW */
	186	rx_bdr->bd_count = ENETC_BD_CNT;
	187	rx_bdr->next_prod_idx = 0;
	188	rx_bdr->next_cons_idx = 0;
	189	rx_bdr->cons_idx = priv->regs_base +
	190	ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
	191	rx_bdr->prod_idx = priv->regs_base +
	192	ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
	193
	194	/* set Rx BD address */
	195	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
	196	lower_32_bits(rx_bd_add));
	197	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
	198	upper_32_bits(rx_bd_add));
	199	/* set Rx BD count (multiple of 8) */
	200	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
	201	rx_bdr->bd_count);
	202	/* set Rx buffer size */
	203	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
	204
	205	/* fill Rx BD */
	206	memset(priv->enetc_rxbd, 0,
	207	rx_bdr->bd_count * sizeof(union enetc_rx_bd));
	208	for (i = 0; i < rx_bdr->bd_count; i++) {
	209	priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
	210	/* each RX buffer must be aligned to 64B */
	211	WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
	212	}
	213
	214	/* reset producer (ENETC owned) and consumer (SW owned) index */
	215	enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
	216	enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
	217
	218	/* enable Rx ring */
	219	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
	220	}
	221
	222	/*
	223	* Start ENETC interface:
	224	* - perform FLR
	225	* - enable access to port and SI registers
	226	* - set mac address
	227	* - setup TX/RX buffer descriptors
	228	* - enable Tx/Rx rings
	229	*/
	230	static int enetc_start(struct udevice *dev)
	231	{
	232	struct eth_pdata *plat = dev_get_platdata(dev);
	233	struct enetc_priv *priv = dev_get_priv(dev);
	234
	235	/* reset and enable the PCI device */
	236	dm_pci_flr(dev);
	237	dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
	238	PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	239
	240	if (!is_valid_ethaddr(plat->enetaddr)) {
	241	enetc_dbg(dev, "invalid MAC address, generate random ...\n");
	242	net_random_ethaddr(plat->enetaddr);
	243	}
	244	enetc_set_primary_mac_addr(priv, plat->enetaddr);
	245
	246	enetc_enable_si_port(priv);
	247
	248	/* setup Tx/Rx buffer descriptors */
	249	enetc_setup_tx_bdr(dev);
	250	enetc_setup_rx_bdr(dev);
	251
	252	return 0;
	253	}
	254
	255	/*
	256	* Stop the network interface:
	257	* - just quiesce it, we can wipe all configuration as _start starts from
	258	* scratch each time
	259	*/
	260	static void enetc_stop(struct udevice *dev)
	261	{
	262	/* FLR is sufficient to quiesce the device */
	263	dm_pci_flr(dev);
	264	}
	265
	266	/*
	267	* ENETC transmit packet:
	268	* - check if Tx BD ring is full
	269	* - set buffer/packet address (dma address)
	270	* - set final fragment flag
	271	* - try while producer index equals consumer index or timeout
	272	*/
	273	static int enetc_send(struct udevice dev, void packet, int length)
	274	{
	275	struct enetc_priv *priv = dev_get_priv(dev);
	276	struct bd_ring *txr = &priv->tx_bdr;
	277	void nv_packet = (void )packet;
	278	int tries = ENETC_POLL_TRIES;
	279	u32 pi, ci;
	280
	281	pi = txr->next_prod_idx;
	282	ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
	283	/* Tx ring is full when */
	284	if (((pi + 1) % txr->bd_count) == ci) {
	285	enetc_dbg(dev, "Tx BDR full\n");
	286	return -ETIMEDOUT;
	287	}
	288	enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
	289	upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
	290
	291	/* prepare Tx BD */
	292	memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
	293	priv->enetc_txbd[pi].addr =
	294	cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
	295	priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
	296	priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
	297	priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
	298	dmb();
	299	/* send frame: increment producer index */
	300	pi = (pi + 1) % txr->bd_count;
	301	txr->next_prod_idx = pi;
	302	enetc_write_reg(txr->prod_idx, pi);
	303	while ((--tries >= 0) &&
	304	(pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
	305	udelay(10);
	306
	307	return tries > 0 ? 0 : -ETIMEDOUT;
	308	}
	309
	310	/*
	311	* Receive frame:
	312	* - wait for the next BD to get ready bit set
	313	* - clean up the descriptor
	314	* - move on and indicate to HW that the cleaned BD is available for Rx
	315	*/
	316	static int enetc_recv(struct udevice dev, int flags, uchar *packetp)
	317	{
	318	struct enetc_priv *priv = dev_get_priv(dev);
	319	struct bd_ring *rxr = &priv->rx_bdr;
	320	int tries = ENETC_POLL_TRIES;
	321	int pi = rxr->next_prod_idx;
	322	int ci = rxr->next_cons_idx;
	323	u32 status;
	324	int len;
	325	u8 rdy;
	326
	327	do {
	328	dmb();
	329	status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
	330	/* check if current BD is ready to be consumed */
	331	rdy = ENETC_RXBD_STATUS_R(status);
	332	} while (--tries >= 0 && !rdy);
	333
	334	if (!rdy)
	335	return -EAGAIN;
	336
	337	dmb();
	338	len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
	339	packetp = (uchar )enetc_rxb_address(dev, pi);
	340	enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
	341	ENETC_RXBD_STATUS_ERRORS(status),
	342	upper_32_bits((u64)packetp), lower_32_bits((u64)packetp));
	343
	344	/* BD clean up and advance to next in ring */
	345	memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
	346	priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
	347	rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
	348	ci = (ci + 1) % rxr->bd_count;
	349	rxr->next_cons_idx = ci;
	350	dmb();
	351	/* free up the slot in the ring for HW */
	352	enetc_write_reg(rxr->cons_idx, ci);
	353
	354	return len;
	355	}
	356
	357	static const struct eth_ops enetc_ops = {
	358	.start = enetc_start,
	359	.send = enetc_send,
	360	.recv = enetc_recv,
	361	.stop = enetc_stop,
	362	};
	363
	364	U_BOOT_DRIVER(eth_enetc) = {
	365	.name = "enetc_eth",
	366	.id = UCLASS_ETH,
	367	.bind = enetc_bind,
	368	.probe = enetc_probe,
	369	.remove = enetc_remove,
	370	.ops = &enetc_ops,
	371	.priv_auto_alloc_size = sizeof(struct enetc_priv),
	372	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	373	};
	374
	375	static struct pci_device_id enetc_ids[] = {
	376	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
	377	{}
	378	};
	379
	380	U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
	381

drivers/net/fsl_enetc.h

Diff comments View file @ 120b5ef

File was created	1	/* SPDX-License-Identifier: GPL-2.0+ */
	2	/*
	3	* ENETC ethernet controller driver
	4	* Copyright 2017-2019 NXP
	5	*/
	6
	7	#ifndef _ENETC_H
	8	#define _ENETC_H
	9
	10	#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
	11
	12	/* PCI function IDs */
	13	#define PCI_DEVICE_ID_ENETC_ETH 0xE100
	14
	15	/* ENETC Ethernet controller registers */
	16	/* Station interface register offsets */
	17	#define ENETC_SIMR 0x000
	18	#define ENETC_SIMR_EN BIT(31)
	19	#define ENETC_SICAR0 0x040
	20	/* write cache cfg: snoop, no allocate, data & BD coherent */
	21	#define ENETC_SICAR_WR_CFG 0x6767
	22	/* read cache cfg: coherent copy, look up, don't alloc in cache */
	23	#define ENETC_SICAR_RD_CFG 0x27270000
	24	#define ENETC_SIROCT 0x300
	25	#define ENETC_SIRFRM 0x308
	26	#define ENETC_SITOCT 0x320
	27	#define ENETC_SITFRM 0x328
	28
	29	/* Rx/Tx Buffer Descriptor Ring registers */
	30	enum enetc_bdr_type {TX, RX};
	31	#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
	32	#define ENETC_BDR_IDX_MASK 0xffff
	33
	34	/* Rx BDR reg offsets */
	35	#define ENETC_RBMR 0x00
	36	#define ENETC_RBMR_EN BIT(31)
	37	#define ENETC_RBBSR 0x08
	38	/* initial consumer index for Rx BDR */
	39	#define ENETC_RBCIR 0x0c
	40	#define ENETC_RBBAR0 0x10
	41	#define ENETC_RBBAR1 0x14
	42	#define ENETC_RBPIR 0x18
	43	#define ENETC_RBLENR 0x20
	44
	45	/* Tx BDR reg offsets */
	46	#define ENETC_TBMR 0x00
	47	#define ENETC_TBMR_EN BIT(31)
	48	#define ENETC_TBBAR0 0x10
	49	#define ENETC_TBBAR1 0x14
	50	#define ENETC_TBPIR 0x18
	51	#define ENETC_TBCIR 0x1c
	52	#define ENETC_TBLENR 0x20
	53
	54	/* Port registers offset */
	55	#define ENETC_PORT_REGS_OFF 0x10000
	56
	57	/* Port registers */
	58	#define ENETC_PMR 0x0000
	59	#define ENETC_PMR_SI0_EN BIT(16)
	60	#define ENETC_PSIPMMR 0x0018
	61	#define ENETC_PSIPMAR0 0x0100
	62	#define ENETC_PSIPMAR1 0x0104
	63	#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
	64	#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
	65	#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
	66	/* MAC configuration */
	67	#define ENETC_PM_CC 0x8008
	68	#define ENETC_PM_CC_DEFAULT 0x0810
	69	#define ENETC_PM_CC_RX_TX_EN 0x8813
	70	#define ENETC_PM_MAXFRM 0x8014
	71	#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
	72
	73	/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
	74	#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
	75	#define ENETC_BD_ALIGN 128
	76
	77	/* single pair of Rx/Tx rings */
	78	#define ENETC_RX_BDR_CNT 1
	79	#define ENETC_TX_BDR_CNT 1
	80	#define ENETC_RX_BDR_ID 0
	81	#define ENETC_TX_BDR_ID 0
	82
	83	/* Tx buffer descriptor */
	84	struct enetc_tx_bd {
	85	__le64 addr;
	86	__le16 buf_len;
	87	__le16 frm_len;
	88	__le16 err_csum;
	89	__le16 flags;
	90	};
	91
	92	#define ENETC_TXBD_FLAGS_F BIT(15)
	93	#define ENETC_POLL_TRIES 32000
	94
	95	/* Rx buffer descriptor */
	96	union enetc_rx_bd {
	97	/* SW provided BD format */
	98	struct {
	99	__le64 addr;
	100	u8 reserved[8];
	101	} w;
	102
	103	/* ENETC returned BD format */
	104	struct {
	105	__le16 inet_csum;
	106	__le16 parse_summary;
	107	__le32 rss_hash;
	108	__le16 buf_len;
	109	__le16 vlan_opt;
	110	union {
	111	struct {
	112	__le16 flags;
	113	__le16 error;
	114	};
	115	__le32 lstatus;
	116	};
	117	} r;
	118	};
	119
	120	#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
	121	#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
	122	#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
	123	#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
	124
	125	/* Tx/Rx ring info */
	126	struct bd_ring {
	127	void *cons_idx;
	128	void *prod_idx;
	129	/* next BD index to use */
	130	int next_prod_idx;
	131	int next_cons_idx;
	132	int bd_count;
	133	};
	134
	135	/* ENETC private structure */
	136	struct enetc_priv {
	137	struct enetc_tx_bd *enetc_txbd;
	138	union enetc_rx_bd *enetc_rxbd;
	139
	140	void regs_base; / base ENETC registers */
	141	void port_regs; / base ENETC port registers */
	142
	143	/* Rx/Tx buffer descriptor rings info */
	144	struct bd_ring tx_bdr;
	145	struct bd_ring rx_bdr;
	146	};
	147
	148	/* register accessors */
	149	#define enetc_read_reg(x) readl((x))
	150	#define enetc_write_reg(x, val) writel((val), (x))
	151	#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
	152	#define enetc_write(priv, off, v) \
	153	enetc_write_reg((priv)->regs_base + (off), v)
	154
	155	/* port register accessors */
	156	#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
	157	#define enetc_read_port(priv, off) \
	158	enetc_read_reg(enetc_port_regs((priv), (off)))
	159	#define enetc_write_port(priv, off, v) \
	160	enetc_write_reg(enetc_port_regs((priv), (off)), v)
	161
	162	/* BDR register accessors, see ENETC_BDR() */
	163	#define enetc_bdr_read(priv, t, n, off) \
	164	enetc_read(priv, ENETC_BDR(t, n, off))
	165	#define enetc_bdr_write(priv, t, n, off, val) \
	166	enetc_write(priv, ENETC_BDR(t, n, off), val)
	167
	168	#endif /* _ENETC_H */
	169