drivers: net: add NXP ENETC ethernet driver

Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers: net: add NXP ENETC ethernet driver
Adds a driver for NXP ENETC ethernet controller currently integrated in LS1028A. ENETC is a fairly straight-forward BD ring device and interfaces are presented as PCI EPs on the SoC ECAM. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean · Joe Hershberger
1 parent ff6c6b2d6d
Showing 4 changed files with 556 additions and 0 deletions Side-by-side Diff
drivers/net/Kconfig
drivers/net/Makefile
drivers/net/fsl_enetc.c
drivers/net/fsl_enetc.h
@@ -588,5 +588,12 @@
 	  This driver supports HIGMACV300 Ethernet controller found on
 	  HiSilicon SoCs.
  
+config FSL_ENETC
+	bool "NXP ENETC Ethernet controller"
+	depends on DM_PCI && DM_ETH
+	help
+	  This driver supports the NXP ENETC Ethernet controller found on some
+	  of the NXP SoCs.
+
 endif # NETDEVICES
@@ -79,4 +79,5 @@
 obj-y += mscc_eswitch/
 obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
 obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
+obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ENETC ethernet controller driver
+ * Copyright 2017-2019 NXP
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <memalign.h>
+#include <asm/io.h>
+#include <pci.h>
+
+#include "fsl_enetc.h"
+
+/*
+ * Bind the device:
+ * - set a more explicit name on the interface
+ */
+static int enetc_bind(struct udevice *dev)
+{
+	char name[16];
+	static int eth_num_devices;
+
+	/*
+	 * prefer using PCI function numbers to number interfaces, but these
+	 * are only available if dts nodes are present.  For PCI they are
+	 * optional, handle that case too.  Just in case some nodes are present
+	 * and some are not, use different naming scheme - enetc-N based on
+	 * PCI function # and enetc#N based on interface count
+	 */
+	if (ofnode_valid(dev->node))
+		sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
+	else
+		sprintf(name, "enetc#%u", eth_num_devices++);
+	device_set_name(dev, name);
+
+	return 0;
+}
+
+/*
+ * Probe ENETC driver:
+ * - initialize port and station interface BARs
+ */
+static int enetc_probe(struct udevice *dev)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+
+	if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
+		enetc_dbg(dev, "interface disabled\n");
+		return -ENODEV;
+	}
+
+	priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
+				    sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
+	priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
+				    sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
+
+	if (!priv->enetc_txbd || !priv->enetc_rxbd) {
+		/* free should be able to handle NULL, just free all pointers */
+		free(priv->enetc_txbd);
+		free(priv->enetc_rxbd);
+
+		return -ENOMEM;
+	}
+
+	/* initialize register */
+	priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
+	if (!priv->regs_base) {
+		enetc_dbg(dev, "failed to map BAR0\n");
+		return -EINVAL;
+	}
+	priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
+
+	dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
+
+	return 0;
+}
+
+/*
+ * Remove the driver from an interface:
+ * - free up allocated memory
+ */
+static int enetc_remove(struct udevice *dev)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+
+	free(priv->enetc_txbd);
+	free(priv->enetc_rxbd);
+
+	return 0;
+}
+
+/* ENETC Port MAC address registers, accepts big-endian format */
+static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
+{
+	u16 lower = *(const u16 *)(addr + 4);
+	u32 upper = *(const u32 *)addr;
+
+	enetc_write_port(priv, ENETC_PSIPMAR0, upper);
+	enetc_write_port(priv, ENETC_PSIPMAR1, lower);
+}
+
+/* Configure port parameters (# of rings, frame size, enable port) */
+static void enetc_enable_si_port(struct enetc_priv *priv)
+{
+	u32 val;
+
+	/* set Rx/Tx BDR count */
+	val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
+	val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
+	enetc_write_port(priv, ENETC_PSICFGR(0), val);
+	/* set Rx max frame size */
+	enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
+	/* enable MAC port */
+	enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
+	/* enable port */
+	enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
+	/* set SI cache policy */
+	enetc_write(priv, ENETC_SICAR0,
+		    ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
+	/* enable SI */
+	enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
+}
+
+/* returns DMA address for a given buffer index */
+static inline u64 enetc_rxb_address(struct udevice *dev, int i)
+{
+	return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
+}
+
+/*
+ * Setup a single Tx BD Ring (ID = 0):
+ * - set Tx buffer descriptor address
+ * - set the BD count
+ * - initialize the producer and consumer index
+ */
+static void enetc_setup_tx_bdr(struct udevice *dev)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+	struct bd_ring *tx_bdr = &priv->tx_bdr;
+	u64 tx_bd_add = (u64)priv->enetc_txbd;
+
+	/* used later to advance to the next Tx BD */
+	tx_bdr->bd_count = ENETC_BD_CNT;
+	tx_bdr->next_prod_idx = 0;
+	tx_bdr->next_cons_idx = 0;
+	tx_bdr->cons_idx = priv->regs_base +
+				ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
+	tx_bdr->prod_idx = priv->regs_base +
+				ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
+
+	/* set Tx BD address */
+	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
+			lower_32_bits(tx_bd_add));
+	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
+			upper_32_bits(tx_bd_add));
+	/* set Tx 8 BD count */
+	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
+			tx_bdr->bd_count);
+
+	/* reset both producer/consumer indexes */
+	enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
+	enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
+
+	/* enable TX ring */
+	enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
+}
+
+/*
+ * Setup a single Rx BD Ring (ID = 0):
+ * - set Rx buffer descriptors address (one descriptor per buffer)
+ * - set buffer size as max frame size
+ * - enable Rx ring
+ * - reset consumer and producer indexes
+ * - set buffer for each descriptor
+ */
+static void enetc_setup_rx_bdr(struct udevice *dev)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+	struct bd_ring *rx_bdr = &priv->rx_bdr;
+	u64 rx_bd_add = (u64)priv->enetc_rxbd;
+	int i;
+
+	/* used later to advance to the next BD produced by ENETC HW */
+	rx_bdr->bd_count = ENETC_BD_CNT;
+	rx_bdr->next_prod_idx = 0;
+	rx_bdr->next_cons_idx = 0;
+	rx_bdr->cons_idx = priv->regs_base +
+				ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
+	rx_bdr->prod_idx = priv->regs_base +
+				ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
+
+	/* set Rx BD address */
+	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
+			lower_32_bits(rx_bd_add));
+	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
+			upper_32_bits(rx_bd_add));
+	/* set Rx BD count (multiple of 8) */
+	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
+			rx_bdr->bd_count);
+	/* set Rx buffer  size */
+	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
+
+	/* fill Rx BD */
+	memset(priv->enetc_rxbd, 0,
+	       rx_bdr->bd_count * sizeof(union enetc_rx_bd));
+	for (i = 0; i < rx_bdr->bd_count; i++) {
+		priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
+		/* each RX buffer must be aligned to 64B */
+		WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
+	}
+
+	/* reset producer (ENETC owned) and consumer (SW owned) index */
+	enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
+	enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
+
+	/* enable Rx ring */
+	enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
+}
+
+/*
+ * Start ENETC interface:
+ * - perform FLR
+ * - enable access to port and SI registers
+ * - set mac address
+ * - setup TX/RX buffer descriptors
+ * - enable Tx/Rx rings
+ */
+static int enetc_start(struct udevice *dev)
+{
+	struct eth_pdata *plat = dev_get_platdata(dev);
+	struct enetc_priv *priv = dev_get_priv(dev);
+
+	/* reset and enable the PCI device */
+	dm_pci_flr(dev);
+	dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
+			       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+	if (!is_valid_ethaddr(plat->enetaddr)) {
+		enetc_dbg(dev, "invalid MAC address, generate random ...\n");
+		net_random_ethaddr(plat->enetaddr);
+	}
+	enetc_set_primary_mac_addr(priv, plat->enetaddr);
+
+	enetc_enable_si_port(priv);
+
+	/* setup Tx/Rx buffer descriptors */
+	enetc_setup_tx_bdr(dev);
+	enetc_setup_rx_bdr(dev);
+
+	return 0;
+}
+
+/*
+ * Stop the network interface:
+ * - just quiesce it, we can wipe all configuration as _start starts from
+ * scratch each time
+ */
+static void enetc_stop(struct udevice *dev)
+{
+	/* FLR is sufficient to quiesce the device */
+	dm_pci_flr(dev);
+}
+
+/*
+ * ENETC transmit packet:
+ * - check if Tx BD ring is full
+ * - set buffer/packet address (dma address)
+ * - set final fragment flag
+ * - try while producer index equals consumer index or timeout
+ */
+static int enetc_send(struct udevice *dev, void *packet, int length)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+	struct bd_ring *txr = &priv->tx_bdr;
+	void *nv_packet = (void *)packet;
+	int tries = ENETC_POLL_TRIES;
+	u32 pi, ci;
+
+	pi = txr->next_prod_idx;
+	ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
+	/* Tx ring is full when */
+	if (((pi + 1) % txr->bd_count) == ci) {
+		enetc_dbg(dev, "Tx BDR full\n");
+		return -ETIMEDOUT;
+	}
+	enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
+		  upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
+
+	/* prepare Tx BD */
+	memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
+	priv->enetc_txbd[pi].addr =
+		cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
+	priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
+	priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
+	priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
+	dmb();
+	/* send frame: increment producer index */
+	pi = (pi + 1) % txr->bd_count;
+	txr->next_prod_idx = pi;
+	enetc_write_reg(txr->prod_idx, pi);
+	while ((--tries >= 0) &&
+	       (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
+		udelay(10);
+
+	return tries > 0 ? 0 : -ETIMEDOUT;
+}
+
+/*
+ * Receive frame:
+ * - wait for the next BD to get ready bit set
+ * - clean up the descriptor
+ * - move on and indicate to HW that the cleaned BD is available for Rx
+ */
+static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+	struct enetc_priv *priv = dev_get_priv(dev);
+	struct bd_ring *rxr = &priv->rx_bdr;
+	int tries = ENETC_POLL_TRIES;
+	int pi = rxr->next_prod_idx;
+	int ci = rxr->next_cons_idx;
+	u32 status;
+	int len;
+	u8 rdy;
+
+	do {
+		dmb();
+		status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
+		/* check if current BD is ready to be consumed */
+		rdy = ENETC_RXBD_STATUS_R(status);
+	} while (--tries >= 0 && !rdy);
+
+	if (!rdy)
+		return -EAGAIN;
+
+	dmb();
+	len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
+	*packetp = (uchar *)enetc_rxb_address(dev, pi);
+	enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
+		  ENETC_RXBD_STATUS_ERRORS(status),
+		  upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
+
+	/* BD clean up and advance to next in ring */
+	memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
+	priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
+	rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
+	ci = (ci + 1) % rxr->bd_count;
+	rxr->next_cons_idx = ci;
+	dmb();
+	/* free up the slot in the ring for HW */
+	enetc_write_reg(rxr->cons_idx, ci);
+
+	return len;
+}
+
+static const struct eth_ops enetc_ops = {
+	.start	= enetc_start,
+	.send	= enetc_send,
+	.recv	= enetc_recv,
+	.stop	= enetc_stop,
+};
+
+U_BOOT_DRIVER(eth_enetc) = {
+	.name	= "enetc_eth",
+	.id	= UCLASS_ETH,
+	.bind	= enetc_bind,
+	.probe	= enetc_probe,
+	.remove = enetc_remove,
+	.ops	= &enetc_ops,
+	.priv_auto_alloc_size = sizeof(struct enetc_priv),
+	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
+static struct pci_device_id enetc_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
+	{}
+};
+
+U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * ENETC ethernet controller driver
+ * Copyright 2017-2019 NXP
+ */
+
+#ifndef _ENETC_H
+#define _ENETC_H
+
+#define enetc_dbg(dev, fmt, args...)	debug("%s:" fmt, dev->name, ##args)
+
+/* PCI function IDs */
+#define PCI_DEVICE_ID_ENETC_ETH		0xE100
+
+/* ENETC Ethernet controller registers */
+/* Station interface register offsets */
+#define ENETC_SIMR		0x000
+#define  ENETC_SIMR_EN		BIT(31)
+#define ENETC_SICAR0		0x040
+/* write cache cfg: snoop, no allocate, data & BD coherent */
+#define  ENETC_SICAR_WR_CFG	0x6767
+/* read cache cfg: coherent copy, look up, don't alloc in cache */
+#define  ENETC_SICAR_RD_CFG	0x27270000
+#define ENETC_SIROCT		0x300
+#define ENETC_SIRFRM		0x308
+#define ENETC_SITOCT		0x320
+#define ENETC_SITFRM		0x328
+
+/* Rx/Tx Buffer Descriptor Ring registers */
+enum enetc_bdr_type {TX, RX};
+#define ENETC_BDR(type, n, off)	(0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
+#define ENETC_BDR_IDX_MASK	0xffff
+
+/* Rx BDR reg offsets */
+#define ENETC_RBMR		0x00
+#define  ENETC_RBMR_EN		BIT(31)
+#define ENETC_RBBSR		0x08
+/* initial consumer index for Rx BDR */
+#define ENETC_RBCIR		0x0c
+#define ENETC_RBBAR0		0x10
+#define ENETC_RBBAR1		0x14
+#define ENETC_RBPIR		0x18
+#define ENETC_RBLENR		0x20
+
+/* Tx BDR reg offsets */
+#define ENETC_TBMR		0x00
+#define  ENETC_TBMR_EN		BIT(31)
+#define ENETC_TBBAR0		0x10
+#define ENETC_TBBAR1		0x14
+#define ENETC_TBPIR		0x18
+#define ENETC_TBCIR		0x1c
+#define ENETC_TBLENR		0x20
+
+/* Port registers offset */
+#define ENETC_PORT_REGS_OFF		0x10000
+
+/* Port registers */
+#define ENETC_PMR			0x0000
+#define  ENETC_PMR_SI0_EN		BIT(16)
+#define ENETC_PSIPMMR			0x0018
+#define ENETC_PSIPMAR0			0x0100
+#define ENETC_PSIPMAR1			0x0104
+#define ENETC_PSICFGR(n)		(0x0940 + (n) * 0x10)
+#define  ENETC_PSICFGR_SET_TXBDR(val)	((val) & 0xff)
+#define  ENETC_PSICFGR_SET_RXBDR(val)	(((val) & 0xff) << 16)
+/* MAC configuration */
+#define ENETC_PM_CC			0x8008
+#define  ENETC_PM_CC_DEFAULT		0x0810
+#define  ENETC_PM_CC_RX_TX_EN		0x8813
+#define ENETC_PM_MAXFRM			0x8014
+#define  ENETC_RX_MAXFRM_SIZE		PKTSIZE_ALIGN
+
+/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
+#define ENETC_BD_CNT		CONFIG_SYS_RX_ETH_BUFFER
+#define ENETC_BD_ALIGN		128
+
+/* single pair of Rx/Tx rings */
+#define ENETC_RX_BDR_CNT	1
+#define ENETC_TX_BDR_CNT	1
+#define ENETC_RX_BDR_ID		0
+#define ENETC_TX_BDR_ID		0
+
+/* Tx buffer descriptor */
+struct enetc_tx_bd {
+	__le64 addr;
+	__le16 buf_len;
+	__le16 frm_len;
+	__le16 err_csum;
+	__le16 flags;
+};
+
+#define ENETC_TXBD_FLAGS_F	BIT(15)
+#define ENETC_POLL_TRIES	32000
+
+/* Rx buffer descriptor */
+union enetc_rx_bd {
+	/* SW provided BD format */
+	struct {
+		__le64 addr;
+		u8 reserved[8];
+	} w;
+
+	/* ENETC returned BD format */
+	struct {
+		__le16 inet_csum;
+		__le16 parse_summary;
+		__le32 rss_hash;
+		__le16 buf_len;
+		__le16 vlan_opt;
+		union {
+			struct {
+				__le16 flags;
+				__le16 error;
+			};
+			__le32 lstatus;
+		};
+	} r;
+};
+
+#define ENETC_RXBD_STATUS_R(status)		(((status) >> 30) & 0x1)
+#define ENETC_RXBD_STATUS_F(status)		(((status) >> 31) & 0x1)
+#define ENETC_RXBD_STATUS_ERRORS(status)	(((status) >> 16) & 0xff)
+#define ENETC_RXBD_STATUS(flags)		((flags) << 16)
+
+/* Tx/Rx ring info */
+struct bd_ring {
+	void *cons_idx;
+	void *prod_idx;
+	/* next BD index to use */
+	int next_prod_idx;
+	int next_cons_idx;
+	int bd_count;
+};
+
+/* ENETC private structure */
+struct enetc_priv {
+	struct enetc_tx_bd *enetc_txbd;
+	union enetc_rx_bd *enetc_rxbd;
+
+	void *regs_base; /* base ENETC registers */
+	void *port_regs; /* base ENETC port registers */
+
+	/* Rx/Tx buffer descriptor rings info */
+	struct bd_ring tx_bdr;
+	struct bd_ring rx_bdr;
+};
+
+/* register accessors */
+#define enetc_read_reg(x)	readl((x))
+#define enetc_write_reg(x, val)	writel((val), (x))
+#define enetc_read(priv, off)	enetc_read_reg((priv)->regs_base + (off))
+#define enetc_write(priv, off, v) \
+			enetc_write_reg((priv)->regs_base + (off), v)
+
+/* port register accessors */
+#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
+#define enetc_read_port(priv, off) \
+			enetc_read_reg(enetc_port_regs((priv), (off)))
+#define enetc_write_port(priv, off, v) \
+			enetc_write_reg(enetc_port_regs((priv), (off)), v)
+
+/* BDR register accessors, see ENETC_BDR() */
+#define enetc_bdr_read(priv, t, n, off) \
+			enetc_read(priv, ENETC_BDR(t, n, off))
+#define enetc_bdr_write(priv, t, n, off, val) \
+			enetc_write(priv, ENETC_BDR(t, n, off), val)
+
+#endif /* _ENETC_H */
...	...	@@ -588,5 +588,12 @@
588	588	This driver supports HIGMACV300 Ethernet controller found on
589	589	HiSilicon SoCs.
590	590
	591	+config FSL_ENETC
	592	+ bool "NXP ENETC Ethernet controller"
	593	+ depends on DM_PCI && DM_ETH
	594	+ help
	595	+ This driver supports the NXP ENETC Ethernet controller found on some
	596	+ of the NXP SoCs.
	597	+
591	598	endif # NETDEVICES
...	...	@@ -79,4 +79,5 @@
79	79	obj-y += mscc_eswitch/
80	80	obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
81	81	obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
	82	+obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * ENETC ethernet controller driver
	4	+ * Copyright 2017-2019 NXP
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <dm.h>
	9	+#include <errno.h>
	10	+#include <memalign.h>
	11	+#include <asm/io.h>
	12	+#include <pci.h>
	13	+
	14	+#include "fsl_enetc.h"
	15	+
	16	+/*
	17	+ * Bind the device:
	18	+ * - set a more explicit name on the interface
	19	+ */
	20	+static int enetc_bind(struct udevice *dev)
	21	+{
	22	+ char name[16];
	23	+ static int eth_num_devices;
	24	+
	25	+ /*
	26	+ * prefer using PCI function numbers to number interfaces, but these
	27	+ * are only available if dts nodes are present. For PCI they are
	28	+ * optional, handle that case too. Just in case some nodes are present
	29	+ * and some are not, use different naming scheme - enetc-N based on
	30	+ * PCI function # and enetc#N based on interface count
	31	+ */
	32	+ if (ofnode_valid(dev->node))
	33	+ sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
	34	+ else
	35	+ sprintf(name, "enetc#%u", eth_num_devices++);
	36	+ device_set_name(dev, name);
	37	+
	38	+ return 0;
	39	+}
	40	+
	41	+/*
	42	+ * Probe ENETC driver:
	43	+ * - initialize port and station interface BARs
	44	+ */
	45	+static int enetc_probe(struct udevice *dev)
	46	+{
	47	+ struct enetc_priv *priv = dev_get_priv(dev);
	48	+
	49	+ if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
	50	+ enetc_dbg(dev, "interface disabled\n");
	51	+ return -ENODEV;
	52	+ }
	53	+
	54	+ priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
	55	+ sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
	56	+ priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
	57	+ sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
	58	+
	59	+ if (!priv->enetc_txbd \|\| !priv->enetc_rxbd) {
	60	+ /* free should be able to handle NULL, just free all pointers */
	61	+ free(priv->enetc_txbd);
	62	+ free(priv->enetc_rxbd);
	63	+
	64	+ return -ENOMEM;
	65	+ }
	66	+
	67	+ /* initialize register */
	68	+ priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
	69	+ if (!priv->regs_base) {
	70	+ enetc_dbg(dev, "failed to map BAR0\n");
	71	+ return -EINVAL;
	72	+ }
	73	+ priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
	74	+
	75	+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
	76	+
	77	+ return 0;
	78	+}
	79	+
	80	+/*
	81	+ * Remove the driver from an interface:
	82	+ * - free up allocated memory
	83	+ */
	84	+static int enetc_remove(struct udevice *dev)
	85	+{
	86	+ struct enetc_priv *priv = dev_get_priv(dev);
	87	+
	88	+ free(priv->enetc_txbd);
	89	+ free(priv->enetc_rxbd);
	90	+
	91	+ return 0;
	92	+}
	93	+
	94	+/* ENETC Port MAC address registers, accepts big-endian format */
	95	+static void enetc_set_primary_mac_addr(struct enetc_priv priv, const u8 addr)
	96	+{
	97	+ u16 lower = (const u16 )(addr + 4);
	98	+ u32 upper = (const u32 )addr;
	99	+
	100	+ enetc_write_port(priv, ENETC_PSIPMAR0, upper);
	101	+ enetc_write_port(priv, ENETC_PSIPMAR1, lower);
	102	+}
	103	+
	104	+/* Configure port parameters (# of rings, frame size, enable port) */
	105	+static void enetc_enable_si_port(struct enetc_priv *priv)
	106	+{
	107	+ u32 val;
	108	+
	109	+ /* set Rx/Tx BDR count */
	110	+ val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
	111	+ val \|= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
	112	+ enetc_write_port(priv, ENETC_PSICFGR(0), val);
	113	+ /* set Rx max frame size */
	114	+ enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
	115	+ /* enable MAC port */
	116	+ enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
	117	+ /* enable port */
	118	+ enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
	119	+ /* set SI cache policy */
	120	+ enetc_write(priv, ENETC_SICAR0,
	121	+ ENETC_SICAR_RD_CFG \| ENETC_SICAR_WR_CFG);
	122	+ /* enable SI */
	123	+ enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
	124	+}
	125	+
	126	+/* returns DMA address for a given buffer index */
	127	+static inline u64 enetc_rxb_address(struct udevice *dev, int i)
	128	+{
	129	+ return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
	130	+}
	131	+
	132	+/*
	133	+ * Setup a single Tx BD Ring (ID = 0):
	134	+ * - set Tx buffer descriptor address
	135	+ * - set the BD count
	136	+ * - initialize the producer and consumer index
	137	+ */
	138	+static void enetc_setup_tx_bdr(struct udevice *dev)
	139	+{
	140	+ struct enetc_priv *priv = dev_get_priv(dev);
	141	+ struct bd_ring *tx_bdr = &priv->tx_bdr;
	142	+ u64 tx_bd_add = (u64)priv->enetc_txbd;
	143	+
	144	+ /* used later to advance to the next Tx BD */
	145	+ tx_bdr->bd_count = ENETC_BD_CNT;
	146	+ tx_bdr->next_prod_idx = 0;
	147	+ tx_bdr->next_cons_idx = 0;
	148	+ tx_bdr->cons_idx = priv->regs_base +
	149	+ ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
	150	+ tx_bdr->prod_idx = priv->regs_base +
	151	+ ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
	152	+
	153	+ /* set Tx BD address */
	154	+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
	155	+ lower_32_bits(tx_bd_add));
	156	+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
	157	+ upper_32_bits(tx_bd_add));
	158	+ /* set Tx 8 BD count */
	159	+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
	160	+ tx_bdr->bd_count);
	161	+
	162	+ /* reset both producer/consumer indexes */
	163	+ enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
	164	+ enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
	165	+
	166	+ /* enable TX ring */
	167	+ enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
	168	+}
	169	+
	170	+/*
	171	+ * Setup a single Rx BD Ring (ID = 0):
	172	+ * - set Rx buffer descriptors address (one descriptor per buffer)
	173	+ * - set buffer size as max frame size
	174	+ * - enable Rx ring
	175	+ * - reset consumer and producer indexes
	176	+ * - set buffer for each descriptor
	177	+ */
	178	+static void enetc_setup_rx_bdr(struct udevice *dev)
	179	+{
	180	+ struct enetc_priv *priv = dev_get_priv(dev);
	181	+ struct bd_ring *rx_bdr = &priv->rx_bdr;
	182	+ u64 rx_bd_add = (u64)priv->enetc_rxbd;
	183	+ int i;
	184	+
	185	+ /* used later to advance to the next BD produced by ENETC HW */
	186	+ rx_bdr->bd_count = ENETC_BD_CNT;
	187	+ rx_bdr->next_prod_idx = 0;
	188	+ rx_bdr->next_cons_idx = 0;
	189	+ rx_bdr->cons_idx = priv->regs_base +
	190	+ ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
	191	+ rx_bdr->prod_idx = priv->regs_base +
	192	+ ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
	193	+
	194	+ /* set Rx BD address */
	195	+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
	196	+ lower_32_bits(rx_bd_add));
	197	+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
	198	+ upper_32_bits(rx_bd_add));
	199	+ /* set Rx BD count (multiple of 8) */
	200	+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
	201	+ rx_bdr->bd_count);
	202	+ /* set Rx buffer size */
	203	+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
	204	+
	205	+ /* fill Rx BD */
	206	+ memset(priv->enetc_rxbd, 0,
	207	+ rx_bdr->bd_count * sizeof(union enetc_rx_bd));
	208	+ for (i = 0; i < rx_bdr->bd_count; i++) {
	209	+ priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
	210	+ /* each RX buffer must be aligned to 64B */
	211	+ WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
	212	+ }
	213	+
	214	+ /* reset producer (ENETC owned) and consumer (SW owned) index */
	215	+ enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
	216	+ enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
	217	+
	218	+ /* enable Rx ring */
	219	+ enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
	220	+}
	221	+
	222	+/*
	223	+ * Start ENETC interface:
	224	+ * - perform FLR
	225	+ * - enable access to port and SI registers
	226	+ * - set mac address
	227	+ * - setup TX/RX buffer descriptors
	228	+ * - enable Tx/Rx rings
	229	+ */
	230	+static int enetc_start(struct udevice *dev)
	231	+{
	232	+ struct eth_pdata *plat = dev_get_platdata(dev);
	233	+ struct enetc_priv *priv = dev_get_priv(dev);
	234	+
	235	+ /* reset and enable the PCI device */
	236	+ dm_pci_flr(dev);
	237	+ dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
	238	+ PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
	239	+
	240	+ if (!is_valid_ethaddr(plat->enetaddr)) {
	241	+ enetc_dbg(dev, "invalid MAC address, generate random ...\n");
	242	+ net_random_ethaddr(plat->enetaddr);
	243	+ }
	244	+ enetc_set_primary_mac_addr(priv, plat->enetaddr);
	245	+
	246	+ enetc_enable_si_port(priv);
	247	+
	248	+ /* setup Tx/Rx buffer descriptors */
	249	+ enetc_setup_tx_bdr(dev);
	250	+ enetc_setup_rx_bdr(dev);
	251	+
	252	+ return 0;
	253	+}
	254	+
	255	+/*
	256	+ * Stop the network interface:
	257	+ * - just quiesce it, we can wipe all configuration as _start starts from
	258	+ * scratch each time
	259	+ */
	260	+static void enetc_stop(struct udevice *dev)
	261	+{
	262	+ /* FLR is sufficient to quiesce the device */
	263	+ dm_pci_flr(dev);
	264	+}
	265	+
	266	+/*
	267	+ * ENETC transmit packet:
	268	+ * - check if Tx BD ring is full
	269	+ * - set buffer/packet address (dma address)
	270	+ * - set final fragment flag
	271	+ * - try while producer index equals consumer index or timeout
	272	+ */
	273	+static int enetc_send(struct udevice dev, void packet, int length)
	274	+{
	275	+ struct enetc_priv *priv = dev_get_priv(dev);
	276	+ struct bd_ring *txr = &priv->tx_bdr;
	277	+ void nv_packet = (void )packet;
	278	+ int tries = ENETC_POLL_TRIES;
	279	+ u32 pi, ci;
	280	+
	281	+ pi = txr->next_prod_idx;
	282	+ ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
	283	+ /* Tx ring is full when */
	284	+ if (((pi + 1) % txr->bd_count) == ci) {
	285	+ enetc_dbg(dev, "Tx BDR full\n");
	286	+ return -ETIMEDOUT;
	287	+ }
	288	+ enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
	289	+ upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
	290	+
	291	+ /* prepare Tx BD */
	292	+ memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
	293	+ priv->enetc_txbd[pi].addr =
	294	+ cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
	295	+ priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
	296	+ priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
	297	+ priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
	298	+ dmb();
	299	+ /* send frame: increment producer index */
	300	+ pi = (pi + 1) % txr->bd_count;
	301	+ txr->next_prod_idx = pi;
	302	+ enetc_write_reg(txr->prod_idx, pi);
	303	+ while ((--tries >= 0) &&
	304	+ (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
	305	+ udelay(10);
	306	+
	307	+ return tries > 0 ? 0 : -ETIMEDOUT;
	308	+}
	309	+
	310	+/*
	311	+ * Receive frame:
	312	+ * - wait for the next BD to get ready bit set
	313	+ * - clean up the descriptor
	314	+ * - move on and indicate to HW that the cleaned BD is available for Rx
	315	+ */
	316	+static int enetc_recv(struct udevice dev, int flags, uchar *packetp)
	317	+{
	318	+ struct enetc_priv *priv = dev_get_priv(dev);
	319	+ struct bd_ring *rxr = &priv->rx_bdr;
	320	+ int tries = ENETC_POLL_TRIES;
	321	+ int pi = rxr->next_prod_idx;
	322	+ int ci = rxr->next_cons_idx;
	323	+ u32 status;
	324	+ int len;
	325	+ u8 rdy;
	326	+
	327	+ do {
	328	+ dmb();
	329	+ status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
	330	+ /* check if current BD is ready to be consumed */
	331	+ rdy = ENETC_RXBD_STATUS_R(status);
	332	+ } while (--tries >= 0 && !rdy);
	333	+
	334	+ if (!rdy)
	335	+ return -EAGAIN;
	336	+
	337	+ dmb();
	338	+ len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
	339	+ packetp = (uchar )enetc_rxb_address(dev, pi);
	340	+ enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
	341	+ ENETC_RXBD_STATUS_ERRORS(status),
	342	+ upper_32_bits((u64)packetp), lower_32_bits((u64)packetp));
	343	+
	344	+ /* BD clean up and advance to next in ring */
	345	+ memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
	346	+ priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
	347	+ rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
	348	+ ci = (ci + 1) % rxr->bd_count;
	349	+ rxr->next_cons_idx = ci;
	350	+ dmb();
	351	+ /* free up the slot in the ring for HW */
	352	+ enetc_write_reg(rxr->cons_idx, ci);
	353	+
	354	+ return len;
	355	+}
	356	+
	357	+static const struct eth_ops enetc_ops = {
	358	+ .start = enetc_start,
	359	+ .send = enetc_send,
	360	+ .recv = enetc_recv,
	361	+ .stop = enetc_stop,
	362	+};
	363	+
	364	+U_BOOT_DRIVER(eth_enetc) = {
	365	+ .name = "enetc_eth",
	366	+ .id = UCLASS_ETH,
	367	+ .bind = enetc_bind,
	368	+ .probe = enetc_probe,
	369	+ .remove = enetc_remove,
	370	+ .ops = &enetc_ops,
	371	+ .priv_auto_alloc_size = sizeof(struct enetc_priv),
	372	+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
	373	+};
	374	+
	375	+static struct pci_device_id enetc_ids[] = {
	376	+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
	377	+ {}
	378	+};
	379	+
	380	+U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
	2	+/*
	3	+ * ENETC ethernet controller driver
	4	+ * Copyright 2017-2019 NXP
	5	+ */
	6	+
	7	+#ifndef _ENETC_H
	8	+#define _ENETC_H
	9	+
	10	+#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
	11	+
	12	+/* PCI function IDs */
	13	+#define PCI_DEVICE_ID_ENETC_ETH 0xE100
	14	+
	15	+/* ENETC Ethernet controller registers */
	16	+/* Station interface register offsets */
	17	+#define ENETC_SIMR 0x000
	18	+#define ENETC_SIMR_EN BIT(31)
	19	+#define ENETC_SICAR0 0x040
	20	+/* write cache cfg: snoop, no allocate, data & BD coherent */
	21	+#define ENETC_SICAR_WR_CFG 0x6767
	22	+/* read cache cfg: coherent copy, look up, don't alloc in cache */
	23	+#define ENETC_SICAR_RD_CFG 0x27270000
	24	+#define ENETC_SIROCT 0x300
	25	+#define ENETC_SIRFRM 0x308
	26	+#define ENETC_SITOCT 0x320
	27	+#define ENETC_SITFRM 0x328
	28	+
	29	+/* Rx/Tx Buffer Descriptor Ring registers */
	30	+enum enetc_bdr_type {TX, RX};
	31	+#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
	32	+#define ENETC_BDR_IDX_MASK 0xffff
	33	+
	34	+/* Rx BDR reg offsets */
	35	+#define ENETC_RBMR 0x00
	36	+#define ENETC_RBMR_EN BIT(31)
	37	+#define ENETC_RBBSR 0x08
	38	+/* initial consumer index for Rx BDR */
	39	+#define ENETC_RBCIR 0x0c
	40	+#define ENETC_RBBAR0 0x10
	41	+#define ENETC_RBBAR1 0x14
	42	+#define ENETC_RBPIR 0x18
	43	+#define ENETC_RBLENR 0x20
	44	+
	45	+/* Tx BDR reg offsets */
	46	+#define ENETC_TBMR 0x00
	47	+#define ENETC_TBMR_EN BIT(31)
	48	+#define ENETC_TBBAR0 0x10
	49	+#define ENETC_TBBAR1 0x14
	50	+#define ENETC_TBPIR 0x18
	51	+#define ENETC_TBCIR 0x1c
	52	+#define ENETC_TBLENR 0x20
	53	+
	54	+/* Port registers offset */
	55	+#define ENETC_PORT_REGS_OFF 0x10000
	56	+
	57	+/* Port registers */
	58	+#define ENETC_PMR 0x0000
	59	+#define ENETC_PMR_SI0_EN BIT(16)
	60	+#define ENETC_PSIPMMR 0x0018
	61	+#define ENETC_PSIPMAR0 0x0100
	62	+#define ENETC_PSIPMAR1 0x0104
	63	+#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
	64	+#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
	65	+#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
	66	+/* MAC configuration */
	67	+#define ENETC_PM_CC 0x8008
	68	+#define ENETC_PM_CC_DEFAULT 0x0810
	69	+#define ENETC_PM_CC_RX_TX_EN 0x8813
	70	+#define ENETC_PM_MAXFRM 0x8014
	71	+#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
	72	+
	73	+/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
	74	+#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
	75	+#define ENETC_BD_ALIGN 128
	76	+
	77	+/* single pair of Rx/Tx rings */
	78	+#define ENETC_RX_BDR_CNT 1
	79	+#define ENETC_TX_BDR_CNT 1
	80	+#define ENETC_RX_BDR_ID 0
	81	+#define ENETC_TX_BDR_ID 0
	82	+
	83	+/* Tx buffer descriptor */
	84	+struct enetc_tx_bd {
	85	+ __le64 addr;
	86	+ __le16 buf_len;
	87	+ __le16 frm_len;
	88	+ __le16 err_csum;
	89	+ __le16 flags;
	90	+};
	91	+
	92	+#define ENETC_TXBD_FLAGS_F BIT(15)
	93	+#define ENETC_POLL_TRIES 32000
	94	+
	95	+/* Rx buffer descriptor */
	96	+union enetc_rx_bd {
	97	+ /* SW provided BD format */
	98	+ struct {
	99	+ __le64 addr;
	100	+ u8 reserved[8];
	101	+ } w;
	102	+
	103	+ /* ENETC returned BD format */
	104	+ struct {
	105	+ __le16 inet_csum;
	106	+ __le16 parse_summary;
	107	+ __le32 rss_hash;
	108	+ __le16 buf_len;
	109	+ __le16 vlan_opt;
	110	+ union {
	111	+ struct {
	112	+ __le16 flags;
	113	+ __le16 error;
	114	+ };
	115	+ __le32 lstatus;
	116	+ };
	117	+ } r;
	118	+};
	119	+
	120	+#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
	121	+#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
	122	+#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
	123	+#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
	124	+
	125	+/* Tx/Rx ring info */
	126	+struct bd_ring {
	127	+ void *cons_idx;
	128	+ void *prod_idx;
	129	+ /* next BD index to use */
	130	+ int next_prod_idx;
	131	+ int next_cons_idx;
	132	+ int bd_count;
	133	+};
	134	+
	135	+/* ENETC private structure */
	136	+struct enetc_priv {
	137	+ struct enetc_tx_bd *enetc_txbd;
	138	+ union enetc_rx_bd *enetc_rxbd;
	139	+
	140	+ void regs_base; / base ENETC registers */
	141	+ void port_regs; / base ENETC port registers */
	142	+
	143	+ /* Rx/Tx buffer descriptor rings info */
	144	+ struct bd_ring tx_bdr;
	145	+ struct bd_ring rx_bdr;
	146	+};
	147	+
	148	+/* register accessors */
	149	+#define enetc_read_reg(x) readl((x))
	150	+#define enetc_write_reg(x, val) writel((val), (x))
	151	+#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
	152	+#define enetc_write(priv, off, v) \
	153	+ enetc_write_reg((priv)->regs_base + (off), v)
	154	+
	155	+/* port register accessors */
	156	+#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
	157	+#define enetc_read_port(priv, off) \
	158	+ enetc_read_reg(enetc_port_regs((priv), (off)))
	159	+#define enetc_write_port(priv, off, v) \
	160	+ enetc_write_reg(enetc_port_regs((priv), (off)), v)
	161	+
	162	+/* BDR register accessors, see ENETC_BDR() */
	163	+#define enetc_bdr_read(priv, t, n, off) \
	164	+ enetc_read(priv, ENETC_BDR(t, n, off))
	165	+#define enetc_bdr_write(priv, t, n, off, val) \
	166	+ enetc_write(priv, ENETC_BDR(t, n, off), val)
	167	+
	168	+#endif /* _ENETC_H */