Eric Lee / smarc-uboot

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Commit 12406ae247736bb6dfd4a92431caec33ab2a54d7

Authored by Kever Yang
Committed by Simon Glass
1 parent ce26e8a1dd
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

rk_pwm: use clock framework API to get module clock 

This patch use clock API instead of hardcode for get pwm clock.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix printf() to debug() nit:
Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 14 additions and 3 deletions Side-by-side Diff

drivers/pwm/rk_pwm.c
Diff comments   View file @ 12406ae
... ... @@ -6,6 +6,7 @@
6 6 */
7 7  
8 8 #include <common.h>
  9 +#include <clk.h>
9 10 #include <div64.h>
10 11 #include <dm.h>
11 12 #include <pwm.h>
12 13  
... ... @@ -13,9 +14,9 @@
13 14 #include <syscon.h>
14 15 #include <asm/io.h>
15 16 #include <asm/arch/clock.h>
16   -#include <asm/arch/cru_rk3288.h>
17 17 #include <asm/arch/grf_rk3288.h>
18 18 #include <asm/arch/pwm.h>
  19 +#include <asm/arch/hardware.h>
19 20 #include <power/regulator.h>
20 21  
21 22 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -23,6 +24,7 @@
23 24 struct rk_pwm_priv {
24 25 struct rk3288_pwm *regs;
25 26 struct rk3288_grf *grf;
  27 + ulong freq;
26 28 };
27 29  
28 30 static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
... ... @@ -38,8 +40,8 @@
38 40 RK_PWM_DISABLE,
39 41 &regs->ctrl);
40 42  
41   - period = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * period_ns, 1000000);
42   - duty = lldiv((uint64_t)(PD_BUS_PCLK_HZ / 1000) * duty_ns, 1000000);
  43 + period = lldiv((uint64_t)(priv->freq / 1000) * period_ns, 1000000);
  44 + duty = lldiv((uint64_t)(priv->freq / 1000) * duty_ns, 1000000);
43 45  
44 46 writel(period, &regs->period_hpr);
45 47 writel(duty, &regs->duty_lpr);
46 48  
... ... @@ -76,8 +78,17 @@
76 78 static int rk_pwm_probe(struct udevice *dev)
77 79 {
78 80 struct rk_pwm_priv *priv = dev_get_priv(dev);
  81 + struct clk clk;
  82 + int ret = 0;
79 83  
80 84 rk_setreg(&priv->grf->soc_con2, 1 << 0);
  85 +
  86 + ret = clk_get_by_index(dev, 0, &clk);
  87 + if (ret < 0) {
  88 + debug("%s get clock fail!\n", __func__);
  89 + return -EINVAL;
  90 + }
  91 + priv->freq = clk_get_rate(&clk);
81 92  
82 93 return 0;
83 94 }